1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool ext_ifencei; 81 bool ext_zfh; 82 bool ext_zfhmin; 83 bool ext_zve32f; 84 bool ext_zve64f; 85 bool hlsx; 86 /* vector extension */ 87 bool vill; 88 /* 89 * Encode LMUL to lmul as follows: 90 * LMUL vlmul lmul 91 * 1 000 0 92 * 2 001 1 93 * 4 010 2 94 * 8 011 3 95 * - 100 - 96 * 1/8 101 -3 97 * 1/4 110 -2 98 * 1/2 111 -1 99 */ 100 int8_t lmul; 101 uint8_t sew; 102 uint16_t vlen; 103 uint16_t elen; 104 target_ulong vstart; 105 bool vl_eq_vlmax; 106 uint8_t ntemp; 107 CPUState *cs; 108 TCGv zero; 109 /* Space for 3 operands plus 1 extra for address computation. */ 110 TCGv temp[4]; 111 /* PointerMasking extension */ 112 bool pm_mask_enabled; 113 bool pm_base_enabled; 114 } DisasContext; 115 116 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 117 { 118 return ctx->misa_ext & ext; 119 } 120 121 #ifdef TARGET_RISCV32 122 #define get_xl(ctx) MXL_RV32 123 #elif defined(CONFIG_USER_ONLY) 124 #define get_xl(ctx) MXL_RV64 125 #else 126 #define get_xl(ctx) ((ctx)->xl) 127 #endif 128 129 /* The word size for this machine mode. */ 130 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 131 { 132 return 16 << get_xl(ctx); 133 } 134 135 /* The operation length, as opposed to the xlen. */ 136 #ifdef TARGET_RISCV32 137 #define get_ol(ctx) MXL_RV32 138 #else 139 #define get_ol(ctx) ((ctx)->ol) 140 #endif 141 142 static inline int get_olen(DisasContext *ctx) 143 { 144 return 16 << get_ol(ctx); 145 } 146 147 /* The maximum register length */ 148 #ifdef TARGET_RISCV32 149 #define get_xl_max(ctx) MXL_RV32 150 #else 151 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 152 #endif 153 154 /* 155 * RISC-V requires NaN-boxing of narrower width floating point values. 156 * This applies when a 32-bit value is assigned to a 64-bit FP register. 157 * For consistency and simplicity, we nanbox results even when the RVD 158 * extension is not present. 159 */ 160 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 161 { 162 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 163 } 164 165 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 166 { 167 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 168 } 169 170 /* 171 * A narrow n-bit operation, where n < FLEN, checks that input operands 172 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 173 * If so, the least-significant bits of the input are used, otherwise the 174 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 175 * 176 * Here, the result is always nan-boxed, even the canonical nan. 177 */ 178 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 179 { 180 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 181 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 182 183 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 184 tcg_temp_free_i64(t_max); 185 tcg_temp_free_i64(t_nan); 186 } 187 188 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 189 { 190 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 191 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 192 193 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 194 } 195 196 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 197 { 198 if (get_xl(ctx) == MXL_RV32) { 199 dest = (int32_t)dest; 200 } 201 tcg_gen_movi_tl(cpu_pc, dest); 202 } 203 204 static void gen_set_pc(DisasContext *ctx, TCGv dest) 205 { 206 if (get_xl(ctx) == MXL_RV32) { 207 tcg_gen_ext32s_tl(cpu_pc, dest); 208 } else { 209 tcg_gen_mov_tl(cpu_pc, dest); 210 } 211 } 212 213 static void generate_exception(DisasContext *ctx, int excp) 214 { 215 gen_set_pc_imm(ctx, ctx->base.pc_next); 216 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 217 ctx->base.is_jmp = DISAS_NORETURN; 218 } 219 220 static void generate_exception_mtval(DisasContext *ctx, int excp) 221 { 222 gen_set_pc_imm(ctx, ctx->base.pc_next); 223 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 224 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 225 ctx->base.is_jmp = DISAS_NORETURN; 226 } 227 228 static void gen_exception_illegal(DisasContext *ctx) 229 { 230 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 231 offsetof(CPURISCVState, bins)); 232 233 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 234 } 235 236 static void gen_exception_inst_addr_mis(DisasContext *ctx) 237 { 238 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 239 } 240 241 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 242 { 243 if (translator_use_goto_tb(&ctx->base, dest)) { 244 tcg_gen_goto_tb(n); 245 gen_set_pc_imm(ctx, dest); 246 tcg_gen_exit_tb(ctx->base.tb, n); 247 } else { 248 gen_set_pc_imm(ctx, dest); 249 tcg_gen_lookup_and_goto_ptr(); 250 } 251 } 252 253 /* 254 * Wrappers for getting reg values. 255 * 256 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 257 * constant zero as a source, and an uninitialized sink as destination. 258 * 259 * Further, we may provide an extension for word operations. 260 */ 261 static TCGv temp_new(DisasContext *ctx) 262 { 263 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 264 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 265 } 266 267 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 268 { 269 TCGv t; 270 271 if (reg_num == 0) { 272 return ctx->zero; 273 } 274 275 switch (get_ol(ctx)) { 276 case MXL_RV32: 277 switch (ext) { 278 case EXT_NONE: 279 break; 280 case EXT_SIGN: 281 t = temp_new(ctx); 282 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 283 return t; 284 case EXT_ZERO: 285 t = temp_new(ctx); 286 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 287 return t; 288 default: 289 g_assert_not_reached(); 290 } 291 break; 292 case MXL_RV64: 293 case MXL_RV128: 294 break; 295 default: 296 g_assert_not_reached(); 297 } 298 return cpu_gpr[reg_num]; 299 } 300 301 static TCGv get_gprh(DisasContext *ctx, int reg_num) 302 { 303 assert(get_xl(ctx) == MXL_RV128); 304 if (reg_num == 0) { 305 return ctx->zero; 306 } 307 return cpu_gprh[reg_num]; 308 } 309 310 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 311 { 312 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 313 return temp_new(ctx); 314 } 315 return cpu_gpr[reg_num]; 316 } 317 318 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 319 { 320 if (reg_num == 0) { 321 return temp_new(ctx); 322 } 323 return cpu_gprh[reg_num]; 324 } 325 326 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 327 { 328 if (reg_num != 0) { 329 switch (get_ol(ctx)) { 330 case MXL_RV32: 331 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 332 break; 333 case MXL_RV64: 334 case MXL_RV128: 335 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 336 break; 337 default: 338 g_assert_not_reached(); 339 } 340 341 if (get_xl_max(ctx) == MXL_RV128) { 342 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 343 } 344 } 345 } 346 347 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 348 { 349 if (reg_num != 0) { 350 switch (get_ol(ctx)) { 351 case MXL_RV32: 352 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 353 break; 354 case MXL_RV64: 355 case MXL_RV128: 356 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 357 break; 358 default: 359 g_assert_not_reached(); 360 } 361 362 if (get_xl_max(ctx) == MXL_RV128) { 363 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 364 } 365 } 366 } 367 368 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 369 { 370 assert(get_ol(ctx) == MXL_RV128); 371 if (reg_num != 0) { 372 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 373 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 374 } 375 } 376 377 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 378 { 379 target_ulong next_pc; 380 381 /* check misaligned: */ 382 next_pc = ctx->base.pc_next + imm; 383 if (!has_ext(ctx, RVC)) { 384 if ((next_pc & 0x3) != 0) { 385 gen_exception_inst_addr_mis(ctx); 386 return; 387 } 388 } 389 390 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 391 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 392 ctx->base.is_jmp = DISAS_NORETURN; 393 } 394 395 /* Compute a canonical address from a register plus offset. */ 396 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 397 { 398 TCGv addr = temp_new(ctx); 399 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 400 401 tcg_gen_addi_tl(addr, src1, imm); 402 if (ctx->pm_mask_enabled) { 403 tcg_gen_and_tl(addr, addr, pm_mask); 404 } else if (get_xl(ctx) == MXL_RV32) { 405 tcg_gen_ext32u_tl(addr, addr); 406 } 407 if (ctx->pm_base_enabled) { 408 tcg_gen_or_tl(addr, addr, pm_base); 409 } 410 return addr; 411 } 412 413 #ifndef CONFIG_USER_ONLY 414 /* The states of mstatus_fs are: 415 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 416 * We will have already diagnosed disabled state, 417 * and need to turn initial/clean into dirty. 418 */ 419 static void mark_fs_dirty(DisasContext *ctx) 420 { 421 TCGv tmp; 422 423 if (ctx->mstatus_fs != MSTATUS_FS) { 424 /* Remember the state change for the rest of the TB. */ 425 ctx->mstatus_fs = MSTATUS_FS; 426 427 tmp = tcg_temp_new(); 428 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 429 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 430 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 431 tcg_temp_free(tmp); 432 } 433 434 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 435 /* Remember the stage change for the rest of the TB. */ 436 ctx->mstatus_hs_fs = MSTATUS_FS; 437 438 tmp = tcg_temp_new(); 439 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 440 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 441 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 442 tcg_temp_free(tmp); 443 } 444 } 445 #else 446 static inline void mark_fs_dirty(DisasContext *ctx) { } 447 #endif 448 449 #ifndef CONFIG_USER_ONLY 450 /* The states of mstatus_vs are: 451 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 452 * We will have already diagnosed disabled state, 453 * and need to turn initial/clean into dirty. 454 */ 455 static void mark_vs_dirty(DisasContext *ctx) 456 { 457 TCGv tmp; 458 459 if (ctx->mstatus_vs != MSTATUS_VS) { 460 /* Remember the state change for the rest of the TB. */ 461 ctx->mstatus_vs = MSTATUS_VS; 462 463 tmp = tcg_temp_new(); 464 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 465 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 466 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 467 tcg_temp_free(tmp); 468 } 469 470 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 471 /* Remember the stage change for the rest of the TB. */ 472 ctx->mstatus_hs_vs = MSTATUS_VS; 473 474 tmp = tcg_temp_new(); 475 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 476 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 477 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 478 tcg_temp_free(tmp); 479 } 480 } 481 #else 482 static inline void mark_vs_dirty(DisasContext *ctx) { } 483 #endif 484 485 static void gen_set_rm(DisasContext *ctx, int rm) 486 { 487 if (ctx->frm == rm) { 488 return; 489 } 490 ctx->frm = rm; 491 492 if (rm == RISCV_FRM_ROD) { 493 gen_helper_set_rod_rounding_mode(cpu_env); 494 return; 495 } 496 497 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 498 } 499 500 static int ex_plus_1(DisasContext *ctx, int nf) 501 { 502 return nf + 1; 503 } 504 505 #define EX_SH(amount) \ 506 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 507 { \ 508 return imm << amount; \ 509 } 510 EX_SH(1) 511 EX_SH(2) 512 EX_SH(3) 513 EX_SH(4) 514 EX_SH(12) 515 516 #define REQUIRE_EXT(ctx, ext) do { \ 517 if (!has_ext(ctx, ext)) { \ 518 return false; \ 519 } \ 520 } while (0) 521 522 #define REQUIRE_32BIT(ctx) do { \ 523 if (get_xl(ctx) != MXL_RV32) { \ 524 return false; \ 525 } \ 526 } while (0) 527 528 #define REQUIRE_64BIT(ctx) do { \ 529 if (get_xl(ctx) != MXL_RV64) { \ 530 return false; \ 531 } \ 532 } while (0) 533 534 #define REQUIRE_128BIT(ctx) do { \ 535 if (get_xl(ctx) != MXL_RV128) { \ 536 return false; \ 537 } \ 538 } while (0) 539 540 #define REQUIRE_64_OR_128BIT(ctx) do { \ 541 if (get_xl(ctx) == MXL_RV32) { \ 542 return false; \ 543 } \ 544 } while (0) 545 546 static int ex_rvc_register(DisasContext *ctx, int reg) 547 { 548 return 8 + reg; 549 } 550 551 static int ex_rvc_shifti(DisasContext *ctx, int imm) 552 { 553 /* For RV128 a shamt of 0 means a shift by 64. */ 554 return imm ? imm : 64; 555 } 556 557 /* Include the auto-generated decoder for 32 bit insn */ 558 #include "decode-insn32.c.inc" 559 560 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 561 void (*func)(TCGv, TCGv, target_long)) 562 { 563 TCGv dest = dest_gpr(ctx, a->rd); 564 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 565 566 func(dest, src1, a->imm); 567 568 if (get_xl(ctx) == MXL_RV128) { 569 TCGv src1h = get_gprh(ctx, a->rs1); 570 TCGv desth = dest_gprh(ctx, a->rd); 571 572 func(desth, src1h, -(a->imm < 0)); 573 gen_set_gpr128(ctx, a->rd, dest, desth); 574 } else { 575 gen_set_gpr(ctx, a->rd, dest); 576 } 577 578 return true; 579 } 580 581 static bool gen_logic(DisasContext *ctx, arg_r *a, 582 void (*func)(TCGv, TCGv, TCGv)) 583 { 584 TCGv dest = dest_gpr(ctx, a->rd); 585 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 586 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 587 588 func(dest, src1, src2); 589 590 if (get_xl(ctx) == MXL_RV128) { 591 TCGv src1h = get_gprh(ctx, a->rs1); 592 TCGv src2h = get_gprh(ctx, a->rs2); 593 TCGv desth = dest_gprh(ctx, a->rd); 594 595 func(desth, src1h, src2h); 596 gen_set_gpr128(ctx, a->rd, dest, desth); 597 } else { 598 gen_set_gpr(ctx, a->rd, dest); 599 } 600 601 return true; 602 } 603 604 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 605 void (*func)(TCGv, TCGv, target_long), 606 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 607 { 608 TCGv dest = dest_gpr(ctx, a->rd); 609 TCGv src1 = get_gpr(ctx, a->rs1, ext); 610 611 if (get_ol(ctx) < MXL_RV128) { 612 func(dest, src1, a->imm); 613 gen_set_gpr(ctx, a->rd, dest); 614 } else { 615 if (f128 == NULL) { 616 return false; 617 } 618 619 TCGv src1h = get_gprh(ctx, a->rs1); 620 TCGv desth = dest_gprh(ctx, a->rd); 621 622 f128(dest, desth, src1, src1h, a->imm); 623 gen_set_gpr128(ctx, a->rd, dest, desth); 624 } 625 return true; 626 } 627 628 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 629 void (*func)(TCGv, TCGv, TCGv), 630 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 631 { 632 TCGv dest = dest_gpr(ctx, a->rd); 633 TCGv src1 = get_gpr(ctx, a->rs1, ext); 634 TCGv src2 = tcg_constant_tl(a->imm); 635 636 if (get_ol(ctx) < MXL_RV128) { 637 func(dest, src1, src2); 638 gen_set_gpr(ctx, a->rd, dest); 639 } else { 640 if (f128 == NULL) { 641 return false; 642 } 643 644 TCGv src1h = get_gprh(ctx, a->rs1); 645 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 646 TCGv desth = dest_gprh(ctx, a->rd); 647 648 f128(dest, desth, src1, src1h, src2, src2h); 649 gen_set_gpr128(ctx, a->rd, dest, desth); 650 } 651 return true; 652 } 653 654 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 655 void (*func)(TCGv, TCGv, TCGv), 656 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 657 { 658 TCGv dest = dest_gpr(ctx, a->rd); 659 TCGv src1 = get_gpr(ctx, a->rs1, ext); 660 TCGv src2 = get_gpr(ctx, a->rs2, ext); 661 662 if (get_ol(ctx) < MXL_RV128) { 663 func(dest, src1, src2); 664 gen_set_gpr(ctx, a->rd, dest); 665 } else { 666 if (f128 == NULL) { 667 return false; 668 } 669 670 TCGv src1h = get_gprh(ctx, a->rs1); 671 TCGv src2h = get_gprh(ctx, a->rs2); 672 TCGv desth = dest_gprh(ctx, a->rd); 673 674 f128(dest, desth, src1, src1h, src2, src2h); 675 gen_set_gpr128(ctx, a->rd, dest, desth); 676 } 677 return true; 678 } 679 680 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 681 void (*f_tl)(TCGv, TCGv, TCGv), 682 void (*f_32)(TCGv, TCGv, TCGv), 683 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 684 { 685 int olen = get_olen(ctx); 686 687 if (olen != TARGET_LONG_BITS) { 688 if (olen == 32) { 689 f_tl = f_32; 690 } else if (olen != 128) { 691 g_assert_not_reached(); 692 } 693 } 694 return gen_arith(ctx, a, ext, f_tl, f_128); 695 } 696 697 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 698 void (*func)(TCGv, TCGv, target_long), 699 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 700 { 701 TCGv dest, src1; 702 int max_len = get_olen(ctx); 703 704 if (a->shamt >= max_len) { 705 return false; 706 } 707 708 dest = dest_gpr(ctx, a->rd); 709 src1 = get_gpr(ctx, a->rs1, ext); 710 711 if (max_len < 128) { 712 func(dest, src1, a->shamt); 713 gen_set_gpr(ctx, a->rd, dest); 714 } else { 715 TCGv src1h = get_gprh(ctx, a->rs1); 716 TCGv desth = dest_gprh(ctx, a->rd); 717 718 if (f128 == NULL) { 719 return false; 720 } 721 f128(dest, desth, src1, src1h, a->shamt); 722 gen_set_gpr128(ctx, a->rd, dest, desth); 723 } 724 return true; 725 } 726 727 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 728 DisasExtend ext, 729 void (*f_tl)(TCGv, TCGv, target_long), 730 void (*f_32)(TCGv, TCGv, target_long), 731 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 732 target_long)) 733 { 734 int olen = get_olen(ctx); 735 if (olen != TARGET_LONG_BITS) { 736 if (olen == 32) { 737 f_tl = f_32; 738 } else if (olen != 128) { 739 g_assert_not_reached(); 740 } 741 } 742 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 743 } 744 745 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 746 void (*func)(TCGv, TCGv, TCGv)) 747 { 748 TCGv dest, src1, src2; 749 int max_len = get_olen(ctx); 750 751 if (a->shamt >= max_len) { 752 return false; 753 } 754 755 dest = dest_gpr(ctx, a->rd); 756 src1 = get_gpr(ctx, a->rs1, ext); 757 src2 = tcg_constant_tl(a->shamt); 758 759 func(dest, src1, src2); 760 761 gen_set_gpr(ctx, a->rd, dest); 762 return true; 763 } 764 765 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 766 void (*func)(TCGv, TCGv, TCGv), 767 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 768 { 769 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 770 TCGv ext2 = tcg_temp_new(); 771 int max_len = get_olen(ctx); 772 773 tcg_gen_andi_tl(ext2, src2, max_len - 1); 774 775 TCGv dest = dest_gpr(ctx, a->rd); 776 TCGv src1 = get_gpr(ctx, a->rs1, ext); 777 778 if (max_len < 128) { 779 func(dest, src1, ext2); 780 gen_set_gpr(ctx, a->rd, dest); 781 } else { 782 TCGv src1h = get_gprh(ctx, a->rs1); 783 TCGv desth = dest_gprh(ctx, a->rd); 784 785 if (f128 == NULL) { 786 return false; 787 } 788 f128(dest, desth, src1, src1h, ext2); 789 gen_set_gpr128(ctx, a->rd, dest, desth); 790 } 791 tcg_temp_free(ext2); 792 return true; 793 } 794 795 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 796 void (*f_tl)(TCGv, TCGv, TCGv), 797 void (*f_32)(TCGv, TCGv, TCGv), 798 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 799 { 800 int olen = get_olen(ctx); 801 if (olen != TARGET_LONG_BITS) { 802 if (olen == 32) { 803 f_tl = f_32; 804 } else if (olen != 128) { 805 g_assert_not_reached(); 806 } 807 } 808 return gen_shift(ctx, a, ext, f_tl, f_128); 809 } 810 811 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 812 void (*func)(TCGv, TCGv)) 813 { 814 TCGv dest = dest_gpr(ctx, a->rd); 815 TCGv src1 = get_gpr(ctx, a->rs1, ext); 816 817 func(dest, src1); 818 819 gen_set_gpr(ctx, a->rd, dest); 820 return true; 821 } 822 823 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 824 void (*f_tl)(TCGv, TCGv), 825 void (*f_32)(TCGv, TCGv)) 826 { 827 int olen = get_olen(ctx); 828 829 if (olen != TARGET_LONG_BITS) { 830 if (olen == 32) { 831 f_tl = f_32; 832 } else { 833 g_assert_not_reached(); 834 } 835 } 836 return gen_unary(ctx, a, ext, f_tl); 837 } 838 839 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 840 { 841 DisasContext *ctx = container_of(dcbase, DisasContext, base); 842 CPUState *cpu = ctx->cs; 843 CPURISCVState *env = cpu->env_ptr; 844 845 return cpu_ldl_code(env, pc); 846 } 847 848 /* Include insn module translation function */ 849 #include "insn_trans/trans_rvi.c.inc" 850 #include "insn_trans/trans_rvm.c.inc" 851 #include "insn_trans/trans_rva.c.inc" 852 #include "insn_trans/trans_rvf.c.inc" 853 #include "insn_trans/trans_rvd.c.inc" 854 #include "insn_trans/trans_rvh.c.inc" 855 #include "insn_trans/trans_rvv.c.inc" 856 #include "insn_trans/trans_rvb.c.inc" 857 #include "insn_trans/trans_rvzfh.c.inc" 858 #include "insn_trans/trans_privileged.c.inc" 859 860 /* Include the auto-generated decoder for 16 bit insn */ 861 #include "decode-insn16.c.inc" 862 863 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 864 { 865 /* check for compressed insn */ 866 if (extract16(opcode, 0, 2) != 3) { 867 if (!has_ext(ctx, RVC)) { 868 gen_exception_illegal(ctx); 869 } else { 870 ctx->opcode = opcode; 871 ctx->pc_succ_insn = ctx->base.pc_next + 2; 872 if (!decode_insn16(ctx, opcode)) { 873 gen_exception_illegal(ctx); 874 } 875 } 876 } else { 877 uint32_t opcode32 = opcode; 878 opcode32 = deposit32(opcode32, 16, 16, 879 translator_lduw(env, &ctx->base, 880 ctx->base.pc_next + 2)); 881 ctx->opcode = opcode32; 882 ctx->pc_succ_insn = ctx->base.pc_next + 4; 883 if (!decode_insn32(ctx, opcode32)) { 884 gen_exception_illegal(ctx); 885 } 886 } 887 } 888 889 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 890 { 891 DisasContext *ctx = container_of(dcbase, DisasContext, base); 892 CPURISCVState *env = cs->env_ptr; 893 RISCVCPU *cpu = RISCV_CPU(cs); 894 uint32_t tb_flags = ctx->base.tb->flags; 895 896 ctx->pc_succ_insn = ctx->base.pc_first; 897 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 898 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 899 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 900 ctx->priv_ver = env->priv_ver; 901 #if !defined(CONFIG_USER_ONLY) 902 if (riscv_has_ext(env, RVH)) { 903 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 904 } else { 905 ctx->virt_enabled = false; 906 } 907 #else 908 ctx->virt_enabled = false; 909 #endif 910 ctx->misa_ext = env->misa_ext; 911 ctx->frm = -1; /* unknown rounding mode */ 912 ctx->cfg_ptr = &(cpu->cfg); 913 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 914 ctx->ext_zfh = cpu->cfg.ext_zfh; 915 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; 916 ctx->ext_zve32f = cpu->cfg.ext_zve32f; 917 ctx->ext_zve64f = cpu->cfg.ext_zve64f; 918 ctx->vlen = cpu->cfg.vlen; 919 ctx->elen = cpu->cfg.elen; 920 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 921 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 922 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 923 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 924 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 925 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 926 ctx->vstart = env->vstart; 927 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 928 ctx->misa_mxl_max = env->misa_mxl_max; 929 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 930 ctx->cs = cs; 931 ctx->ntemp = 0; 932 memset(ctx->temp, 0, sizeof(ctx->temp)); 933 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 934 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 935 ctx->zero = tcg_constant_tl(0); 936 } 937 938 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 939 { 940 } 941 942 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 943 { 944 DisasContext *ctx = container_of(dcbase, DisasContext, base); 945 946 tcg_gen_insn_start(ctx->base.pc_next); 947 } 948 949 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 950 { 951 DisasContext *ctx = container_of(dcbase, DisasContext, base); 952 CPURISCVState *env = cpu->env_ptr; 953 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 954 955 ctx->ol = ctx->xl; 956 decode_opc(env, ctx, opcode16); 957 ctx->base.pc_next = ctx->pc_succ_insn; 958 959 for (int i = ctx->ntemp - 1; i >= 0; --i) { 960 tcg_temp_free(ctx->temp[i]); 961 ctx->temp[i] = NULL; 962 } 963 ctx->ntemp = 0; 964 965 if (ctx->base.is_jmp == DISAS_NEXT) { 966 target_ulong page_start; 967 968 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 969 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 970 ctx->base.is_jmp = DISAS_TOO_MANY; 971 } 972 } 973 } 974 975 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 976 { 977 DisasContext *ctx = container_of(dcbase, DisasContext, base); 978 979 switch (ctx->base.is_jmp) { 980 case DISAS_TOO_MANY: 981 gen_goto_tb(ctx, 0, ctx->base.pc_next); 982 break; 983 case DISAS_NORETURN: 984 break; 985 default: 986 g_assert_not_reached(); 987 } 988 } 989 990 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 991 { 992 #ifndef CONFIG_USER_ONLY 993 RISCVCPU *rvcpu = RISCV_CPU(cpu); 994 CPURISCVState *env = &rvcpu->env; 995 #endif 996 997 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 998 #ifndef CONFIG_USER_ONLY 999 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 1000 #endif 1001 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 1002 } 1003 1004 static const TranslatorOps riscv_tr_ops = { 1005 .init_disas_context = riscv_tr_init_disas_context, 1006 .tb_start = riscv_tr_tb_start, 1007 .insn_start = riscv_tr_insn_start, 1008 .translate_insn = riscv_tr_translate_insn, 1009 .tb_stop = riscv_tr_tb_stop, 1010 .disas_log = riscv_tr_disas_log, 1011 }; 1012 1013 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1014 { 1015 DisasContext ctx; 1016 1017 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1018 } 1019 1020 void riscv_translate_init(void) 1021 { 1022 int i; 1023 1024 /* 1025 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1026 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1027 * unless you specifically block reads/writes to reg 0. 1028 */ 1029 cpu_gpr[0] = NULL; 1030 cpu_gprh[0] = NULL; 1031 1032 for (i = 1; i < 32; i++) { 1033 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1034 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1035 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1036 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1037 } 1038 1039 for (i = 0; i < 32; i++) { 1040 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1041 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1042 } 1043 1044 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1045 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1046 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1047 "vstart"); 1048 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1049 "load_res"); 1050 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1051 "load_val"); 1052 /* Assign PM CSRs to tcg globals */ 1053 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1054 "pmmask"); 1055 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1056 "pmbase"); 1057 } 1058