1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 /* global register indices */ 37 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 38 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 39 static TCGv load_res; 40 static TCGv load_val; 41 /* globals for PM CSRs */ 42 static TCGv pm_mask; 43 static TCGv pm_base; 44 45 #include "exec/gen-icount.h" 46 47 /* 48 * If an operation is being performed on less than TARGET_LONG_BITS, 49 * it may require the inputs to be sign- or zero-extended; which will 50 * depend on the exact operation being performed. 51 */ 52 typedef enum { 53 EXT_NONE, 54 EXT_SIGN, 55 EXT_ZERO, 56 } DisasExtend; 57 58 typedef struct DisasContext { 59 DisasContextBase base; 60 /* pc_succ_insn points to the instruction following base.pc_next */ 61 target_ulong pc_succ_insn; 62 target_ulong priv_ver; 63 RISCVMXL misa_mxl_max; 64 RISCVMXL xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 uint32_t mstatus_fs; 68 uint32_t mstatus_vs; 69 uint32_t mstatus_hs_fs; 70 uint32_t mstatus_hs_vs; 71 uint32_t mem_idx; 72 /* Remember the rounding mode encoded in the previous fp instruction, 73 which we have already installed into env->fp_status. Or -1 for 74 no previous fp instruction. Note that we exit the TB when writing 75 to any system register, which includes CSR_FRM, so we do not have 76 to reset this known value. */ 77 int frm; 78 RISCVMXL ol; 79 bool virt_inst_excp; 80 bool virt_enabled; 81 const RISCVCPUConfig *cfg_ptr; 82 bool hlsx; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint8_t vta; 100 uint8_t vma; 101 bool cfg_vta_all_1s; 102 target_ulong vstart; 103 bool vl_eq_vlmax; 104 CPUState *cs; 105 TCGv zero; 106 /* PointerMasking extension */ 107 bool pm_mask_enabled; 108 bool pm_base_enabled; 109 /* Use icount trigger for native debug */ 110 bool itrigger; 111 /* FRM is known to contain a valid value. */ 112 bool frm_valid; 113 /* TCG of the current insn_start */ 114 TCGOp *insn_start; 115 } DisasContext; 116 117 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 118 { 119 return ctx->misa_ext & ext; 120 } 121 122 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 123 { 124 return true; 125 } 126 127 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) 128 { 129 return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || 130 ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || 131 ctx->cfg_ptr->ext_xtheadcondmov || 132 ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || 133 ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || 134 ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; 135 } 136 137 #define MATERIALISE_EXT_PREDICATE(ext) \ 138 static bool has_ ## ext ## _p(DisasContext *ctx) \ 139 { \ 140 return ctx->cfg_ptr->ext_ ## ext ; \ 141 } 142 143 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 144 145 #ifdef TARGET_RISCV32 146 #define get_xl(ctx) MXL_RV32 147 #elif defined(CONFIG_USER_ONLY) 148 #define get_xl(ctx) MXL_RV64 149 #else 150 #define get_xl(ctx) ((ctx)->xl) 151 #endif 152 153 /* The word size for this machine mode. */ 154 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 155 { 156 return 16 << get_xl(ctx); 157 } 158 159 /* The operation length, as opposed to the xlen. */ 160 #ifdef TARGET_RISCV32 161 #define get_ol(ctx) MXL_RV32 162 #else 163 #define get_ol(ctx) ((ctx)->ol) 164 #endif 165 166 static inline int get_olen(DisasContext *ctx) 167 { 168 return 16 << get_ol(ctx); 169 } 170 171 /* The maximum register length */ 172 #ifdef TARGET_RISCV32 173 #define get_xl_max(ctx) MXL_RV32 174 #else 175 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 176 #endif 177 178 /* 179 * RISC-V requires NaN-boxing of narrower width floating point values. 180 * This applies when a 32-bit value is assigned to a 64-bit FP register. 181 * For consistency and simplicity, we nanbox results even when the RVD 182 * extension is not present. 183 */ 184 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 185 { 186 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 187 } 188 189 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 190 { 191 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 192 } 193 194 /* 195 * A narrow n-bit operation, where n < FLEN, checks that input operands 196 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 197 * If so, the least-significant bits of the input are used, otherwise the 198 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 199 * 200 * Here, the result is always nan-boxed, even the canonical nan. 201 */ 202 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 203 { 204 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 205 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 206 207 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 208 } 209 210 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 211 { 212 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 213 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 214 215 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 216 } 217 218 static void decode_save_opc(DisasContext *ctx) 219 { 220 assert(ctx->insn_start != NULL); 221 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 222 ctx->insn_start = NULL; 223 } 224 225 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 226 { 227 if (get_xl(ctx) == MXL_RV32) { 228 dest = (int32_t)dest; 229 } 230 tcg_gen_movi_tl(cpu_pc, dest); 231 } 232 233 static void gen_set_pc(DisasContext *ctx, TCGv dest) 234 { 235 if (get_xl(ctx) == MXL_RV32) { 236 tcg_gen_ext32s_tl(cpu_pc, dest); 237 } else { 238 tcg_gen_mov_tl(cpu_pc, dest); 239 } 240 } 241 242 static void generate_exception(DisasContext *ctx, int excp) 243 { 244 gen_set_pc_imm(ctx, ctx->base.pc_next); 245 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 246 ctx->base.is_jmp = DISAS_NORETURN; 247 } 248 249 static void gen_exception_illegal(DisasContext *ctx) 250 { 251 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 252 offsetof(CPURISCVState, bins)); 253 if (ctx->virt_inst_excp) { 254 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 255 } else { 256 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 257 } 258 } 259 260 static void gen_exception_inst_addr_mis(DisasContext *ctx) 261 { 262 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 263 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 264 } 265 266 static void lookup_and_goto_ptr(DisasContext *ctx) 267 { 268 #ifndef CONFIG_USER_ONLY 269 if (ctx->itrigger) { 270 gen_helper_itrigger_match(cpu_env); 271 } 272 #endif 273 tcg_gen_lookup_and_goto_ptr(); 274 } 275 276 static void exit_tb(DisasContext *ctx) 277 { 278 #ifndef CONFIG_USER_ONLY 279 if (ctx->itrigger) { 280 gen_helper_itrigger_match(cpu_env); 281 } 282 #endif 283 tcg_gen_exit_tb(NULL, 0); 284 } 285 286 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 287 { 288 /* 289 * Under itrigger, instruction executes one by one like singlestep, 290 * direct block chain benefits will be small. 291 */ 292 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 293 tcg_gen_goto_tb(n); 294 gen_set_pc_imm(ctx, dest); 295 tcg_gen_exit_tb(ctx->base.tb, n); 296 } else { 297 gen_set_pc_imm(ctx, dest); 298 lookup_and_goto_ptr(ctx); 299 } 300 } 301 302 /* 303 * Wrappers for getting reg values. 304 * 305 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 306 * constant zero as a source, and an uninitialized sink as destination. 307 * 308 * Further, we may provide an extension for word operations. 309 */ 310 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 311 { 312 TCGv t; 313 314 if (reg_num == 0) { 315 return ctx->zero; 316 } 317 318 switch (get_ol(ctx)) { 319 case MXL_RV32: 320 switch (ext) { 321 case EXT_NONE: 322 break; 323 case EXT_SIGN: 324 t = tcg_temp_new(); 325 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 326 return t; 327 case EXT_ZERO: 328 t = tcg_temp_new(); 329 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 330 return t; 331 default: 332 g_assert_not_reached(); 333 } 334 break; 335 case MXL_RV64: 336 case MXL_RV128: 337 break; 338 default: 339 g_assert_not_reached(); 340 } 341 return cpu_gpr[reg_num]; 342 } 343 344 static TCGv get_gprh(DisasContext *ctx, int reg_num) 345 { 346 assert(get_xl(ctx) == MXL_RV128); 347 if (reg_num == 0) { 348 return ctx->zero; 349 } 350 return cpu_gprh[reg_num]; 351 } 352 353 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 354 { 355 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 356 return tcg_temp_new(); 357 } 358 return cpu_gpr[reg_num]; 359 } 360 361 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 362 { 363 if (reg_num == 0) { 364 return tcg_temp_new(); 365 } 366 return cpu_gprh[reg_num]; 367 } 368 369 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 370 { 371 if (reg_num != 0) { 372 switch (get_ol(ctx)) { 373 case MXL_RV32: 374 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 375 break; 376 case MXL_RV64: 377 case MXL_RV128: 378 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 379 break; 380 default: 381 g_assert_not_reached(); 382 } 383 384 if (get_xl_max(ctx) == MXL_RV128) { 385 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 386 } 387 } 388 } 389 390 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 391 { 392 if (reg_num != 0) { 393 switch (get_ol(ctx)) { 394 case MXL_RV32: 395 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 396 break; 397 case MXL_RV64: 398 case MXL_RV128: 399 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 400 break; 401 default: 402 g_assert_not_reached(); 403 } 404 405 if (get_xl_max(ctx) == MXL_RV128) { 406 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 407 } 408 } 409 } 410 411 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 412 { 413 assert(get_ol(ctx) == MXL_RV128); 414 if (reg_num != 0) { 415 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 416 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 417 } 418 } 419 420 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 421 { 422 if (!ctx->cfg_ptr->ext_zfinx) { 423 return cpu_fpr[reg_num]; 424 } 425 426 if (reg_num == 0) { 427 return tcg_constant_i64(0); 428 } 429 switch (get_xl(ctx)) { 430 case MXL_RV32: 431 #ifdef TARGET_RISCV32 432 { 433 TCGv_i64 t = tcg_temp_new_i64(); 434 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 435 return t; 436 } 437 #else 438 /* fall through */ 439 case MXL_RV64: 440 return cpu_gpr[reg_num]; 441 #endif 442 default: 443 g_assert_not_reached(); 444 } 445 } 446 447 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 448 { 449 if (!ctx->cfg_ptr->ext_zfinx) { 450 return cpu_fpr[reg_num]; 451 } 452 453 if (reg_num == 0) { 454 return tcg_constant_i64(0); 455 } 456 switch (get_xl(ctx)) { 457 case MXL_RV32: 458 { 459 TCGv_i64 t = tcg_temp_new_i64(); 460 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 461 return t; 462 } 463 #ifdef TARGET_RISCV64 464 case MXL_RV64: 465 return cpu_gpr[reg_num]; 466 #endif 467 default: 468 g_assert_not_reached(); 469 } 470 } 471 472 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 473 { 474 if (!ctx->cfg_ptr->ext_zfinx) { 475 return cpu_fpr[reg_num]; 476 } 477 478 if (reg_num == 0) { 479 return tcg_temp_new_i64(); 480 } 481 482 switch (get_xl(ctx)) { 483 case MXL_RV32: 484 return tcg_temp_new_i64(); 485 #ifdef TARGET_RISCV64 486 case MXL_RV64: 487 return cpu_gpr[reg_num]; 488 #endif 489 default: 490 g_assert_not_reached(); 491 } 492 } 493 494 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 495 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 496 { 497 if (!ctx->cfg_ptr->ext_zfinx) { 498 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 499 return; 500 } 501 if (reg_num != 0) { 502 switch (get_xl(ctx)) { 503 case MXL_RV32: 504 #ifdef TARGET_RISCV32 505 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 506 break; 507 #else 508 /* fall through */ 509 case MXL_RV64: 510 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 511 break; 512 #endif 513 default: 514 g_assert_not_reached(); 515 } 516 } 517 } 518 519 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 520 { 521 if (!ctx->cfg_ptr->ext_zfinx) { 522 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 523 return; 524 } 525 526 if (reg_num != 0) { 527 switch (get_xl(ctx)) { 528 case MXL_RV32: 529 #ifdef TARGET_RISCV32 530 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 531 break; 532 #else 533 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 534 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 535 break; 536 case MXL_RV64: 537 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 538 break; 539 #endif 540 default: 541 g_assert_not_reached(); 542 } 543 } 544 } 545 546 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 547 { 548 target_ulong next_pc; 549 550 /* check misaligned: */ 551 next_pc = ctx->base.pc_next + imm; 552 if (!ctx->cfg_ptr->ext_zca) { 553 if ((next_pc & 0x3) != 0) { 554 gen_exception_inst_addr_mis(ctx); 555 return; 556 } 557 } 558 559 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 560 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 561 ctx->base.is_jmp = DISAS_NORETURN; 562 } 563 564 /* Compute a canonical address from a register plus offset. */ 565 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 566 { 567 TCGv addr = tcg_temp_new(); 568 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 569 570 tcg_gen_addi_tl(addr, src1, imm); 571 if (ctx->pm_mask_enabled) { 572 tcg_gen_andc_tl(addr, addr, pm_mask); 573 } else if (get_xl(ctx) == MXL_RV32) { 574 tcg_gen_ext32u_tl(addr, addr); 575 } 576 if (ctx->pm_base_enabled) { 577 tcg_gen_or_tl(addr, addr, pm_base); 578 } 579 return addr; 580 } 581 582 /* Compute a canonical address from a register plus reg offset. */ 583 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 584 { 585 TCGv addr = tcg_temp_new(); 586 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 587 588 tcg_gen_add_tl(addr, src1, offs); 589 if (ctx->pm_mask_enabled) { 590 tcg_gen_andc_tl(addr, addr, pm_mask); 591 } else if (get_xl(ctx) == MXL_RV32) { 592 tcg_gen_ext32u_tl(addr, addr); 593 } 594 if (ctx->pm_base_enabled) { 595 tcg_gen_or_tl(addr, addr, pm_base); 596 } 597 return addr; 598 } 599 600 #ifndef CONFIG_USER_ONLY 601 /* The states of mstatus_fs are: 602 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 603 * We will have already diagnosed disabled state, 604 * and need to turn initial/clean into dirty. 605 */ 606 static void mark_fs_dirty(DisasContext *ctx) 607 { 608 TCGv tmp; 609 610 if (!has_ext(ctx, RVF)) { 611 return; 612 } 613 614 if (ctx->mstatus_fs != MSTATUS_FS) { 615 /* Remember the state change for the rest of the TB. */ 616 ctx->mstatus_fs = MSTATUS_FS; 617 618 tmp = tcg_temp_new(); 619 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 620 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 621 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 622 } 623 624 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 625 /* Remember the stage change for the rest of the TB. */ 626 ctx->mstatus_hs_fs = MSTATUS_FS; 627 628 tmp = tcg_temp_new(); 629 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 630 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 631 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 632 } 633 } 634 #else 635 static inline void mark_fs_dirty(DisasContext *ctx) { } 636 #endif 637 638 #ifndef CONFIG_USER_ONLY 639 /* The states of mstatus_vs are: 640 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 641 * We will have already diagnosed disabled state, 642 * and need to turn initial/clean into dirty. 643 */ 644 static void mark_vs_dirty(DisasContext *ctx) 645 { 646 TCGv tmp; 647 648 if (ctx->mstatus_vs != MSTATUS_VS) { 649 /* Remember the state change for the rest of the TB. */ 650 ctx->mstatus_vs = MSTATUS_VS; 651 652 tmp = tcg_temp_new(); 653 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 654 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 655 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 656 } 657 658 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 659 /* Remember the stage change for the rest of the TB. */ 660 ctx->mstatus_hs_vs = MSTATUS_VS; 661 662 tmp = tcg_temp_new(); 663 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 664 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 665 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 666 } 667 } 668 #else 669 static inline void mark_vs_dirty(DisasContext *ctx) { } 670 #endif 671 672 static void gen_set_rm(DisasContext *ctx, int rm) 673 { 674 if (ctx->frm == rm) { 675 return; 676 } 677 ctx->frm = rm; 678 679 if (rm == RISCV_FRM_DYN) { 680 /* The helper will return only if frm valid. */ 681 ctx->frm_valid = true; 682 } 683 684 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 685 decode_save_opc(ctx); 686 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 687 } 688 689 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 690 { 691 if (ctx->frm == rm && ctx->frm_valid) { 692 return; 693 } 694 ctx->frm = rm; 695 ctx->frm_valid = true; 696 697 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 698 decode_save_opc(ctx); 699 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 700 } 701 702 static int ex_plus_1(DisasContext *ctx, int nf) 703 { 704 return nf + 1; 705 } 706 707 #define EX_SH(amount) \ 708 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 709 { \ 710 return imm << amount; \ 711 } 712 EX_SH(1) 713 EX_SH(2) 714 EX_SH(3) 715 EX_SH(4) 716 EX_SH(12) 717 718 #define REQUIRE_EXT(ctx, ext) do { \ 719 if (!has_ext(ctx, ext)) { \ 720 return false; \ 721 } \ 722 } while (0) 723 724 #define REQUIRE_32BIT(ctx) do { \ 725 if (get_xl(ctx) != MXL_RV32) { \ 726 return false; \ 727 } \ 728 } while (0) 729 730 #define REQUIRE_64BIT(ctx) do { \ 731 if (get_xl(ctx) != MXL_RV64) { \ 732 return false; \ 733 } \ 734 } while (0) 735 736 #define REQUIRE_128BIT(ctx) do { \ 737 if (get_xl(ctx) != MXL_RV128) { \ 738 return false; \ 739 } \ 740 } while (0) 741 742 #define REQUIRE_64_OR_128BIT(ctx) do { \ 743 if (get_xl(ctx) == MXL_RV32) { \ 744 return false; \ 745 } \ 746 } while (0) 747 748 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 749 if (!ctx->cfg_ptr->ext_##A && \ 750 !ctx->cfg_ptr->ext_##B) { \ 751 return false; \ 752 } \ 753 } while (0) 754 755 static int ex_rvc_register(DisasContext *ctx, int reg) 756 { 757 return 8 + reg; 758 } 759 760 static int ex_sreg_register(DisasContext *ctx, int reg) 761 { 762 return reg < 2 ? reg + 8 : reg + 16; 763 } 764 765 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 766 { 767 /* For RV128 a shamt of 0 means a shift by 64. */ 768 if (get_ol(ctx) == MXL_RV128) { 769 imm = imm ? imm : 64; 770 } 771 return imm; 772 } 773 774 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 775 { 776 /* 777 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 778 * shifts, the shamt is sign-extended. 779 */ 780 if (get_ol(ctx) == MXL_RV128) { 781 imm = imm | (imm & 32) << 1; 782 imm = imm ? imm : 64; 783 } 784 return imm; 785 } 786 787 /* Include the auto-generated decoder for 32 bit insn */ 788 #include "decode-insn32.c.inc" 789 790 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 791 void (*func)(TCGv, TCGv, target_long)) 792 { 793 TCGv dest = dest_gpr(ctx, a->rd); 794 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 795 796 func(dest, src1, a->imm); 797 798 if (get_xl(ctx) == MXL_RV128) { 799 TCGv src1h = get_gprh(ctx, a->rs1); 800 TCGv desth = dest_gprh(ctx, a->rd); 801 802 func(desth, src1h, -(a->imm < 0)); 803 gen_set_gpr128(ctx, a->rd, dest, desth); 804 } else { 805 gen_set_gpr(ctx, a->rd, dest); 806 } 807 808 return true; 809 } 810 811 static bool gen_logic(DisasContext *ctx, arg_r *a, 812 void (*func)(TCGv, TCGv, TCGv)) 813 { 814 TCGv dest = dest_gpr(ctx, a->rd); 815 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 816 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 817 818 func(dest, src1, src2); 819 820 if (get_xl(ctx) == MXL_RV128) { 821 TCGv src1h = get_gprh(ctx, a->rs1); 822 TCGv src2h = get_gprh(ctx, a->rs2); 823 TCGv desth = dest_gprh(ctx, a->rd); 824 825 func(desth, src1h, src2h); 826 gen_set_gpr128(ctx, a->rd, dest, desth); 827 } else { 828 gen_set_gpr(ctx, a->rd, dest); 829 } 830 831 return true; 832 } 833 834 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 835 void (*func)(TCGv, TCGv, target_long), 836 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 837 { 838 TCGv dest = dest_gpr(ctx, a->rd); 839 TCGv src1 = get_gpr(ctx, a->rs1, ext); 840 841 if (get_ol(ctx) < MXL_RV128) { 842 func(dest, src1, a->imm); 843 gen_set_gpr(ctx, a->rd, dest); 844 } else { 845 if (f128 == NULL) { 846 return false; 847 } 848 849 TCGv src1h = get_gprh(ctx, a->rs1); 850 TCGv desth = dest_gprh(ctx, a->rd); 851 852 f128(dest, desth, src1, src1h, a->imm); 853 gen_set_gpr128(ctx, a->rd, dest, desth); 854 } 855 return true; 856 } 857 858 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 859 void (*func)(TCGv, TCGv, TCGv), 860 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 861 { 862 TCGv dest = dest_gpr(ctx, a->rd); 863 TCGv src1 = get_gpr(ctx, a->rs1, ext); 864 TCGv src2 = tcg_constant_tl(a->imm); 865 866 if (get_ol(ctx) < MXL_RV128) { 867 func(dest, src1, src2); 868 gen_set_gpr(ctx, a->rd, dest); 869 } else { 870 if (f128 == NULL) { 871 return false; 872 } 873 874 TCGv src1h = get_gprh(ctx, a->rs1); 875 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 876 TCGv desth = dest_gprh(ctx, a->rd); 877 878 f128(dest, desth, src1, src1h, src2, src2h); 879 gen_set_gpr128(ctx, a->rd, dest, desth); 880 } 881 return true; 882 } 883 884 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 885 void (*func)(TCGv, TCGv, TCGv), 886 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 887 { 888 TCGv dest = dest_gpr(ctx, a->rd); 889 TCGv src1 = get_gpr(ctx, a->rs1, ext); 890 TCGv src2 = get_gpr(ctx, a->rs2, ext); 891 892 if (get_ol(ctx) < MXL_RV128) { 893 func(dest, src1, src2); 894 gen_set_gpr(ctx, a->rd, dest); 895 } else { 896 if (f128 == NULL) { 897 return false; 898 } 899 900 TCGv src1h = get_gprh(ctx, a->rs1); 901 TCGv src2h = get_gprh(ctx, a->rs2); 902 TCGv desth = dest_gprh(ctx, a->rd); 903 904 f128(dest, desth, src1, src1h, src2, src2h); 905 gen_set_gpr128(ctx, a->rd, dest, desth); 906 } 907 return true; 908 } 909 910 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 911 void (*f_tl)(TCGv, TCGv, TCGv), 912 void (*f_32)(TCGv, TCGv, TCGv), 913 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 914 { 915 int olen = get_olen(ctx); 916 917 if (olen != TARGET_LONG_BITS) { 918 if (olen == 32) { 919 f_tl = f_32; 920 } else if (olen != 128) { 921 g_assert_not_reached(); 922 } 923 } 924 return gen_arith(ctx, a, ext, f_tl, f_128); 925 } 926 927 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 928 void (*func)(TCGv, TCGv, target_long), 929 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 930 { 931 TCGv dest, src1; 932 int max_len = get_olen(ctx); 933 934 if (a->shamt >= max_len) { 935 return false; 936 } 937 938 dest = dest_gpr(ctx, a->rd); 939 src1 = get_gpr(ctx, a->rs1, ext); 940 941 if (max_len < 128) { 942 func(dest, src1, a->shamt); 943 gen_set_gpr(ctx, a->rd, dest); 944 } else { 945 TCGv src1h = get_gprh(ctx, a->rs1); 946 TCGv desth = dest_gprh(ctx, a->rd); 947 948 if (f128 == NULL) { 949 return false; 950 } 951 f128(dest, desth, src1, src1h, a->shamt); 952 gen_set_gpr128(ctx, a->rd, dest, desth); 953 } 954 return true; 955 } 956 957 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 958 DisasExtend ext, 959 void (*f_tl)(TCGv, TCGv, target_long), 960 void (*f_32)(TCGv, TCGv, target_long), 961 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 962 target_long)) 963 { 964 int olen = get_olen(ctx); 965 if (olen != TARGET_LONG_BITS) { 966 if (olen == 32) { 967 f_tl = f_32; 968 } else if (olen != 128) { 969 g_assert_not_reached(); 970 } 971 } 972 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 973 } 974 975 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 976 void (*func)(TCGv, TCGv, TCGv)) 977 { 978 TCGv dest, src1, src2; 979 int max_len = get_olen(ctx); 980 981 if (a->shamt >= max_len) { 982 return false; 983 } 984 985 dest = dest_gpr(ctx, a->rd); 986 src1 = get_gpr(ctx, a->rs1, ext); 987 src2 = tcg_constant_tl(a->shamt); 988 989 func(dest, src1, src2); 990 991 gen_set_gpr(ctx, a->rd, dest); 992 return true; 993 } 994 995 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 996 void (*func)(TCGv, TCGv, TCGv), 997 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 998 { 999 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1000 TCGv ext2 = tcg_temp_new(); 1001 int max_len = get_olen(ctx); 1002 1003 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1004 1005 TCGv dest = dest_gpr(ctx, a->rd); 1006 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1007 1008 if (max_len < 128) { 1009 func(dest, src1, ext2); 1010 gen_set_gpr(ctx, a->rd, dest); 1011 } else { 1012 TCGv src1h = get_gprh(ctx, a->rs1); 1013 TCGv desth = dest_gprh(ctx, a->rd); 1014 1015 if (f128 == NULL) { 1016 return false; 1017 } 1018 f128(dest, desth, src1, src1h, ext2); 1019 gen_set_gpr128(ctx, a->rd, dest, desth); 1020 } 1021 return true; 1022 } 1023 1024 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1025 void (*f_tl)(TCGv, TCGv, TCGv), 1026 void (*f_32)(TCGv, TCGv, TCGv), 1027 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1028 { 1029 int olen = get_olen(ctx); 1030 if (olen != TARGET_LONG_BITS) { 1031 if (olen == 32) { 1032 f_tl = f_32; 1033 } else if (olen != 128) { 1034 g_assert_not_reached(); 1035 } 1036 } 1037 return gen_shift(ctx, a, ext, f_tl, f_128); 1038 } 1039 1040 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1041 void (*func)(TCGv, TCGv)) 1042 { 1043 TCGv dest = dest_gpr(ctx, a->rd); 1044 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1045 1046 func(dest, src1); 1047 1048 gen_set_gpr(ctx, a->rd, dest); 1049 return true; 1050 } 1051 1052 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1053 void (*f_tl)(TCGv, TCGv), 1054 void (*f_32)(TCGv, TCGv)) 1055 { 1056 int olen = get_olen(ctx); 1057 1058 if (olen != TARGET_LONG_BITS) { 1059 if (olen == 32) { 1060 f_tl = f_32; 1061 } else { 1062 g_assert_not_reached(); 1063 } 1064 } 1065 return gen_unary(ctx, a, ext, f_tl); 1066 } 1067 1068 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1069 { 1070 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1071 CPUState *cpu = ctx->cs; 1072 CPURISCVState *env = cpu->env_ptr; 1073 1074 return cpu_ldl_code(env, pc); 1075 } 1076 1077 /* Include insn module translation function */ 1078 #include "insn_trans/trans_rvi.c.inc" 1079 #include "insn_trans/trans_rvm.c.inc" 1080 #include "insn_trans/trans_rva.c.inc" 1081 #include "insn_trans/trans_rvf.c.inc" 1082 #include "insn_trans/trans_rvd.c.inc" 1083 #include "insn_trans/trans_rvh.c.inc" 1084 #include "insn_trans/trans_rvv.c.inc" 1085 #include "insn_trans/trans_rvb.c.inc" 1086 #include "insn_trans/trans_rvzicond.c.inc" 1087 #include "insn_trans/trans_rvzawrs.c.inc" 1088 #include "insn_trans/trans_rvzicbo.c.inc" 1089 #include "insn_trans/trans_rvzfh.c.inc" 1090 #include "insn_trans/trans_rvk.c.inc" 1091 #include "insn_trans/trans_privileged.c.inc" 1092 #include "insn_trans/trans_svinval.c.inc" 1093 #include "decode-xthead.c.inc" 1094 #include "insn_trans/trans_xthead.c.inc" 1095 #include "insn_trans/trans_xventanacondops.c.inc" 1096 1097 /* Include the auto-generated decoder for 16 bit insn */ 1098 #include "decode-insn16.c.inc" 1099 #include "insn_trans/trans_rvzce.c.inc" 1100 1101 /* Include decoders for factored-out extensions */ 1102 #include "decode-XVentanaCondOps.c.inc" 1103 1104 /* The specification allows for longer insns, but not supported by qemu. */ 1105 #define MAX_INSN_LEN 4 1106 1107 static inline int insn_len(uint16_t first_word) 1108 { 1109 return (first_word & 3) == 3 ? 4 : 2; 1110 } 1111 1112 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1113 { 1114 /* 1115 * A table with predicate (i.e., guard) functions and decoder functions 1116 * that are tested in-order until a decoder matches onto the opcode. 1117 */ 1118 static const struct { 1119 bool (*guard_func)(DisasContext *); 1120 bool (*decode_func)(DisasContext *, uint32_t); 1121 } decoders[] = { 1122 { always_true_p, decode_insn32 }, 1123 { has_xthead_p, decode_xthead }, 1124 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1125 }; 1126 1127 ctx->virt_inst_excp = false; 1128 /* Check for compressed insn */ 1129 if (insn_len(opcode) == 2) { 1130 ctx->opcode = opcode; 1131 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1132 /* 1133 * The Zca extension is added as way to refer to instructions in the C 1134 * extension that do not include the floating-point loads and stores 1135 */ 1136 if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) { 1137 return; 1138 } 1139 } else { 1140 uint32_t opcode32 = opcode; 1141 opcode32 = deposit32(opcode32, 16, 16, 1142 translator_lduw(env, &ctx->base, 1143 ctx->base.pc_next + 2)); 1144 ctx->opcode = opcode32; 1145 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1146 1147 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1148 if (decoders[i].guard_func(ctx) && 1149 decoders[i].decode_func(ctx, opcode32)) { 1150 return; 1151 } 1152 } 1153 } 1154 1155 gen_exception_illegal(ctx); 1156 } 1157 1158 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1159 { 1160 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1161 CPURISCVState *env = cs->env_ptr; 1162 RISCVCPU *cpu = RISCV_CPU(cs); 1163 uint32_t tb_flags = ctx->base.tb->flags; 1164 1165 ctx->pc_succ_insn = ctx->base.pc_first; 1166 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1167 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1168 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1169 ctx->priv_ver = env->priv_ver; 1170 #if !defined(CONFIG_USER_ONLY) 1171 if (riscv_has_ext(env, RVH)) { 1172 ctx->virt_enabled = env->virt_enabled; 1173 } else { 1174 ctx->virt_enabled = false; 1175 } 1176 #else 1177 ctx->virt_enabled = false; 1178 #endif 1179 ctx->misa_ext = env->misa_ext; 1180 ctx->frm = -1; /* unknown rounding mode */ 1181 ctx->cfg_ptr = &(cpu->cfg); 1182 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1183 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1184 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1185 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1186 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1187 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1188 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1189 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1190 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1191 ctx->vstart = env->vstart; 1192 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1193 ctx->misa_mxl_max = env->misa_mxl_max; 1194 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1195 ctx->cs = cs; 1196 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1197 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1198 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1199 ctx->zero = tcg_constant_tl(0); 1200 ctx->virt_inst_excp = false; 1201 } 1202 1203 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1204 { 1205 } 1206 1207 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1208 { 1209 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1210 1211 tcg_gen_insn_start(ctx->base.pc_next, 0); 1212 ctx->insn_start = tcg_last_op(); 1213 } 1214 1215 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1216 { 1217 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1218 CPURISCVState *env = cpu->env_ptr; 1219 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1220 1221 ctx->ol = ctx->xl; 1222 decode_opc(env, ctx, opcode16); 1223 ctx->base.pc_next = ctx->pc_succ_insn; 1224 1225 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1226 if (ctx->base.is_jmp == DISAS_NEXT) { 1227 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1228 ctx->base.is_jmp = DISAS_TOO_MANY; 1229 } else { 1230 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1231 1232 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1233 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1234 int len = insn_len(next_insn); 1235 1236 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1237 ctx->base.is_jmp = DISAS_TOO_MANY; 1238 } 1239 } 1240 } 1241 } 1242 } 1243 1244 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1245 { 1246 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1247 1248 switch (ctx->base.is_jmp) { 1249 case DISAS_TOO_MANY: 1250 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1251 break; 1252 case DISAS_NORETURN: 1253 break; 1254 default: 1255 g_assert_not_reached(); 1256 } 1257 } 1258 1259 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1260 CPUState *cpu, FILE *logfile) 1261 { 1262 #ifndef CONFIG_USER_ONLY 1263 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1264 CPURISCVState *env = &rvcpu->env; 1265 #endif 1266 1267 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1268 #ifndef CONFIG_USER_ONLY 1269 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n", 1270 env->priv, env->virt_enabled); 1271 #endif 1272 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1273 } 1274 1275 static const TranslatorOps riscv_tr_ops = { 1276 .init_disas_context = riscv_tr_init_disas_context, 1277 .tb_start = riscv_tr_tb_start, 1278 .insn_start = riscv_tr_insn_start, 1279 .translate_insn = riscv_tr_translate_insn, 1280 .tb_stop = riscv_tr_tb_stop, 1281 .disas_log = riscv_tr_disas_log, 1282 }; 1283 1284 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1285 target_ulong pc, void *host_pc) 1286 { 1287 DisasContext ctx; 1288 1289 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1290 } 1291 1292 void riscv_translate_init(void) 1293 { 1294 int i; 1295 1296 /* 1297 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1298 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1299 * unless you specifically block reads/writes to reg 0. 1300 */ 1301 cpu_gpr[0] = NULL; 1302 cpu_gprh[0] = NULL; 1303 1304 for (i = 1; i < 32; i++) { 1305 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1306 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1307 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1308 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1309 } 1310 1311 for (i = 0; i < 32; i++) { 1312 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1313 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1314 } 1315 1316 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1317 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1318 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1319 "vstart"); 1320 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1321 "load_res"); 1322 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1323 "load_val"); 1324 /* Assign PM CSRs to tcg globals */ 1325 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1326 "pmmask"); 1327 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1328 "pmbase"); 1329 } 1330