1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 #define HELPER_H "helper.h" 37 #include "exec/helper-info.c.inc" 38 #undef HELPER_H 39 40 /* global register indices */ 41 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 42 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 43 static TCGv load_res; 44 static TCGv load_val; 45 /* globals for PM CSRs */ 46 static TCGv pm_mask; 47 static TCGv pm_base; 48 49 /* 50 * If an operation is being performed on less than TARGET_LONG_BITS, 51 * it may require the inputs to be sign- or zero-extended; which will 52 * depend on the exact operation being performed. 53 */ 54 typedef enum { 55 EXT_NONE, 56 EXT_SIGN, 57 EXT_ZERO, 58 } DisasExtend; 59 60 typedef struct DisasContext { 61 DisasContextBase base; 62 /* pc_succ_insn points to the instruction following base.pc_next */ 63 target_ulong pc_succ_insn; 64 target_ulong cur_insn_len; 65 target_ulong pc_save; 66 target_ulong priv_ver; 67 RISCVMXL misa_mxl_max; 68 RISCVMXL xl; 69 uint32_t misa_ext; 70 uint32_t opcode; 71 RISCVExtStatus mstatus_fs; 72 RISCVExtStatus mstatus_vs; 73 uint32_t mem_idx; 74 uint32_t priv; 75 /* 76 * Remember the rounding mode encoded in the previous fp instruction, 77 * which we have already installed into env->fp_status. Or -1 for 78 * no previous fp instruction. Note that we exit the TB when writing 79 * to any system register, which includes CSR_FRM, so we do not have 80 * to reset this known value. 81 */ 82 int frm; 83 RISCVMXL ol; 84 bool virt_inst_excp; 85 bool virt_enabled; 86 const RISCVCPUConfig *cfg_ptr; 87 /* vector extension */ 88 bool vill; 89 /* 90 * Encode LMUL to lmul as follows: 91 * LMUL vlmul lmul 92 * 1 000 0 93 * 2 001 1 94 * 4 010 2 95 * 8 011 3 96 * - 100 - 97 * 1/8 101 -3 98 * 1/4 110 -2 99 * 1/2 111 -1 100 */ 101 int8_t lmul; 102 uint8_t sew; 103 uint8_t vta; 104 uint8_t vma; 105 bool cfg_vta_all_1s; 106 bool vstart_eq_zero; 107 bool vl_eq_vlmax; 108 CPUState *cs; 109 TCGv zero; 110 /* PointerMasking extension */ 111 bool pm_mask_enabled; 112 bool pm_base_enabled; 113 /* Use icount trigger for native debug */ 114 bool itrigger; 115 /* FRM is known to contain a valid value. */ 116 bool frm_valid; 117 /* TCG of the current insn_start */ 118 TCGOp *insn_start; 119 } DisasContext; 120 121 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 122 { 123 return ctx->misa_ext & ext; 124 } 125 126 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 127 { 128 return true; 129 } 130 131 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) 132 { 133 return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || 134 ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || 135 ctx->cfg_ptr->ext_xtheadcondmov || 136 ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || 137 ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || 138 ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; 139 } 140 141 #define MATERIALISE_EXT_PREDICATE(ext) \ 142 static bool has_ ## ext ## _p(DisasContext *ctx) \ 143 { \ 144 return ctx->cfg_ptr->ext_ ## ext ; \ 145 } 146 147 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 148 149 #ifdef TARGET_RISCV32 150 #define get_xl(ctx) MXL_RV32 151 #elif defined(CONFIG_USER_ONLY) 152 #define get_xl(ctx) MXL_RV64 153 #else 154 #define get_xl(ctx) ((ctx)->xl) 155 #endif 156 157 /* The word size for this machine mode. */ 158 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 159 { 160 return 16 << get_xl(ctx); 161 } 162 163 /* The operation length, as opposed to the xlen. */ 164 #ifdef TARGET_RISCV32 165 #define get_ol(ctx) MXL_RV32 166 #else 167 #define get_ol(ctx) ((ctx)->ol) 168 #endif 169 170 static inline int get_olen(DisasContext *ctx) 171 { 172 return 16 << get_ol(ctx); 173 } 174 175 /* The maximum register length */ 176 #ifdef TARGET_RISCV32 177 #define get_xl_max(ctx) MXL_RV32 178 #else 179 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 180 #endif 181 182 /* 183 * RISC-V requires NaN-boxing of narrower width floating point values. 184 * This applies when a 32-bit value is assigned to a 64-bit FP register. 185 * For consistency and simplicity, we nanbox results even when the RVD 186 * extension is not present. 187 */ 188 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 189 { 190 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 191 } 192 193 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 194 { 195 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 196 } 197 198 /* 199 * A narrow n-bit operation, where n < FLEN, checks that input operands 200 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 201 * If so, the least-significant bits of the input are used, otherwise the 202 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 203 * 204 * Here, the result is always nan-boxed, even the canonical nan. 205 */ 206 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 207 { 208 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 209 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 210 211 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 212 } 213 214 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 215 { 216 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 217 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 218 219 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 220 } 221 222 static void decode_save_opc(DisasContext *ctx) 223 { 224 assert(ctx->insn_start != NULL); 225 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 226 ctx->insn_start = NULL; 227 } 228 229 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, 230 target_long diff) 231 { 232 target_ulong dest = ctx->base.pc_next + diff; 233 234 assert(ctx->pc_save != -1); 235 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 236 tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save); 237 if (get_xl(ctx) == MXL_RV32) { 238 tcg_gen_ext32s_tl(target, target); 239 } 240 } else { 241 if (get_xl(ctx) == MXL_RV32) { 242 dest = (int32_t)dest; 243 } 244 tcg_gen_movi_tl(target, dest); 245 } 246 } 247 248 static void gen_update_pc(DisasContext *ctx, target_long diff) 249 { 250 gen_pc_plus_diff(cpu_pc, ctx, diff); 251 ctx->pc_save = ctx->base.pc_next + diff; 252 } 253 254 static void generate_exception(DisasContext *ctx, int excp) 255 { 256 gen_update_pc(ctx, 0); 257 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 258 ctx->base.is_jmp = DISAS_NORETURN; 259 } 260 261 static void gen_exception_illegal(DisasContext *ctx) 262 { 263 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 264 offsetof(CPURISCVState, bins)); 265 if (ctx->virt_inst_excp) { 266 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 267 } else { 268 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 269 } 270 } 271 272 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) 273 { 274 tcg_gen_st_tl(target, cpu_env, offsetof(CPURISCVState, badaddr)); 275 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 276 } 277 278 static void lookup_and_goto_ptr(DisasContext *ctx) 279 { 280 #ifndef CONFIG_USER_ONLY 281 if (ctx->itrigger) { 282 gen_helper_itrigger_match(cpu_env); 283 } 284 #endif 285 tcg_gen_lookup_and_goto_ptr(); 286 } 287 288 static void exit_tb(DisasContext *ctx) 289 { 290 #ifndef CONFIG_USER_ONLY 291 if (ctx->itrigger) { 292 gen_helper_itrigger_match(cpu_env); 293 } 294 #endif 295 tcg_gen_exit_tb(NULL, 0); 296 } 297 298 static void gen_goto_tb(DisasContext *ctx, int n, target_long diff) 299 { 300 target_ulong dest = ctx->base.pc_next + diff; 301 302 /* 303 * Under itrigger, instruction executes one by one like singlestep, 304 * direct block chain benefits will be small. 305 */ 306 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 307 /* 308 * For pcrel, the pc must always be up-to-date on entry to 309 * the linked TB, so that it can use simple additions for all 310 * further adjustments. For !pcrel, the linked TB is compiled 311 * to know its full virtual address, so we can delay the 312 * update to pc to the unlinked path. A long chain of links 313 * can thus avoid many updates to the PC. 314 */ 315 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 316 gen_update_pc(ctx, diff); 317 tcg_gen_goto_tb(n); 318 } else { 319 tcg_gen_goto_tb(n); 320 gen_update_pc(ctx, diff); 321 } 322 tcg_gen_exit_tb(ctx->base.tb, n); 323 } else { 324 gen_update_pc(ctx, diff); 325 lookup_and_goto_ptr(ctx); 326 } 327 } 328 329 /* 330 * Wrappers for getting reg values. 331 * 332 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 333 * constant zero as a source, and an uninitialized sink as destination. 334 * 335 * Further, we may provide an extension for word operations. 336 */ 337 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 338 { 339 TCGv t; 340 341 if (reg_num == 0) { 342 return ctx->zero; 343 } 344 345 switch (get_ol(ctx)) { 346 case MXL_RV32: 347 switch (ext) { 348 case EXT_NONE: 349 break; 350 case EXT_SIGN: 351 t = tcg_temp_new(); 352 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 353 return t; 354 case EXT_ZERO: 355 t = tcg_temp_new(); 356 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 357 return t; 358 default: 359 g_assert_not_reached(); 360 } 361 break; 362 case MXL_RV64: 363 case MXL_RV128: 364 break; 365 default: 366 g_assert_not_reached(); 367 } 368 return cpu_gpr[reg_num]; 369 } 370 371 static TCGv get_gprh(DisasContext *ctx, int reg_num) 372 { 373 assert(get_xl(ctx) == MXL_RV128); 374 if (reg_num == 0) { 375 return ctx->zero; 376 } 377 return cpu_gprh[reg_num]; 378 } 379 380 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 381 { 382 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 383 return tcg_temp_new(); 384 } 385 return cpu_gpr[reg_num]; 386 } 387 388 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 389 { 390 if (reg_num == 0) { 391 return tcg_temp_new(); 392 } 393 return cpu_gprh[reg_num]; 394 } 395 396 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 397 { 398 if (reg_num != 0) { 399 switch (get_ol(ctx)) { 400 case MXL_RV32: 401 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 402 break; 403 case MXL_RV64: 404 case MXL_RV128: 405 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 406 break; 407 default: 408 g_assert_not_reached(); 409 } 410 411 if (get_xl_max(ctx) == MXL_RV128) { 412 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 413 } 414 } 415 } 416 417 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 418 { 419 if (reg_num != 0) { 420 switch (get_ol(ctx)) { 421 case MXL_RV32: 422 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 423 break; 424 case MXL_RV64: 425 case MXL_RV128: 426 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 427 break; 428 default: 429 g_assert_not_reached(); 430 } 431 432 if (get_xl_max(ctx) == MXL_RV128) { 433 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 434 } 435 } 436 } 437 438 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 439 { 440 assert(get_ol(ctx) == MXL_RV128); 441 if (reg_num != 0) { 442 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 443 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 444 } 445 } 446 447 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 448 { 449 if (!ctx->cfg_ptr->ext_zfinx) { 450 return cpu_fpr[reg_num]; 451 } 452 453 if (reg_num == 0) { 454 return tcg_constant_i64(0); 455 } 456 switch (get_xl(ctx)) { 457 case MXL_RV32: 458 #ifdef TARGET_RISCV32 459 { 460 TCGv_i64 t = tcg_temp_new_i64(); 461 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 462 return t; 463 } 464 #else 465 /* fall through */ 466 case MXL_RV64: 467 return cpu_gpr[reg_num]; 468 #endif 469 default: 470 g_assert_not_reached(); 471 } 472 } 473 474 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 475 { 476 if (!ctx->cfg_ptr->ext_zfinx) { 477 return cpu_fpr[reg_num]; 478 } 479 480 if (reg_num == 0) { 481 return tcg_constant_i64(0); 482 } 483 switch (get_xl(ctx)) { 484 case MXL_RV32: 485 { 486 TCGv_i64 t = tcg_temp_new_i64(); 487 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 488 return t; 489 } 490 #ifdef TARGET_RISCV64 491 case MXL_RV64: 492 return cpu_gpr[reg_num]; 493 #endif 494 default: 495 g_assert_not_reached(); 496 } 497 } 498 499 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 500 { 501 if (!ctx->cfg_ptr->ext_zfinx) { 502 return cpu_fpr[reg_num]; 503 } 504 505 if (reg_num == 0) { 506 return tcg_temp_new_i64(); 507 } 508 509 switch (get_xl(ctx)) { 510 case MXL_RV32: 511 return tcg_temp_new_i64(); 512 #ifdef TARGET_RISCV64 513 case MXL_RV64: 514 return cpu_gpr[reg_num]; 515 #endif 516 default: 517 g_assert_not_reached(); 518 } 519 } 520 521 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 522 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 523 { 524 if (!ctx->cfg_ptr->ext_zfinx) { 525 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 526 return; 527 } 528 if (reg_num != 0) { 529 switch (get_xl(ctx)) { 530 case MXL_RV32: 531 #ifdef TARGET_RISCV32 532 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 533 break; 534 #else 535 /* fall through */ 536 case MXL_RV64: 537 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 538 break; 539 #endif 540 default: 541 g_assert_not_reached(); 542 } 543 } 544 } 545 546 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 547 { 548 if (!ctx->cfg_ptr->ext_zfinx) { 549 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 550 return; 551 } 552 553 if (reg_num != 0) { 554 switch (get_xl(ctx)) { 555 case MXL_RV32: 556 #ifdef TARGET_RISCV32 557 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 558 break; 559 #else 560 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 561 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 562 break; 563 case MXL_RV64: 564 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 565 break; 566 #endif 567 default: 568 g_assert_not_reached(); 569 } 570 } 571 } 572 573 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 574 { 575 TCGv succ_pc = dest_gpr(ctx, rd); 576 577 /* check misaligned: */ 578 if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { 579 if ((imm & 0x3) != 0) { 580 TCGv target_pc = tcg_temp_new(); 581 gen_pc_plus_diff(target_pc, ctx, imm); 582 gen_exception_inst_addr_mis(ctx, target_pc); 583 return; 584 } 585 } 586 587 gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); 588 gen_set_gpr(ctx, rd, succ_pc); 589 590 gen_goto_tb(ctx, 0, imm); /* must use this for safety */ 591 ctx->base.is_jmp = DISAS_NORETURN; 592 } 593 594 /* Compute a canonical address from a register plus offset. */ 595 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 596 { 597 TCGv addr = tcg_temp_new(); 598 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 599 600 tcg_gen_addi_tl(addr, src1, imm); 601 if (ctx->pm_mask_enabled) { 602 tcg_gen_andc_tl(addr, addr, pm_mask); 603 } else if (get_xl(ctx) == MXL_RV32) { 604 tcg_gen_ext32u_tl(addr, addr); 605 } 606 if (ctx->pm_base_enabled) { 607 tcg_gen_or_tl(addr, addr, pm_base); 608 } 609 return addr; 610 } 611 612 /* Compute a canonical address from a register plus reg offset. */ 613 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 614 { 615 TCGv addr = tcg_temp_new(); 616 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 617 618 tcg_gen_add_tl(addr, src1, offs); 619 if (ctx->pm_mask_enabled) { 620 tcg_gen_andc_tl(addr, addr, pm_mask); 621 } else if (get_xl(ctx) == MXL_RV32) { 622 tcg_gen_ext32u_tl(addr, addr); 623 } 624 if (ctx->pm_base_enabled) { 625 tcg_gen_or_tl(addr, addr, pm_base); 626 } 627 return addr; 628 } 629 630 #ifndef CONFIG_USER_ONLY 631 /* 632 * We will have already diagnosed disabled state, 633 * and need to turn initial/clean into dirty. 634 */ 635 static void mark_fs_dirty(DisasContext *ctx) 636 { 637 TCGv tmp; 638 639 if (!has_ext(ctx, RVF)) { 640 return; 641 } 642 643 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 644 /* Remember the state change for the rest of the TB. */ 645 ctx->mstatus_fs = EXT_STATUS_DIRTY; 646 647 tmp = tcg_temp_new(); 648 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 649 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 650 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 651 652 if (ctx->virt_enabled) { 653 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 654 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 655 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 656 } 657 } 658 } 659 #else 660 static inline void mark_fs_dirty(DisasContext *ctx) { } 661 #endif 662 663 #ifndef CONFIG_USER_ONLY 664 /* 665 * We will have already diagnosed disabled state, 666 * and need to turn initial/clean into dirty. 667 */ 668 static void mark_vs_dirty(DisasContext *ctx) 669 { 670 TCGv tmp; 671 672 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 673 /* Remember the state change for the rest of the TB. */ 674 ctx->mstatus_vs = EXT_STATUS_DIRTY; 675 676 tmp = tcg_temp_new(); 677 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 678 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 679 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 680 681 if (ctx->virt_enabled) { 682 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 683 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 684 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 685 } 686 } 687 } 688 #else 689 static inline void mark_vs_dirty(DisasContext *ctx) { } 690 #endif 691 692 static void gen_set_rm(DisasContext *ctx, int rm) 693 { 694 if (ctx->frm == rm) { 695 return; 696 } 697 ctx->frm = rm; 698 699 if (rm == RISCV_FRM_DYN) { 700 /* The helper will return only if frm valid. */ 701 ctx->frm_valid = true; 702 } 703 704 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 705 decode_save_opc(ctx); 706 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 707 } 708 709 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 710 { 711 if (ctx->frm == rm && ctx->frm_valid) { 712 return; 713 } 714 ctx->frm = rm; 715 ctx->frm_valid = true; 716 717 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 718 decode_save_opc(ctx); 719 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 720 } 721 722 static int ex_plus_1(DisasContext *ctx, int nf) 723 { 724 return nf + 1; 725 } 726 727 #define EX_SH(amount) \ 728 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 729 { \ 730 return imm << amount; \ 731 } 732 EX_SH(1) 733 EX_SH(2) 734 EX_SH(3) 735 EX_SH(4) 736 EX_SH(12) 737 738 #define REQUIRE_EXT(ctx, ext) do { \ 739 if (!has_ext(ctx, ext)) { \ 740 return false; \ 741 } \ 742 } while (0) 743 744 #define REQUIRE_32BIT(ctx) do { \ 745 if (get_xl(ctx) != MXL_RV32) { \ 746 return false; \ 747 } \ 748 } while (0) 749 750 #define REQUIRE_64BIT(ctx) do { \ 751 if (get_xl(ctx) != MXL_RV64) { \ 752 return false; \ 753 } \ 754 } while (0) 755 756 #define REQUIRE_128BIT(ctx) do { \ 757 if (get_xl(ctx) != MXL_RV128) { \ 758 return false; \ 759 } \ 760 } while (0) 761 762 #define REQUIRE_64_OR_128BIT(ctx) do { \ 763 if (get_xl(ctx) == MXL_RV32) { \ 764 return false; \ 765 } \ 766 } while (0) 767 768 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 769 if (!ctx->cfg_ptr->ext_##A && \ 770 !ctx->cfg_ptr->ext_##B) { \ 771 return false; \ 772 } \ 773 } while (0) 774 775 static int ex_rvc_register(DisasContext *ctx, int reg) 776 { 777 return 8 + reg; 778 } 779 780 static int ex_sreg_register(DisasContext *ctx, int reg) 781 { 782 return reg < 2 ? reg + 8 : reg + 16; 783 } 784 785 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 786 { 787 /* For RV128 a shamt of 0 means a shift by 64. */ 788 if (get_ol(ctx) == MXL_RV128) { 789 imm = imm ? imm : 64; 790 } 791 return imm; 792 } 793 794 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 795 { 796 /* 797 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 798 * shifts, the shamt is sign-extended. 799 */ 800 if (get_ol(ctx) == MXL_RV128) { 801 imm = imm | (imm & 32) << 1; 802 imm = imm ? imm : 64; 803 } 804 return imm; 805 } 806 807 /* Include the auto-generated decoder for 32 bit insn */ 808 #include "decode-insn32.c.inc" 809 810 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 811 void (*func)(TCGv, TCGv, target_long)) 812 { 813 TCGv dest = dest_gpr(ctx, a->rd); 814 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 815 816 func(dest, src1, a->imm); 817 818 if (get_xl(ctx) == MXL_RV128) { 819 TCGv src1h = get_gprh(ctx, a->rs1); 820 TCGv desth = dest_gprh(ctx, a->rd); 821 822 func(desth, src1h, -(a->imm < 0)); 823 gen_set_gpr128(ctx, a->rd, dest, desth); 824 } else { 825 gen_set_gpr(ctx, a->rd, dest); 826 } 827 828 return true; 829 } 830 831 static bool gen_logic(DisasContext *ctx, arg_r *a, 832 void (*func)(TCGv, TCGv, TCGv)) 833 { 834 TCGv dest = dest_gpr(ctx, a->rd); 835 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 836 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 837 838 func(dest, src1, src2); 839 840 if (get_xl(ctx) == MXL_RV128) { 841 TCGv src1h = get_gprh(ctx, a->rs1); 842 TCGv src2h = get_gprh(ctx, a->rs2); 843 TCGv desth = dest_gprh(ctx, a->rd); 844 845 func(desth, src1h, src2h); 846 gen_set_gpr128(ctx, a->rd, dest, desth); 847 } else { 848 gen_set_gpr(ctx, a->rd, dest); 849 } 850 851 return true; 852 } 853 854 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 855 void (*func)(TCGv, TCGv, target_long), 856 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 857 { 858 TCGv dest = dest_gpr(ctx, a->rd); 859 TCGv src1 = get_gpr(ctx, a->rs1, ext); 860 861 if (get_ol(ctx) < MXL_RV128) { 862 func(dest, src1, a->imm); 863 gen_set_gpr(ctx, a->rd, dest); 864 } else { 865 if (f128 == NULL) { 866 return false; 867 } 868 869 TCGv src1h = get_gprh(ctx, a->rs1); 870 TCGv desth = dest_gprh(ctx, a->rd); 871 872 f128(dest, desth, src1, src1h, a->imm); 873 gen_set_gpr128(ctx, a->rd, dest, desth); 874 } 875 return true; 876 } 877 878 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 879 void (*func)(TCGv, TCGv, TCGv), 880 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 881 { 882 TCGv dest = dest_gpr(ctx, a->rd); 883 TCGv src1 = get_gpr(ctx, a->rs1, ext); 884 TCGv src2 = tcg_constant_tl(a->imm); 885 886 if (get_ol(ctx) < MXL_RV128) { 887 func(dest, src1, src2); 888 gen_set_gpr(ctx, a->rd, dest); 889 } else { 890 if (f128 == NULL) { 891 return false; 892 } 893 894 TCGv src1h = get_gprh(ctx, a->rs1); 895 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 896 TCGv desth = dest_gprh(ctx, a->rd); 897 898 f128(dest, desth, src1, src1h, src2, src2h); 899 gen_set_gpr128(ctx, a->rd, dest, desth); 900 } 901 return true; 902 } 903 904 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 905 void (*func)(TCGv, TCGv, TCGv), 906 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 907 { 908 TCGv dest = dest_gpr(ctx, a->rd); 909 TCGv src1 = get_gpr(ctx, a->rs1, ext); 910 TCGv src2 = get_gpr(ctx, a->rs2, ext); 911 912 if (get_ol(ctx) < MXL_RV128) { 913 func(dest, src1, src2); 914 gen_set_gpr(ctx, a->rd, dest); 915 } else { 916 if (f128 == NULL) { 917 return false; 918 } 919 920 TCGv src1h = get_gprh(ctx, a->rs1); 921 TCGv src2h = get_gprh(ctx, a->rs2); 922 TCGv desth = dest_gprh(ctx, a->rd); 923 924 f128(dest, desth, src1, src1h, src2, src2h); 925 gen_set_gpr128(ctx, a->rd, dest, desth); 926 } 927 return true; 928 } 929 930 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 931 void (*f_tl)(TCGv, TCGv, TCGv), 932 void (*f_32)(TCGv, TCGv, TCGv), 933 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 934 { 935 int olen = get_olen(ctx); 936 937 if (olen != TARGET_LONG_BITS) { 938 if (olen == 32) { 939 f_tl = f_32; 940 } else if (olen != 128) { 941 g_assert_not_reached(); 942 } 943 } 944 return gen_arith(ctx, a, ext, f_tl, f_128); 945 } 946 947 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 948 void (*func)(TCGv, TCGv, target_long), 949 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 950 { 951 TCGv dest, src1; 952 int max_len = get_olen(ctx); 953 954 if (a->shamt >= max_len) { 955 return false; 956 } 957 958 dest = dest_gpr(ctx, a->rd); 959 src1 = get_gpr(ctx, a->rs1, ext); 960 961 if (max_len < 128) { 962 func(dest, src1, a->shamt); 963 gen_set_gpr(ctx, a->rd, dest); 964 } else { 965 TCGv src1h = get_gprh(ctx, a->rs1); 966 TCGv desth = dest_gprh(ctx, a->rd); 967 968 if (f128 == NULL) { 969 return false; 970 } 971 f128(dest, desth, src1, src1h, a->shamt); 972 gen_set_gpr128(ctx, a->rd, dest, desth); 973 } 974 return true; 975 } 976 977 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 978 DisasExtend ext, 979 void (*f_tl)(TCGv, TCGv, target_long), 980 void (*f_32)(TCGv, TCGv, target_long), 981 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 982 target_long)) 983 { 984 int olen = get_olen(ctx); 985 if (olen != TARGET_LONG_BITS) { 986 if (olen == 32) { 987 f_tl = f_32; 988 } else if (olen != 128) { 989 g_assert_not_reached(); 990 } 991 } 992 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 993 } 994 995 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 996 void (*func)(TCGv, TCGv, TCGv)) 997 { 998 TCGv dest, src1, src2; 999 int max_len = get_olen(ctx); 1000 1001 if (a->shamt >= max_len) { 1002 return false; 1003 } 1004 1005 dest = dest_gpr(ctx, a->rd); 1006 src1 = get_gpr(ctx, a->rs1, ext); 1007 src2 = tcg_constant_tl(a->shamt); 1008 1009 func(dest, src1, src2); 1010 1011 gen_set_gpr(ctx, a->rd, dest); 1012 return true; 1013 } 1014 1015 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 1016 void (*func)(TCGv, TCGv, TCGv), 1017 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1018 { 1019 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1020 TCGv ext2 = tcg_temp_new(); 1021 int max_len = get_olen(ctx); 1022 1023 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1024 1025 TCGv dest = dest_gpr(ctx, a->rd); 1026 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1027 1028 if (max_len < 128) { 1029 func(dest, src1, ext2); 1030 gen_set_gpr(ctx, a->rd, dest); 1031 } else { 1032 TCGv src1h = get_gprh(ctx, a->rs1); 1033 TCGv desth = dest_gprh(ctx, a->rd); 1034 1035 if (f128 == NULL) { 1036 return false; 1037 } 1038 f128(dest, desth, src1, src1h, ext2); 1039 gen_set_gpr128(ctx, a->rd, dest, desth); 1040 } 1041 return true; 1042 } 1043 1044 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1045 void (*f_tl)(TCGv, TCGv, TCGv), 1046 void (*f_32)(TCGv, TCGv, TCGv), 1047 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1048 { 1049 int olen = get_olen(ctx); 1050 if (olen != TARGET_LONG_BITS) { 1051 if (olen == 32) { 1052 f_tl = f_32; 1053 } else if (olen != 128) { 1054 g_assert_not_reached(); 1055 } 1056 } 1057 return gen_shift(ctx, a, ext, f_tl, f_128); 1058 } 1059 1060 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1061 void (*func)(TCGv, TCGv)) 1062 { 1063 TCGv dest = dest_gpr(ctx, a->rd); 1064 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1065 1066 func(dest, src1); 1067 1068 gen_set_gpr(ctx, a->rd, dest); 1069 return true; 1070 } 1071 1072 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1073 void (*f_tl)(TCGv, TCGv), 1074 void (*f_32)(TCGv, TCGv)) 1075 { 1076 int olen = get_olen(ctx); 1077 1078 if (olen != TARGET_LONG_BITS) { 1079 if (olen == 32) { 1080 f_tl = f_32; 1081 } else { 1082 g_assert_not_reached(); 1083 } 1084 } 1085 return gen_unary(ctx, a, ext, f_tl); 1086 } 1087 1088 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1089 { 1090 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1091 CPUState *cpu = ctx->cs; 1092 CPURISCVState *env = cpu->env_ptr; 1093 1094 return cpu_ldl_code(env, pc); 1095 } 1096 1097 /* Include insn module translation function */ 1098 #include "insn_trans/trans_rvi.c.inc" 1099 #include "insn_trans/trans_rvm.c.inc" 1100 #include "insn_trans/trans_rva.c.inc" 1101 #include "insn_trans/trans_rvf.c.inc" 1102 #include "insn_trans/trans_rvd.c.inc" 1103 #include "insn_trans/trans_rvh.c.inc" 1104 #include "insn_trans/trans_rvv.c.inc" 1105 #include "insn_trans/trans_rvb.c.inc" 1106 #include "insn_trans/trans_rvzicond.c.inc" 1107 #include "insn_trans/trans_rvzawrs.c.inc" 1108 #include "insn_trans/trans_rvzicbo.c.inc" 1109 #include "insn_trans/trans_rvzfh.c.inc" 1110 #include "insn_trans/trans_rvk.c.inc" 1111 #include "insn_trans/trans_privileged.c.inc" 1112 #include "insn_trans/trans_svinval.c.inc" 1113 #include "decode-xthead.c.inc" 1114 #include "insn_trans/trans_xthead.c.inc" 1115 #include "insn_trans/trans_xventanacondops.c.inc" 1116 1117 /* Include the auto-generated decoder for 16 bit insn */ 1118 #include "decode-insn16.c.inc" 1119 #include "insn_trans/trans_rvzce.c.inc" 1120 1121 /* Include decoders for factored-out extensions */ 1122 #include "decode-XVentanaCondOps.c.inc" 1123 1124 /* The specification allows for longer insns, but not supported by qemu. */ 1125 #define MAX_INSN_LEN 4 1126 1127 static inline int insn_len(uint16_t first_word) 1128 { 1129 return (first_word & 3) == 3 ? 4 : 2; 1130 } 1131 1132 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1133 { 1134 /* 1135 * A table with predicate (i.e., guard) functions and decoder functions 1136 * that are tested in-order until a decoder matches onto the opcode. 1137 */ 1138 static const struct { 1139 bool (*guard_func)(DisasContext *); 1140 bool (*decode_func)(DisasContext *, uint32_t); 1141 } decoders[] = { 1142 { always_true_p, decode_insn32 }, 1143 { has_xthead_p, decode_xthead }, 1144 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1145 }; 1146 1147 ctx->virt_inst_excp = false; 1148 ctx->cur_insn_len = insn_len(opcode); 1149 /* Check for compressed insn */ 1150 if (ctx->cur_insn_len == 2) { 1151 ctx->opcode = opcode; 1152 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1153 /* 1154 * The Zca extension is added as way to refer to instructions in the C 1155 * extension that do not include the floating-point loads and stores 1156 */ 1157 if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && 1158 decode_insn16(ctx, opcode)) { 1159 return; 1160 } 1161 } else { 1162 uint32_t opcode32 = opcode; 1163 opcode32 = deposit32(opcode32, 16, 16, 1164 translator_lduw(env, &ctx->base, 1165 ctx->base.pc_next + 2)); 1166 ctx->opcode = opcode32; 1167 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1168 1169 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1170 if (decoders[i].guard_func(ctx) && 1171 decoders[i].decode_func(ctx, opcode32)) { 1172 return; 1173 } 1174 } 1175 } 1176 1177 gen_exception_illegal(ctx); 1178 } 1179 1180 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1181 { 1182 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1183 CPURISCVState *env = cs->env_ptr; 1184 RISCVCPU *cpu = RISCV_CPU(cs); 1185 uint32_t tb_flags = ctx->base.tb->flags; 1186 1187 ctx->pc_save = ctx->base.pc_first; 1188 ctx->pc_succ_insn = ctx->base.pc_first; 1189 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1190 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1191 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1192 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1193 ctx->priv_ver = env->priv_ver; 1194 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1195 ctx->misa_ext = env->misa_ext; 1196 ctx->frm = -1; /* unknown rounding mode */ 1197 ctx->cfg_ptr = &(cpu->cfg); 1198 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1199 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1200 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1201 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1202 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1203 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1204 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1205 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1206 ctx->misa_mxl_max = env->misa_mxl_max; 1207 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1208 ctx->cs = cs; 1209 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1210 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1211 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1212 ctx->zero = tcg_constant_tl(0); 1213 ctx->virt_inst_excp = false; 1214 } 1215 1216 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1217 { 1218 } 1219 1220 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1221 { 1222 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1223 target_ulong pc_next = ctx->base.pc_next; 1224 1225 if (tb_cflags(dcbase->tb) & CF_PCREL) { 1226 pc_next &= ~TARGET_PAGE_MASK; 1227 } 1228 1229 tcg_gen_insn_start(pc_next, 0); 1230 ctx->insn_start = tcg_last_op(); 1231 } 1232 1233 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1234 { 1235 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1236 CPURISCVState *env = cpu->env_ptr; 1237 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1238 1239 ctx->ol = ctx->xl; 1240 decode_opc(env, ctx, opcode16); 1241 ctx->base.pc_next = ctx->pc_succ_insn; 1242 1243 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1244 if (ctx->base.is_jmp == DISAS_NEXT) { 1245 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1246 ctx->base.is_jmp = DISAS_TOO_MANY; 1247 } else { 1248 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1249 1250 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1251 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1252 int len = insn_len(next_insn); 1253 1254 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1255 ctx->base.is_jmp = DISAS_TOO_MANY; 1256 } 1257 } 1258 } 1259 } 1260 } 1261 1262 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1263 { 1264 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1265 1266 switch (ctx->base.is_jmp) { 1267 case DISAS_TOO_MANY: 1268 gen_goto_tb(ctx, 0, 0); 1269 break; 1270 case DISAS_NORETURN: 1271 break; 1272 default: 1273 g_assert_not_reached(); 1274 } 1275 } 1276 1277 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1278 CPUState *cpu, FILE *logfile) 1279 { 1280 #ifndef CONFIG_USER_ONLY 1281 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1282 CPURISCVState *env = &rvcpu->env; 1283 #endif 1284 1285 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1286 #ifndef CONFIG_USER_ONLY 1287 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n", 1288 env->priv, env->virt_enabled); 1289 #endif 1290 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1291 } 1292 1293 static const TranslatorOps riscv_tr_ops = { 1294 .init_disas_context = riscv_tr_init_disas_context, 1295 .tb_start = riscv_tr_tb_start, 1296 .insn_start = riscv_tr_insn_start, 1297 .translate_insn = riscv_tr_translate_insn, 1298 .tb_stop = riscv_tr_tb_stop, 1299 .disas_log = riscv_tr_disas_log, 1300 }; 1301 1302 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1303 target_ulong pc, void *host_pc) 1304 { 1305 DisasContext ctx; 1306 1307 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1308 } 1309 1310 void riscv_translate_init(void) 1311 { 1312 int i; 1313 1314 /* 1315 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1316 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1317 * unless you specifically block reads/writes to reg 0. 1318 */ 1319 cpu_gpr[0] = NULL; 1320 cpu_gprh[0] = NULL; 1321 1322 for (i = 1; i < 32; i++) { 1323 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1324 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1325 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1326 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1327 } 1328 1329 for (i = 0; i < 32; i++) { 1330 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1331 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1332 } 1333 1334 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1335 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1336 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1337 "vstart"); 1338 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1339 "load_res"); 1340 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1341 "load_val"); 1342 /* Assign PM CSRs to tcg globals */ 1343 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1344 "pmmask"); 1345 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1346 "pmbase"); 1347 } 1348