1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool hlsx; 81 /* vector extension */ 82 bool vill; 83 /* 84 * Encode LMUL to lmul as follows: 85 * LMUL vlmul lmul 86 * 1 000 0 87 * 2 001 1 88 * 4 010 2 89 * 8 011 3 90 * - 100 - 91 * 1/8 101 -3 92 * 1/4 110 -2 93 * 1/2 111 -1 94 */ 95 int8_t lmul; 96 uint8_t sew; 97 uint8_t vta; 98 uint8_t vma; 99 bool cfg_vta_all_1s; 100 target_ulong vstart; 101 bool vl_eq_vlmax; 102 uint8_t ntemp; 103 CPUState *cs; 104 TCGv zero; 105 /* Space for 3 operands plus 1 extra for address computation. */ 106 TCGv temp[4]; 107 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 108 TCGv_i64 ftemp[4]; 109 uint8_t nftemp; 110 /* PointerMasking extension */ 111 bool pm_mask_enabled; 112 bool pm_base_enabled; 113 /* TCG of the current insn_start */ 114 TCGOp *insn_start; 115 } DisasContext; 116 117 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 118 { 119 return ctx->misa_ext & ext; 120 } 121 122 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 123 { 124 return true; 125 } 126 127 #define MATERIALISE_EXT_PREDICATE(ext) \ 128 static bool has_ ## ext ## _p(DisasContext *ctx) \ 129 { \ 130 return ctx->cfg_ptr->ext_ ## ext ; \ 131 } 132 133 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 134 135 #ifdef TARGET_RISCV32 136 #define get_xl(ctx) MXL_RV32 137 #elif defined(CONFIG_USER_ONLY) 138 #define get_xl(ctx) MXL_RV64 139 #else 140 #define get_xl(ctx) ((ctx)->xl) 141 #endif 142 143 /* The word size for this machine mode. */ 144 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 145 { 146 return 16 << get_xl(ctx); 147 } 148 149 /* The operation length, as opposed to the xlen. */ 150 #ifdef TARGET_RISCV32 151 #define get_ol(ctx) MXL_RV32 152 #else 153 #define get_ol(ctx) ((ctx)->ol) 154 #endif 155 156 static inline int get_olen(DisasContext *ctx) 157 { 158 return 16 << get_ol(ctx); 159 } 160 161 /* The maximum register length */ 162 #ifdef TARGET_RISCV32 163 #define get_xl_max(ctx) MXL_RV32 164 #else 165 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 166 #endif 167 168 /* 169 * RISC-V requires NaN-boxing of narrower width floating point values. 170 * This applies when a 32-bit value is assigned to a 64-bit FP register. 171 * For consistency and simplicity, we nanbox results even when the RVD 172 * extension is not present. 173 */ 174 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 175 { 176 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 177 } 178 179 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 180 { 181 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 182 } 183 184 /* 185 * A narrow n-bit operation, where n < FLEN, checks that input operands 186 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 187 * If so, the least-significant bits of the input are used, otherwise the 188 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 189 * 190 * Here, the result is always nan-boxed, even the canonical nan. 191 */ 192 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 193 { 194 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 195 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 196 197 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 198 tcg_temp_free_i64(t_max); 199 tcg_temp_free_i64(t_nan); 200 } 201 202 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 203 { 204 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 205 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 206 207 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 208 } 209 210 static void decode_save_opc(DisasContext *ctx) 211 { 212 assert(ctx->insn_start != NULL); 213 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 214 ctx->insn_start = NULL; 215 } 216 217 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 218 { 219 if (get_xl(ctx) == MXL_RV32) { 220 dest = (int32_t)dest; 221 } 222 tcg_gen_movi_tl(cpu_pc, dest); 223 } 224 225 static void gen_set_pc(DisasContext *ctx, TCGv dest) 226 { 227 if (get_xl(ctx) == MXL_RV32) { 228 tcg_gen_ext32s_tl(cpu_pc, dest); 229 } else { 230 tcg_gen_mov_tl(cpu_pc, dest); 231 } 232 } 233 234 static void generate_exception(DisasContext *ctx, int excp) 235 { 236 gen_set_pc_imm(ctx, ctx->base.pc_next); 237 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 238 ctx->base.is_jmp = DISAS_NORETURN; 239 } 240 241 static void gen_exception_illegal(DisasContext *ctx) 242 { 243 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 244 offsetof(CPURISCVState, bins)); 245 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 246 } 247 248 static void gen_exception_inst_addr_mis(DisasContext *ctx) 249 { 250 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 251 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 252 } 253 254 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 255 { 256 if (translator_use_goto_tb(&ctx->base, dest)) { 257 tcg_gen_goto_tb(n); 258 gen_set_pc_imm(ctx, dest); 259 tcg_gen_exit_tb(ctx->base.tb, n); 260 } else { 261 gen_set_pc_imm(ctx, dest); 262 tcg_gen_lookup_and_goto_ptr(); 263 } 264 } 265 266 /* 267 * Wrappers for getting reg values. 268 * 269 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 270 * constant zero as a source, and an uninitialized sink as destination. 271 * 272 * Further, we may provide an extension for word operations. 273 */ 274 static TCGv temp_new(DisasContext *ctx) 275 { 276 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 277 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 278 } 279 280 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 281 { 282 TCGv t; 283 284 if (reg_num == 0) { 285 return ctx->zero; 286 } 287 288 switch (get_ol(ctx)) { 289 case MXL_RV32: 290 switch (ext) { 291 case EXT_NONE: 292 break; 293 case EXT_SIGN: 294 t = temp_new(ctx); 295 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 296 return t; 297 case EXT_ZERO: 298 t = temp_new(ctx); 299 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 300 return t; 301 default: 302 g_assert_not_reached(); 303 } 304 break; 305 case MXL_RV64: 306 case MXL_RV128: 307 break; 308 default: 309 g_assert_not_reached(); 310 } 311 return cpu_gpr[reg_num]; 312 } 313 314 static TCGv get_gprh(DisasContext *ctx, int reg_num) 315 { 316 assert(get_xl(ctx) == MXL_RV128); 317 if (reg_num == 0) { 318 return ctx->zero; 319 } 320 return cpu_gprh[reg_num]; 321 } 322 323 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 324 { 325 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 326 return temp_new(ctx); 327 } 328 return cpu_gpr[reg_num]; 329 } 330 331 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 332 { 333 if (reg_num == 0) { 334 return temp_new(ctx); 335 } 336 return cpu_gprh[reg_num]; 337 } 338 339 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 340 { 341 if (reg_num != 0) { 342 switch (get_ol(ctx)) { 343 case MXL_RV32: 344 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 345 break; 346 case MXL_RV64: 347 case MXL_RV128: 348 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 349 break; 350 default: 351 g_assert_not_reached(); 352 } 353 354 if (get_xl_max(ctx) == MXL_RV128) { 355 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 356 } 357 } 358 } 359 360 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 361 { 362 if (reg_num != 0) { 363 switch (get_ol(ctx)) { 364 case MXL_RV32: 365 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 366 break; 367 case MXL_RV64: 368 case MXL_RV128: 369 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 370 break; 371 default: 372 g_assert_not_reached(); 373 } 374 375 if (get_xl_max(ctx) == MXL_RV128) { 376 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 377 } 378 } 379 } 380 381 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 382 { 383 assert(get_ol(ctx) == MXL_RV128); 384 if (reg_num != 0) { 385 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 386 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 387 } 388 } 389 390 static TCGv_i64 ftemp_new(DisasContext *ctx) 391 { 392 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 393 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 394 } 395 396 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 397 { 398 if (!ctx->cfg_ptr->ext_zfinx) { 399 return cpu_fpr[reg_num]; 400 } 401 402 if (reg_num == 0) { 403 return tcg_constant_i64(0); 404 } 405 switch (get_xl(ctx)) { 406 case MXL_RV32: 407 #ifdef TARGET_RISCV32 408 { 409 TCGv_i64 t = ftemp_new(ctx); 410 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 411 return t; 412 } 413 #else 414 /* fall through */ 415 case MXL_RV64: 416 return cpu_gpr[reg_num]; 417 #endif 418 default: 419 g_assert_not_reached(); 420 } 421 } 422 423 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 424 { 425 if (!ctx->cfg_ptr->ext_zfinx) { 426 return cpu_fpr[reg_num]; 427 } 428 429 if (reg_num == 0) { 430 return tcg_constant_i64(0); 431 } 432 switch (get_xl(ctx)) { 433 case MXL_RV32: 434 { 435 TCGv_i64 t = ftemp_new(ctx); 436 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 437 return t; 438 } 439 #ifdef TARGET_RISCV64 440 case MXL_RV64: 441 return cpu_gpr[reg_num]; 442 #endif 443 default: 444 g_assert_not_reached(); 445 } 446 } 447 448 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 449 { 450 if (!ctx->cfg_ptr->ext_zfinx) { 451 return cpu_fpr[reg_num]; 452 } 453 454 if (reg_num == 0) { 455 return ftemp_new(ctx); 456 } 457 458 switch (get_xl(ctx)) { 459 case MXL_RV32: 460 return ftemp_new(ctx); 461 #ifdef TARGET_RISCV64 462 case MXL_RV64: 463 return cpu_gpr[reg_num]; 464 #endif 465 default: 466 g_assert_not_reached(); 467 } 468 } 469 470 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 471 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 472 { 473 if (!ctx->cfg_ptr->ext_zfinx) { 474 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 475 return; 476 } 477 if (reg_num != 0) { 478 switch (get_xl(ctx)) { 479 case MXL_RV32: 480 #ifdef TARGET_RISCV32 481 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 482 break; 483 #else 484 /* fall through */ 485 case MXL_RV64: 486 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 487 break; 488 #endif 489 default: 490 g_assert_not_reached(); 491 } 492 } 493 } 494 495 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 496 { 497 if (!ctx->cfg_ptr->ext_zfinx) { 498 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 499 return; 500 } 501 502 if (reg_num != 0) { 503 switch (get_xl(ctx)) { 504 case MXL_RV32: 505 #ifdef TARGET_RISCV32 506 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 507 break; 508 #else 509 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 510 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 511 break; 512 case MXL_RV64: 513 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 514 break; 515 #endif 516 default: 517 g_assert_not_reached(); 518 } 519 } 520 } 521 522 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 523 { 524 target_ulong next_pc; 525 526 /* check misaligned: */ 527 next_pc = ctx->base.pc_next + imm; 528 if (!has_ext(ctx, RVC)) { 529 if ((next_pc & 0x3) != 0) { 530 gen_exception_inst_addr_mis(ctx); 531 return; 532 } 533 } 534 535 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 536 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 537 ctx->base.is_jmp = DISAS_NORETURN; 538 } 539 540 /* Compute a canonical address from a register plus offset. */ 541 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 542 { 543 TCGv addr = temp_new(ctx); 544 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 545 546 tcg_gen_addi_tl(addr, src1, imm); 547 if (ctx->pm_mask_enabled) { 548 tcg_gen_andc_tl(addr, addr, pm_mask); 549 } else if (get_xl(ctx) == MXL_RV32) { 550 tcg_gen_ext32u_tl(addr, addr); 551 } 552 if (ctx->pm_base_enabled) { 553 tcg_gen_or_tl(addr, addr, pm_base); 554 } 555 return addr; 556 } 557 558 #ifndef CONFIG_USER_ONLY 559 /* The states of mstatus_fs are: 560 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 561 * We will have already diagnosed disabled state, 562 * and need to turn initial/clean into dirty. 563 */ 564 static void mark_fs_dirty(DisasContext *ctx) 565 { 566 TCGv tmp; 567 568 if (!has_ext(ctx, RVF)) { 569 return; 570 } 571 572 if (ctx->mstatus_fs != MSTATUS_FS) { 573 /* Remember the state change for the rest of the TB. */ 574 ctx->mstatus_fs = MSTATUS_FS; 575 576 tmp = tcg_temp_new(); 577 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 578 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 579 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 580 tcg_temp_free(tmp); 581 } 582 583 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 584 /* Remember the stage change for the rest of the TB. */ 585 ctx->mstatus_hs_fs = MSTATUS_FS; 586 587 tmp = tcg_temp_new(); 588 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 589 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 590 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 591 tcg_temp_free(tmp); 592 } 593 } 594 #else 595 static inline void mark_fs_dirty(DisasContext *ctx) { } 596 #endif 597 598 #ifndef CONFIG_USER_ONLY 599 /* The states of mstatus_vs are: 600 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 601 * We will have already diagnosed disabled state, 602 * and need to turn initial/clean into dirty. 603 */ 604 static void mark_vs_dirty(DisasContext *ctx) 605 { 606 TCGv tmp; 607 608 if (ctx->mstatus_vs != MSTATUS_VS) { 609 /* Remember the state change for the rest of the TB. */ 610 ctx->mstatus_vs = MSTATUS_VS; 611 612 tmp = tcg_temp_new(); 613 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 614 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 615 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 616 tcg_temp_free(tmp); 617 } 618 619 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 620 /* Remember the stage change for the rest of the TB. */ 621 ctx->mstatus_hs_vs = MSTATUS_VS; 622 623 tmp = tcg_temp_new(); 624 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 625 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 626 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 627 tcg_temp_free(tmp); 628 } 629 } 630 #else 631 static inline void mark_vs_dirty(DisasContext *ctx) { } 632 #endif 633 634 static void gen_set_rm(DisasContext *ctx, int rm) 635 { 636 if (ctx->frm == rm) { 637 return; 638 } 639 ctx->frm = rm; 640 641 if (rm == RISCV_FRM_ROD) { 642 gen_helper_set_rod_rounding_mode(cpu_env); 643 return; 644 } 645 646 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 647 decode_save_opc(ctx); 648 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 649 } 650 651 static int ex_plus_1(DisasContext *ctx, int nf) 652 { 653 return nf + 1; 654 } 655 656 #define EX_SH(amount) \ 657 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 658 { \ 659 return imm << amount; \ 660 } 661 EX_SH(1) 662 EX_SH(2) 663 EX_SH(3) 664 EX_SH(4) 665 EX_SH(12) 666 667 #define REQUIRE_EXT(ctx, ext) do { \ 668 if (!has_ext(ctx, ext)) { \ 669 return false; \ 670 } \ 671 } while (0) 672 673 #define REQUIRE_32BIT(ctx) do { \ 674 if (get_xl(ctx) != MXL_RV32) { \ 675 return false; \ 676 } \ 677 } while (0) 678 679 #define REQUIRE_64BIT(ctx) do { \ 680 if (get_xl(ctx) != MXL_RV64) { \ 681 return false; \ 682 } \ 683 } while (0) 684 685 #define REQUIRE_128BIT(ctx) do { \ 686 if (get_xl(ctx) != MXL_RV128) { \ 687 return false; \ 688 } \ 689 } while (0) 690 691 #define REQUIRE_64_OR_128BIT(ctx) do { \ 692 if (get_xl(ctx) == MXL_RV32) { \ 693 return false; \ 694 } \ 695 } while (0) 696 697 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 698 if (!ctx->cfg_ptr->ext_##A && \ 699 !ctx->cfg_ptr->ext_##B) { \ 700 return false; \ 701 } \ 702 } while (0) 703 704 static int ex_rvc_register(DisasContext *ctx, int reg) 705 { 706 return 8 + reg; 707 } 708 709 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 710 { 711 /* For RV128 a shamt of 0 means a shift by 64. */ 712 if (get_ol(ctx) == MXL_RV128) { 713 imm = imm ? imm : 64; 714 } 715 return imm; 716 } 717 718 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 719 { 720 /* 721 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 722 * shifts, the shamt is sign-extended. 723 */ 724 if (get_ol(ctx) == MXL_RV128) { 725 imm = imm | (imm & 32) << 1; 726 imm = imm ? imm : 64; 727 } 728 return imm; 729 } 730 731 /* Include the auto-generated decoder for 32 bit insn */ 732 #include "decode-insn32.c.inc" 733 734 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 735 void (*func)(TCGv, TCGv, target_long)) 736 { 737 TCGv dest = dest_gpr(ctx, a->rd); 738 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 739 740 func(dest, src1, a->imm); 741 742 if (get_xl(ctx) == MXL_RV128) { 743 TCGv src1h = get_gprh(ctx, a->rs1); 744 TCGv desth = dest_gprh(ctx, a->rd); 745 746 func(desth, src1h, -(a->imm < 0)); 747 gen_set_gpr128(ctx, a->rd, dest, desth); 748 } else { 749 gen_set_gpr(ctx, a->rd, dest); 750 } 751 752 return true; 753 } 754 755 static bool gen_logic(DisasContext *ctx, arg_r *a, 756 void (*func)(TCGv, TCGv, TCGv)) 757 { 758 TCGv dest = dest_gpr(ctx, a->rd); 759 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 760 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 761 762 func(dest, src1, src2); 763 764 if (get_xl(ctx) == MXL_RV128) { 765 TCGv src1h = get_gprh(ctx, a->rs1); 766 TCGv src2h = get_gprh(ctx, a->rs2); 767 TCGv desth = dest_gprh(ctx, a->rd); 768 769 func(desth, src1h, src2h); 770 gen_set_gpr128(ctx, a->rd, dest, desth); 771 } else { 772 gen_set_gpr(ctx, a->rd, dest); 773 } 774 775 return true; 776 } 777 778 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 779 void (*func)(TCGv, TCGv, target_long), 780 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 781 { 782 TCGv dest = dest_gpr(ctx, a->rd); 783 TCGv src1 = get_gpr(ctx, a->rs1, ext); 784 785 if (get_ol(ctx) < MXL_RV128) { 786 func(dest, src1, a->imm); 787 gen_set_gpr(ctx, a->rd, dest); 788 } else { 789 if (f128 == NULL) { 790 return false; 791 } 792 793 TCGv src1h = get_gprh(ctx, a->rs1); 794 TCGv desth = dest_gprh(ctx, a->rd); 795 796 f128(dest, desth, src1, src1h, a->imm); 797 gen_set_gpr128(ctx, a->rd, dest, desth); 798 } 799 return true; 800 } 801 802 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 803 void (*func)(TCGv, TCGv, TCGv), 804 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 805 { 806 TCGv dest = dest_gpr(ctx, a->rd); 807 TCGv src1 = get_gpr(ctx, a->rs1, ext); 808 TCGv src2 = tcg_constant_tl(a->imm); 809 810 if (get_ol(ctx) < MXL_RV128) { 811 func(dest, src1, src2); 812 gen_set_gpr(ctx, a->rd, dest); 813 } else { 814 if (f128 == NULL) { 815 return false; 816 } 817 818 TCGv src1h = get_gprh(ctx, a->rs1); 819 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 820 TCGv desth = dest_gprh(ctx, a->rd); 821 822 f128(dest, desth, src1, src1h, src2, src2h); 823 gen_set_gpr128(ctx, a->rd, dest, desth); 824 } 825 return true; 826 } 827 828 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 829 void (*func)(TCGv, TCGv, TCGv), 830 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 831 { 832 TCGv dest = dest_gpr(ctx, a->rd); 833 TCGv src1 = get_gpr(ctx, a->rs1, ext); 834 TCGv src2 = get_gpr(ctx, a->rs2, ext); 835 836 if (get_ol(ctx) < MXL_RV128) { 837 func(dest, src1, src2); 838 gen_set_gpr(ctx, a->rd, dest); 839 } else { 840 if (f128 == NULL) { 841 return false; 842 } 843 844 TCGv src1h = get_gprh(ctx, a->rs1); 845 TCGv src2h = get_gprh(ctx, a->rs2); 846 TCGv desth = dest_gprh(ctx, a->rd); 847 848 f128(dest, desth, src1, src1h, src2, src2h); 849 gen_set_gpr128(ctx, a->rd, dest, desth); 850 } 851 return true; 852 } 853 854 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 855 void (*f_tl)(TCGv, TCGv, TCGv), 856 void (*f_32)(TCGv, TCGv, TCGv), 857 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 858 { 859 int olen = get_olen(ctx); 860 861 if (olen != TARGET_LONG_BITS) { 862 if (olen == 32) { 863 f_tl = f_32; 864 } else if (olen != 128) { 865 g_assert_not_reached(); 866 } 867 } 868 return gen_arith(ctx, a, ext, f_tl, f_128); 869 } 870 871 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 872 void (*func)(TCGv, TCGv, target_long), 873 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 874 { 875 TCGv dest, src1; 876 int max_len = get_olen(ctx); 877 878 if (a->shamt >= max_len) { 879 return false; 880 } 881 882 dest = dest_gpr(ctx, a->rd); 883 src1 = get_gpr(ctx, a->rs1, ext); 884 885 if (max_len < 128) { 886 func(dest, src1, a->shamt); 887 gen_set_gpr(ctx, a->rd, dest); 888 } else { 889 TCGv src1h = get_gprh(ctx, a->rs1); 890 TCGv desth = dest_gprh(ctx, a->rd); 891 892 if (f128 == NULL) { 893 return false; 894 } 895 f128(dest, desth, src1, src1h, a->shamt); 896 gen_set_gpr128(ctx, a->rd, dest, desth); 897 } 898 return true; 899 } 900 901 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 902 DisasExtend ext, 903 void (*f_tl)(TCGv, TCGv, target_long), 904 void (*f_32)(TCGv, TCGv, target_long), 905 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 906 target_long)) 907 { 908 int olen = get_olen(ctx); 909 if (olen != TARGET_LONG_BITS) { 910 if (olen == 32) { 911 f_tl = f_32; 912 } else if (olen != 128) { 913 g_assert_not_reached(); 914 } 915 } 916 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 917 } 918 919 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 920 void (*func)(TCGv, TCGv, TCGv)) 921 { 922 TCGv dest, src1, src2; 923 int max_len = get_olen(ctx); 924 925 if (a->shamt >= max_len) { 926 return false; 927 } 928 929 dest = dest_gpr(ctx, a->rd); 930 src1 = get_gpr(ctx, a->rs1, ext); 931 src2 = tcg_constant_tl(a->shamt); 932 933 func(dest, src1, src2); 934 935 gen_set_gpr(ctx, a->rd, dest); 936 return true; 937 } 938 939 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 940 void (*func)(TCGv, TCGv, TCGv), 941 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 942 { 943 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 944 TCGv ext2 = tcg_temp_new(); 945 int max_len = get_olen(ctx); 946 947 tcg_gen_andi_tl(ext2, src2, max_len - 1); 948 949 TCGv dest = dest_gpr(ctx, a->rd); 950 TCGv src1 = get_gpr(ctx, a->rs1, ext); 951 952 if (max_len < 128) { 953 func(dest, src1, ext2); 954 gen_set_gpr(ctx, a->rd, dest); 955 } else { 956 TCGv src1h = get_gprh(ctx, a->rs1); 957 TCGv desth = dest_gprh(ctx, a->rd); 958 959 if (f128 == NULL) { 960 return false; 961 } 962 f128(dest, desth, src1, src1h, ext2); 963 gen_set_gpr128(ctx, a->rd, dest, desth); 964 } 965 tcg_temp_free(ext2); 966 return true; 967 } 968 969 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 970 void (*f_tl)(TCGv, TCGv, TCGv), 971 void (*f_32)(TCGv, TCGv, TCGv), 972 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 973 { 974 int olen = get_olen(ctx); 975 if (olen != TARGET_LONG_BITS) { 976 if (olen == 32) { 977 f_tl = f_32; 978 } else if (olen != 128) { 979 g_assert_not_reached(); 980 } 981 } 982 return gen_shift(ctx, a, ext, f_tl, f_128); 983 } 984 985 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 986 void (*func)(TCGv, TCGv)) 987 { 988 TCGv dest = dest_gpr(ctx, a->rd); 989 TCGv src1 = get_gpr(ctx, a->rs1, ext); 990 991 func(dest, src1); 992 993 gen_set_gpr(ctx, a->rd, dest); 994 return true; 995 } 996 997 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 998 void (*f_tl)(TCGv, TCGv), 999 void (*f_32)(TCGv, TCGv)) 1000 { 1001 int olen = get_olen(ctx); 1002 1003 if (olen != TARGET_LONG_BITS) { 1004 if (olen == 32) { 1005 f_tl = f_32; 1006 } else { 1007 g_assert_not_reached(); 1008 } 1009 } 1010 return gen_unary(ctx, a, ext, f_tl); 1011 } 1012 1013 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1014 { 1015 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1016 CPUState *cpu = ctx->cs; 1017 CPURISCVState *env = cpu->env_ptr; 1018 1019 return cpu_ldl_code(env, pc); 1020 } 1021 1022 /* Include insn module translation function */ 1023 #include "insn_trans/trans_rvi.c.inc" 1024 #include "insn_trans/trans_rvm.c.inc" 1025 #include "insn_trans/trans_rva.c.inc" 1026 #include "insn_trans/trans_rvf.c.inc" 1027 #include "insn_trans/trans_rvd.c.inc" 1028 #include "insn_trans/trans_rvh.c.inc" 1029 #include "insn_trans/trans_rvv.c.inc" 1030 #include "insn_trans/trans_rvb.c.inc" 1031 #include "insn_trans/trans_rvzfh.c.inc" 1032 #include "insn_trans/trans_rvk.c.inc" 1033 #include "insn_trans/trans_privileged.c.inc" 1034 #include "insn_trans/trans_svinval.c.inc" 1035 #include "insn_trans/trans_xventanacondops.c.inc" 1036 1037 /* Include the auto-generated decoder for 16 bit insn */ 1038 #include "decode-insn16.c.inc" 1039 /* Include decoders for factored-out extensions */ 1040 #include "decode-XVentanaCondOps.c.inc" 1041 1042 /* The specification allows for longer insns, but not supported by qemu. */ 1043 #define MAX_INSN_LEN 4 1044 1045 static inline int insn_len(uint16_t first_word) 1046 { 1047 return (first_word & 3) == 3 ? 4 : 2; 1048 } 1049 1050 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1051 { 1052 /* 1053 * A table with predicate (i.e., guard) functions and decoder functions 1054 * that are tested in-order until a decoder matches onto the opcode. 1055 */ 1056 static const struct { 1057 bool (*guard_func)(DisasContext *); 1058 bool (*decode_func)(DisasContext *, uint32_t); 1059 } decoders[] = { 1060 { always_true_p, decode_insn32 }, 1061 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1062 }; 1063 1064 /* Check for compressed insn */ 1065 if (insn_len(opcode) == 2) { 1066 if (!has_ext(ctx, RVC)) { 1067 gen_exception_illegal(ctx); 1068 } else { 1069 ctx->opcode = opcode; 1070 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1071 if (decode_insn16(ctx, opcode)) { 1072 return; 1073 } 1074 } 1075 } else { 1076 uint32_t opcode32 = opcode; 1077 opcode32 = deposit32(opcode32, 16, 16, 1078 translator_lduw(env, &ctx->base, 1079 ctx->base.pc_next + 2)); 1080 ctx->opcode = opcode32; 1081 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1082 1083 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1084 if (decoders[i].guard_func(ctx) && 1085 decoders[i].decode_func(ctx, opcode32)) { 1086 return; 1087 } 1088 } 1089 } 1090 1091 gen_exception_illegal(ctx); 1092 } 1093 1094 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1095 { 1096 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1097 CPURISCVState *env = cs->env_ptr; 1098 RISCVCPU *cpu = RISCV_CPU(cs); 1099 uint32_t tb_flags = ctx->base.tb->flags; 1100 1101 ctx->pc_succ_insn = ctx->base.pc_first; 1102 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1103 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1104 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1105 ctx->priv_ver = env->priv_ver; 1106 #if !defined(CONFIG_USER_ONLY) 1107 if (riscv_has_ext(env, RVH)) { 1108 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1109 } else { 1110 ctx->virt_enabled = false; 1111 } 1112 #else 1113 ctx->virt_enabled = false; 1114 #endif 1115 ctx->misa_ext = env->misa_ext; 1116 ctx->frm = -1; /* unknown rounding mode */ 1117 ctx->cfg_ptr = &(cpu->cfg); 1118 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1119 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1120 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1121 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1122 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1123 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1124 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1125 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1126 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1127 ctx->vstart = env->vstart; 1128 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1129 ctx->misa_mxl_max = env->misa_mxl_max; 1130 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1131 ctx->cs = cs; 1132 ctx->ntemp = 0; 1133 memset(ctx->temp, 0, sizeof(ctx->temp)); 1134 ctx->nftemp = 0; 1135 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1136 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1137 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1138 ctx->zero = tcg_constant_tl(0); 1139 } 1140 1141 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1142 { 1143 } 1144 1145 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1146 { 1147 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1148 1149 tcg_gen_insn_start(ctx->base.pc_next, 0); 1150 ctx->insn_start = tcg_last_op(); 1151 } 1152 1153 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1154 { 1155 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1156 CPURISCVState *env = cpu->env_ptr; 1157 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1158 int i; 1159 1160 ctx->ol = ctx->xl; 1161 decode_opc(env, ctx, opcode16); 1162 ctx->base.pc_next = ctx->pc_succ_insn; 1163 1164 for (i = ctx->ntemp - 1; i >= 0; --i) { 1165 tcg_temp_free(ctx->temp[i]); 1166 ctx->temp[i] = NULL; 1167 } 1168 ctx->ntemp = 0; 1169 for (i = ctx->nftemp - 1; i >= 0; --i) { 1170 tcg_temp_free_i64(ctx->ftemp[i]); 1171 ctx->ftemp[i] = NULL; 1172 } 1173 ctx->nftemp = 0; 1174 1175 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1176 if (ctx->base.is_jmp == DISAS_NEXT) { 1177 if (!is_same_page(&ctx->base, ctx->base.pc_next)) { 1178 ctx->base.is_jmp = DISAS_TOO_MANY; 1179 } else { 1180 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1181 1182 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1183 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1184 int len = insn_len(next_insn); 1185 1186 if (!is_same_page(&ctx->base, ctx->base.pc_next + len)) { 1187 ctx->base.is_jmp = DISAS_TOO_MANY; 1188 } 1189 } 1190 } 1191 } 1192 } 1193 1194 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1195 { 1196 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1197 1198 switch (ctx->base.is_jmp) { 1199 case DISAS_TOO_MANY: 1200 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1201 break; 1202 case DISAS_NORETURN: 1203 break; 1204 default: 1205 g_assert_not_reached(); 1206 } 1207 } 1208 1209 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1210 CPUState *cpu, FILE *logfile) 1211 { 1212 #ifndef CONFIG_USER_ONLY 1213 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1214 CPURISCVState *env = &rvcpu->env; 1215 #endif 1216 1217 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1218 #ifndef CONFIG_USER_ONLY 1219 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1220 env->priv, env->virt); 1221 #endif 1222 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1223 } 1224 1225 static const TranslatorOps riscv_tr_ops = { 1226 .init_disas_context = riscv_tr_init_disas_context, 1227 .tb_start = riscv_tr_tb_start, 1228 .insn_start = riscv_tr_insn_start, 1229 .translate_insn = riscv_tr_translate_insn, 1230 .tb_stop = riscv_tr_tb_stop, 1231 .disas_log = riscv_tr_disas_log, 1232 }; 1233 1234 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 1235 target_ulong pc, void *host_pc) 1236 { 1237 DisasContext ctx; 1238 1239 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1240 } 1241 1242 void riscv_translate_init(void) 1243 { 1244 int i; 1245 1246 /* 1247 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1248 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1249 * unless you specifically block reads/writes to reg 0. 1250 */ 1251 cpu_gpr[0] = NULL; 1252 cpu_gprh[0] = NULL; 1253 1254 for (i = 1; i < 32; i++) { 1255 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1256 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1257 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1258 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1259 } 1260 1261 for (i = 0; i < 32; i++) { 1262 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1263 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1264 } 1265 1266 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1267 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1268 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1269 "vstart"); 1270 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1271 "load_res"); 1272 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1273 "load_val"); 1274 /* Assign PM CSRs to tcg globals */ 1275 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1276 "pmmask"); 1277 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1278 "pmbase"); 1279 } 1280