1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 /* global register indices */ 37 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 38 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 39 static TCGv load_res; 40 static TCGv load_val; 41 /* globals for PM CSRs */ 42 static TCGv pm_mask; 43 static TCGv pm_base; 44 45 #include "exec/gen-icount.h" 46 47 /* 48 * If an operation is being performed on less than TARGET_LONG_BITS, 49 * it may require the inputs to be sign- or zero-extended; which will 50 * depend on the exact operation being performed. 51 */ 52 typedef enum { 53 EXT_NONE, 54 EXT_SIGN, 55 EXT_ZERO, 56 } DisasExtend; 57 58 typedef struct DisasContext { 59 DisasContextBase base; 60 /* pc_succ_insn points to the instruction following base.pc_next */ 61 target_ulong pc_succ_insn; 62 target_ulong priv_ver; 63 RISCVMXL misa_mxl_max; 64 RISCVMXL xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 uint32_t mstatus_fs; 68 uint32_t mstatus_vs; 69 uint32_t mstatus_hs_fs; 70 uint32_t mstatus_hs_vs; 71 uint32_t mem_idx; 72 /* Remember the rounding mode encoded in the previous fp instruction, 73 which we have already installed into env->fp_status. Or -1 for 74 no previous fp instruction. Note that we exit the TB when writing 75 to any system register, which includes CSR_FRM, so we do not have 76 to reset this known value. */ 77 int frm; 78 RISCVMXL ol; 79 bool virt_inst_excp; 80 bool virt_enabled; 81 const RISCVCPUConfig *cfg_ptr; 82 bool hlsx; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint8_t vta; 100 uint8_t vma; 101 bool cfg_vta_all_1s; 102 target_ulong vstart; 103 bool vl_eq_vlmax; 104 uint8_t ntemp; 105 CPUState *cs; 106 TCGv zero; 107 /* Space for 3 operands plus 1 extra for address computation. */ 108 TCGv temp[4]; 109 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 110 TCGv_i64 ftemp[4]; 111 uint8_t nftemp; 112 /* PointerMasking extension */ 113 bool pm_mask_enabled; 114 bool pm_base_enabled; 115 /* Use icount trigger for native debug */ 116 bool itrigger; 117 /* FRM is known to contain a valid value. */ 118 bool frm_valid; 119 /* TCG of the current insn_start */ 120 TCGOp *insn_start; 121 } DisasContext; 122 123 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 124 { 125 return ctx->misa_ext & ext; 126 } 127 128 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 129 { 130 return true; 131 } 132 133 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) 134 { 135 return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || 136 ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || 137 ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync; 138 } 139 140 #define MATERIALISE_EXT_PREDICATE(ext) \ 141 static bool has_ ## ext ## _p(DisasContext *ctx) \ 142 { \ 143 return ctx->cfg_ptr->ext_ ## ext ; \ 144 } 145 146 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 147 148 #ifdef TARGET_RISCV32 149 #define get_xl(ctx) MXL_RV32 150 #elif defined(CONFIG_USER_ONLY) 151 #define get_xl(ctx) MXL_RV64 152 #else 153 #define get_xl(ctx) ((ctx)->xl) 154 #endif 155 156 /* The word size for this machine mode. */ 157 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 158 { 159 return 16 << get_xl(ctx); 160 } 161 162 /* The operation length, as opposed to the xlen. */ 163 #ifdef TARGET_RISCV32 164 #define get_ol(ctx) MXL_RV32 165 #else 166 #define get_ol(ctx) ((ctx)->ol) 167 #endif 168 169 static inline int get_olen(DisasContext *ctx) 170 { 171 return 16 << get_ol(ctx); 172 } 173 174 /* The maximum register length */ 175 #ifdef TARGET_RISCV32 176 #define get_xl_max(ctx) MXL_RV32 177 #else 178 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 179 #endif 180 181 /* 182 * RISC-V requires NaN-boxing of narrower width floating point values. 183 * This applies when a 32-bit value is assigned to a 64-bit FP register. 184 * For consistency and simplicity, we nanbox results even when the RVD 185 * extension is not present. 186 */ 187 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 188 { 189 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 190 } 191 192 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 193 { 194 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 195 } 196 197 /* 198 * A narrow n-bit operation, where n < FLEN, checks that input operands 199 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 200 * If so, the least-significant bits of the input are used, otherwise the 201 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 202 * 203 * Here, the result is always nan-boxed, even the canonical nan. 204 */ 205 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 206 { 207 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 208 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 209 210 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 211 tcg_temp_free_i64(t_max); 212 tcg_temp_free_i64(t_nan); 213 } 214 215 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 216 { 217 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 218 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 219 220 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 221 } 222 223 static void decode_save_opc(DisasContext *ctx) 224 { 225 assert(ctx->insn_start != NULL); 226 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 227 ctx->insn_start = NULL; 228 } 229 230 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 231 { 232 if (get_xl(ctx) == MXL_RV32) { 233 dest = (int32_t)dest; 234 } 235 tcg_gen_movi_tl(cpu_pc, dest); 236 } 237 238 static void gen_set_pc(DisasContext *ctx, TCGv dest) 239 { 240 if (get_xl(ctx) == MXL_RV32) { 241 tcg_gen_ext32s_tl(cpu_pc, dest); 242 } else { 243 tcg_gen_mov_tl(cpu_pc, dest); 244 } 245 } 246 247 static void generate_exception(DisasContext *ctx, int excp) 248 { 249 gen_set_pc_imm(ctx, ctx->base.pc_next); 250 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 251 ctx->base.is_jmp = DISAS_NORETURN; 252 } 253 254 static void gen_exception_illegal(DisasContext *ctx) 255 { 256 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 257 offsetof(CPURISCVState, bins)); 258 if (ctx->virt_inst_excp) { 259 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 260 } else { 261 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 262 } 263 } 264 265 static void gen_exception_inst_addr_mis(DisasContext *ctx) 266 { 267 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 268 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 269 } 270 271 static void lookup_and_goto_ptr(DisasContext *ctx) 272 { 273 #ifndef CONFIG_USER_ONLY 274 if (ctx->itrigger) { 275 gen_helper_itrigger_match(cpu_env); 276 } 277 #endif 278 tcg_gen_lookup_and_goto_ptr(); 279 } 280 281 static void exit_tb(DisasContext *ctx) 282 { 283 #ifndef CONFIG_USER_ONLY 284 if (ctx->itrigger) { 285 gen_helper_itrigger_match(cpu_env); 286 } 287 #endif 288 tcg_gen_exit_tb(NULL, 0); 289 } 290 291 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 292 { 293 /* 294 * Under itrigger, instruction executes one by one like singlestep, 295 * direct block chain benefits will be small. 296 */ 297 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 298 tcg_gen_goto_tb(n); 299 gen_set_pc_imm(ctx, dest); 300 tcg_gen_exit_tb(ctx->base.tb, n); 301 } else { 302 gen_set_pc_imm(ctx, dest); 303 lookup_and_goto_ptr(ctx); 304 } 305 } 306 307 /* 308 * Wrappers for getting reg values. 309 * 310 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 311 * constant zero as a source, and an uninitialized sink as destination. 312 * 313 * Further, we may provide an extension for word operations. 314 */ 315 static TCGv temp_new(DisasContext *ctx) 316 { 317 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 318 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 319 } 320 321 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 322 { 323 TCGv t; 324 325 if (reg_num == 0) { 326 return ctx->zero; 327 } 328 329 switch (get_ol(ctx)) { 330 case MXL_RV32: 331 switch (ext) { 332 case EXT_NONE: 333 break; 334 case EXT_SIGN: 335 t = temp_new(ctx); 336 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 337 return t; 338 case EXT_ZERO: 339 t = temp_new(ctx); 340 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 341 return t; 342 default: 343 g_assert_not_reached(); 344 } 345 break; 346 case MXL_RV64: 347 case MXL_RV128: 348 break; 349 default: 350 g_assert_not_reached(); 351 } 352 return cpu_gpr[reg_num]; 353 } 354 355 static TCGv get_gprh(DisasContext *ctx, int reg_num) 356 { 357 assert(get_xl(ctx) == MXL_RV128); 358 if (reg_num == 0) { 359 return ctx->zero; 360 } 361 return cpu_gprh[reg_num]; 362 } 363 364 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 365 { 366 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 367 return temp_new(ctx); 368 } 369 return cpu_gpr[reg_num]; 370 } 371 372 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 373 { 374 if (reg_num == 0) { 375 return temp_new(ctx); 376 } 377 return cpu_gprh[reg_num]; 378 } 379 380 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 381 { 382 if (reg_num != 0) { 383 switch (get_ol(ctx)) { 384 case MXL_RV32: 385 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 386 break; 387 case MXL_RV64: 388 case MXL_RV128: 389 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 390 break; 391 default: 392 g_assert_not_reached(); 393 } 394 395 if (get_xl_max(ctx) == MXL_RV128) { 396 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 397 } 398 } 399 } 400 401 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 402 { 403 if (reg_num != 0) { 404 switch (get_ol(ctx)) { 405 case MXL_RV32: 406 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 407 break; 408 case MXL_RV64: 409 case MXL_RV128: 410 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 411 break; 412 default: 413 g_assert_not_reached(); 414 } 415 416 if (get_xl_max(ctx) == MXL_RV128) { 417 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 418 } 419 } 420 } 421 422 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 423 { 424 assert(get_ol(ctx) == MXL_RV128); 425 if (reg_num != 0) { 426 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 427 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 428 } 429 } 430 431 static TCGv_i64 ftemp_new(DisasContext *ctx) 432 { 433 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 434 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 435 } 436 437 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 438 { 439 if (!ctx->cfg_ptr->ext_zfinx) { 440 return cpu_fpr[reg_num]; 441 } 442 443 if (reg_num == 0) { 444 return tcg_constant_i64(0); 445 } 446 switch (get_xl(ctx)) { 447 case MXL_RV32: 448 #ifdef TARGET_RISCV32 449 { 450 TCGv_i64 t = ftemp_new(ctx); 451 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 452 return t; 453 } 454 #else 455 /* fall through */ 456 case MXL_RV64: 457 return cpu_gpr[reg_num]; 458 #endif 459 default: 460 g_assert_not_reached(); 461 } 462 } 463 464 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 465 { 466 if (!ctx->cfg_ptr->ext_zfinx) { 467 return cpu_fpr[reg_num]; 468 } 469 470 if (reg_num == 0) { 471 return tcg_constant_i64(0); 472 } 473 switch (get_xl(ctx)) { 474 case MXL_RV32: 475 { 476 TCGv_i64 t = ftemp_new(ctx); 477 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 478 return t; 479 } 480 #ifdef TARGET_RISCV64 481 case MXL_RV64: 482 return cpu_gpr[reg_num]; 483 #endif 484 default: 485 g_assert_not_reached(); 486 } 487 } 488 489 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 490 { 491 if (!ctx->cfg_ptr->ext_zfinx) { 492 return cpu_fpr[reg_num]; 493 } 494 495 if (reg_num == 0) { 496 return ftemp_new(ctx); 497 } 498 499 switch (get_xl(ctx)) { 500 case MXL_RV32: 501 return ftemp_new(ctx); 502 #ifdef TARGET_RISCV64 503 case MXL_RV64: 504 return cpu_gpr[reg_num]; 505 #endif 506 default: 507 g_assert_not_reached(); 508 } 509 } 510 511 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 512 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 513 { 514 if (!ctx->cfg_ptr->ext_zfinx) { 515 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 516 return; 517 } 518 if (reg_num != 0) { 519 switch (get_xl(ctx)) { 520 case MXL_RV32: 521 #ifdef TARGET_RISCV32 522 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 523 break; 524 #else 525 /* fall through */ 526 case MXL_RV64: 527 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 528 break; 529 #endif 530 default: 531 g_assert_not_reached(); 532 } 533 } 534 } 535 536 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 537 { 538 if (!ctx->cfg_ptr->ext_zfinx) { 539 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 540 return; 541 } 542 543 if (reg_num != 0) { 544 switch (get_xl(ctx)) { 545 case MXL_RV32: 546 #ifdef TARGET_RISCV32 547 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 548 break; 549 #else 550 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 551 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 552 break; 553 case MXL_RV64: 554 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 555 break; 556 #endif 557 default: 558 g_assert_not_reached(); 559 } 560 } 561 } 562 563 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 564 { 565 target_ulong next_pc; 566 567 /* check misaligned: */ 568 next_pc = ctx->base.pc_next + imm; 569 if (!has_ext(ctx, RVC)) { 570 if ((next_pc & 0x3) != 0) { 571 gen_exception_inst_addr_mis(ctx); 572 return; 573 } 574 } 575 576 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 577 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 578 ctx->base.is_jmp = DISAS_NORETURN; 579 } 580 581 /* Compute a canonical address from a register plus offset. */ 582 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 583 { 584 TCGv addr = temp_new(ctx); 585 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 586 587 tcg_gen_addi_tl(addr, src1, imm); 588 if (ctx->pm_mask_enabled) { 589 tcg_gen_andc_tl(addr, addr, pm_mask); 590 } else if (get_xl(ctx) == MXL_RV32) { 591 tcg_gen_ext32u_tl(addr, addr); 592 } 593 if (ctx->pm_base_enabled) { 594 tcg_gen_or_tl(addr, addr, pm_base); 595 } 596 return addr; 597 } 598 599 #ifndef CONFIG_USER_ONLY 600 /* The states of mstatus_fs are: 601 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 602 * We will have already diagnosed disabled state, 603 * and need to turn initial/clean into dirty. 604 */ 605 static void mark_fs_dirty(DisasContext *ctx) 606 { 607 TCGv tmp; 608 609 if (!has_ext(ctx, RVF)) { 610 return; 611 } 612 613 if (ctx->mstatus_fs != MSTATUS_FS) { 614 /* Remember the state change for the rest of the TB. */ 615 ctx->mstatus_fs = MSTATUS_FS; 616 617 tmp = tcg_temp_new(); 618 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 619 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 620 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 621 tcg_temp_free(tmp); 622 } 623 624 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 625 /* Remember the stage change for the rest of the TB. */ 626 ctx->mstatus_hs_fs = MSTATUS_FS; 627 628 tmp = tcg_temp_new(); 629 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 630 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 631 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 632 tcg_temp_free(tmp); 633 } 634 } 635 #else 636 static inline void mark_fs_dirty(DisasContext *ctx) { } 637 #endif 638 639 #ifndef CONFIG_USER_ONLY 640 /* The states of mstatus_vs are: 641 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 642 * We will have already diagnosed disabled state, 643 * and need to turn initial/clean into dirty. 644 */ 645 static void mark_vs_dirty(DisasContext *ctx) 646 { 647 TCGv tmp; 648 649 if (ctx->mstatus_vs != MSTATUS_VS) { 650 /* Remember the state change for the rest of the TB. */ 651 ctx->mstatus_vs = MSTATUS_VS; 652 653 tmp = tcg_temp_new(); 654 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 655 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 656 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 657 tcg_temp_free(tmp); 658 } 659 660 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 661 /* Remember the stage change for the rest of the TB. */ 662 ctx->mstatus_hs_vs = MSTATUS_VS; 663 664 tmp = tcg_temp_new(); 665 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 666 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 667 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 668 tcg_temp_free(tmp); 669 } 670 } 671 #else 672 static inline void mark_vs_dirty(DisasContext *ctx) { } 673 #endif 674 675 static void gen_set_rm(DisasContext *ctx, int rm) 676 { 677 if (ctx->frm == rm) { 678 return; 679 } 680 ctx->frm = rm; 681 682 if (rm == RISCV_FRM_DYN) { 683 /* The helper will return only if frm valid. */ 684 ctx->frm_valid = true; 685 } 686 687 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 688 decode_save_opc(ctx); 689 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 690 } 691 692 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 693 { 694 if (ctx->frm == rm && ctx->frm_valid) { 695 return; 696 } 697 ctx->frm = rm; 698 ctx->frm_valid = true; 699 700 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 701 decode_save_opc(ctx); 702 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 703 } 704 705 static int ex_plus_1(DisasContext *ctx, int nf) 706 { 707 return nf + 1; 708 } 709 710 #define EX_SH(amount) \ 711 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 712 { \ 713 return imm << amount; \ 714 } 715 EX_SH(1) 716 EX_SH(2) 717 EX_SH(3) 718 EX_SH(4) 719 EX_SH(12) 720 721 #define REQUIRE_EXT(ctx, ext) do { \ 722 if (!has_ext(ctx, ext)) { \ 723 return false; \ 724 } \ 725 } while (0) 726 727 #define REQUIRE_32BIT(ctx) do { \ 728 if (get_xl(ctx) != MXL_RV32) { \ 729 return false; \ 730 } \ 731 } while (0) 732 733 #define REQUIRE_64BIT(ctx) do { \ 734 if (get_xl(ctx) != MXL_RV64) { \ 735 return false; \ 736 } \ 737 } while (0) 738 739 #define REQUIRE_128BIT(ctx) do { \ 740 if (get_xl(ctx) != MXL_RV128) { \ 741 return false; \ 742 } \ 743 } while (0) 744 745 #define REQUIRE_64_OR_128BIT(ctx) do { \ 746 if (get_xl(ctx) == MXL_RV32) { \ 747 return false; \ 748 } \ 749 } while (0) 750 751 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 752 if (!ctx->cfg_ptr->ext_##A && \ 753 !ctx->cfg_ptr->ext_##B) { \ 754 return false; \ 755 } \ 756 } while (0) 757 758 static int ex_rvc_register(DisasContext *ctx, int reg) 759 { 760 return 8 + reg; 761 } 762 763 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 764 { 765 /* For RV128 a shamt of 0 means a shift by 64. */ 766 if (get_ol(ctx) == MXL_RV128) { 767 imm = imm ? imm : 64; 768 } 769 return imm; 770 } 771 772 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 773 { 774 /* 775 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 776 * shifts, the shamt is sign-extended. 777 */ 778 if (get_ol(ctx) == MXL_RV128) { 779 imm = imm | (imm & 32) << 1; 780 imm = imm ? imm : 64; 781 } 782 return imm; 783 } 784 785 /* Include the auto-generated decoder for 32 bit insn */ 786 #include "decode-insn32.c.inc" 787 788 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 789 void (*func)(TCGv, TCGv, target_long)) 790 { 791 TCGv dest = dest_gpr(ctx, a->rd); 792 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 793 794 func(dest, src1, a->imm); 795 796 if (get_xl(ctx) == MXL_RV128) { 797 TCGv src1h = get_gprh(ctx, a->rs1); 798 TCGv desth = dest_gprh(ctx, a->rd); 799 800 func(desth, src1h, -(a->imm < 0)); 801 gen_set_gpr128(ctx, a->rd, dest, desth); 802 } else { 803 gen_set_gpr(ctx, a->rd, dest); 804 } 805 806 return true; 807 } 808 809 static bool gen_logic(DisasContext *ctx, arg_r *a, 810 void (*func)(TCGv, TCGv, TCGv)) 811 { 812 TCGv dest = dest_gpr(ctx, a->rd); 813 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 814 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 815 816 func(dest, src1, src2); 817 818 if (get_xl(ctx) == MXL_RV128) { 819 TCGv src1h = get_gprh(ctx, a->rs1); 820 TCGv src2h = get_gprh(ctx, a->rs2); 821 TCGv desth = dest_gprh(ctx, a->rd); 822 823 func(desth, src1h, src2h); 824 gen_set_gpr128(ctx, a->rd, dest, desth); 825 } else { 826 gen_set_gpr(ctx, a->rd, dest); 827 } 828 829 return true; 830 } 831 832 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 833 void (*func)(TCGv, TCGv, target_long), 834 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 835 { 836 TCGv dest = dest_gpr(ctx, a->rd); 837 TCGv src1 = get_gpr(ctx, a->rs1, ext); 838 839 if (get_ol(ctx) < MXL_RV128) { 840 func(dest, src1, a->imm); 841 gen_set_gpr(ctx, a->rd, dest); 842 } else { 843 if (f128 == NULL) { 844 return false; 845 } 846 847 TCGv src1h = get_gprh(ctx, a->rs1); 848 TCGv desth = dest_gprh(ctx, a->rd); 849 850 f128(dest, desth, src1, src1h, a->imm); 851 gen_set_gpr128(ctx, a->rd, dest, desth); 852 } 853 return true; 854 } 855 856 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 857 void (*func)(TCGv, TCGv, TCGv), 858 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 859 { 860 TCGv dest = dest_gpr(ctx, a->rd); 861 TCGv src1 = get_gpr(ctx, a->rs1, ext); 862 TCGv src2 = tcg_constant_tl(a->imm); 863 864 if (get_ol(ctx) < MXL_RV128) { 865 func(dest, src1, src2); 866 gen_set_gpr(ctx, a->rd, dest); 867 } else { 868 if (f128 == NULL) { 869 return false; 870 } 871 872 TCGv src1h = get_gprh(ctx, a->rs1); 873 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 874 TCGv desth = dest_gprh(ctx, a->rd); 875 876 f128(dest, desth, src1, src1h, src2, src2h); 877 gen_set_gpr128(ctx, a->rd, dest, desth); 878 } 879 return true; 880 } 881 882 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 883 void (*func)(TCGv, TCGv, TCGv), 884 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 885 { 886 TCGv dest = dest_gpr(ctx, a->rd); 887 TCGv src1 = get_gpr(ctx, a->rs1, ext); 888 TCGv src2 = get_gpr(ctx, a->rs2, ext); 889 890 if (get_ol(ctx) < MXL_RV128) { 891 func(dest, src1, src2); 892 gen_set_gpr(ctx, a->rd, dest); 893 } else { 894 if (f128 == NULL) { 895 return false; 896 } 897 898 TCGv src1h = get_gprh(ctx, a->rs1); 899 TCGv src2h = get_gprh(ctx, a->rs2); 900 TCGv desth = dest_gprh(ctx, a->rd); 901 902 f128(dest, desth, src1, src1h, src2, src2h); 903 gen_set_gpr128(ctx, a->rd, dest, desth); 904 } 905 return true; 906 } 907 908 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 909 void (*f_tl)(TCGv, TCGv, TCGv), 910 void (*f_32)(TCGv, TCGv, TCGv), 911 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 912 { 913 int olen = get_olen(ctx); 914 915 if (olen != TARGET_LONG_BITS) { 916 if (olen == 32) { 917 f_tl = f_32; 918 } else if (olen != 128) { 919 g_assert_not_reached(); 920 } 921 } 922 return gen_arith(ctx, a, ext, f_tl, f_128); 923 } 924 925 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 926 void (*func)(TCGv, TCGv, target_long), 927 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 928 { 929 TCGv dest, src1; 930 int max_len = get_olen(ctx); 931 932 if (a->shamt >= max_len) { 933 return false; 934 } 935 936 dest = dest_gpr(ctx, a->rd); 937 src1 = get_gpr(ctx, a->rs1, ext); 938 939 if (max_len < 128) { 940 func(dest, src1, a->shamt); 941 gen_set_gpr(ctx, a->rd, dest); 942 } else { 943 TCGv src1h = get_gprh(ctx, a->rs1); 944 TCGv desth = dest_gprh(ctx, a->rd); 945 946 if (f128 == NULL) { 947 return false; 948 } 949 f128(dest, desth, src1, src1h, a->shamt); 950 gen_set_gpr128(ctx, a->rd, dest, desth); 951 } 952 return true; 953 } 954 955 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 956 DisasExtend ext, 957 void (*f_tl)(TCGv, TCGv, target_long), 958 void (*f_32)(TCGv, TCGv, target_long), 959 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 960 target_long)) 961 { 962 int olen = get_olen(ctx); 963 if (olen != TARGET_LONG_BITS) { 964 if (olen == 32) { 965 f_tl = f_32; 966 } else if (olen != 128) { 967 g_assert_not_reached(); 968 } 969 } 970 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 971 } 972 973 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 974 void (*func)(TCGv, TCGv, TCGv)) 975 { 976 TCGv dest, src1, src2; 977 int max_len = get_olen(ctx); 978 979 if (a->shamt >= max_len) { 980 return false; 981 } 982 983 dest = dest_gpr(ctx, a->rd); 984 src1 = get_gpr(ctx, a->rs1, ext); 985 src2 = tcg_constant_tl(a->shamt); 986 987 func(dest, src1, src2); 988 989 gen_set_gpr(ctx, a->rd, dest); 990 return true; 991 } 992 993 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 994 void (*func)(TCGv, TCGv, TCGv), 995 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 996 { 997 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 998 TCGv ext2 = tcg_temp_new(); 999 int max_len = get_olen(ctx); 1000 1001 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1002 1003 TCGv dest = dest_gpr(ctx, a->rd); 1004 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1005 1006 if (max_len < 128) { 1007 func(dest, src1, ext2); 1008 gen_set_gpr(ctx, a->rd, dest); 1009 } else { 1010 TCGv src1h = get_gprh(ctx, a->rs1); 1011 TCGv desth = dest_gprh(ctx, a->rd); 1012 1013 if (f128 == NULL) { 1014 return false; 1015 } 1016 f128(dest, desth, src1, src1h, ext2); 1017 gen_set_gpr128(ctx, a->rd, dest, desth); 1018 } 1019 tcg_temp_free(ext2); 1020 return true; 1021 } 1022 1023 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1024 void (*f_tl)(TCGv, TCGv, TCGv), 1025 void (*f_32)(TCGv, TCGv, TCGv), 1026 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1027 { 1028 int olen = get_olen(ctx); 1029 if (olen != TARGET_LONG_BITS) { 1030 if (olen == 32) { 1031 f_tl = f_32; 1032 } else if (olen != 128) { 1033 g_assert_not_reached(); 1034 } 1035 } 1036 return gen_shift(ctx, a, ext, f_tl, f_128); 1037 } 1038 1039 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1040 void (*func)(TCGv, TCGv)) 1041 { 1042 TCGv dest = dest_gpr(ctx, a->rd); 1043 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1044 1045 func(dest, src1); 1046 1047 gen_set_gpr(ctx, a->rd, dest); 1048 return true; 1049 } 1050 1051 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1052 void (*f_tl)(TCGv, TCGv), 1053 void (*f_32)(TCGv, TCGv)) 1054 { 1055 int olen = get_olen(ctx); 1056 1057 if (olen != TARGET_LONG_BITS) { 1058 if (olen == 32) { 1059 f_tl = f_32; 1060 } else { 1061 g_assert_not_reached(); 1062 } 1063 } 1064 return gen_unary(ctx, a, ext, f_tl); 1065 } 1066 1067 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1068 { 1069 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1070 CPUState *cpu = ctx->cs; 1071 CPURISCVState *env = cpu->env_ptr; 1072 1073 return cpu_ldl_code(env, pc); 1074 } 1075 1076 /* Include insn module translation function */ 1077 #include "insn_trans/trans_rvi.c.inc" 1078 #include "insn_trans/trans_rvm.c.inc" 1079 #include "insn_trans/trans_rva.c.inc" 1080 #include "insn_trans/trans_rvf.c.inc" 1081 #include "insn_trans/trans_rvd.c.inc" 1082 #include "insn_trans/trans_rvh.c.inc" 1083 #include "insn_trans/trans_rvv.c.inc" 1084 #include "insn_trans/trans_rvb.c.inc" 1085 #include "insn_trans/trans_rvzawrs.c.inc" 1086 #include "insn_trans/trans_rvzfh.c.inc" 1087 #include "insn_trans/trans_rvk.c.inc" 1088 #include "insn_trans/trans_privileged.c.inc" 1089 #include "insn_trans/trans_svinval.c.inc" 1090 #include "decode-xthead.c.inc" 1091 #include "insn_trans/trans_xthead.c.inc" 1092 #include "insn_trans/trans_xventanacondops.c.inc" 1093 1094 /* Include the auto-generated decoder for 16 bit insn */ 1095 #include "decode-insn16.c.inc" 1096 /* Include decoders for factored-out extensions */ 1097 #include "decode-XVentanaCondOps.c.inc" 1098 1099 /* The specification allows for longer insns, but not supported by qemu. */ 1100 #define MAX_INSN_LEN 4 1101 1102 static inline int insn_len(uint16_t first_word) 1103 { 1104 return (first_word & 3) == 3 ? 4 : 2; 1105 } 1106 1107 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1108 { 1109 /* 1110 * A table with predicate (i.e., guard) functions and decoder functions 1111 * that are tested in-order until a decoder matches onto the opcode. 1112 */ 1113 static const struct { 1114 bool (*guard_func)(DisasContext *); 1115 bool (*decode_func)(DisasContext *, uint32_t); 1116 } decoders[] = { 1117 { always_true_p, decode_insn32 }, 1118 { has_xthead_p, decode_xthead }, 1119 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1120 }; 1121 1122 ctx->virt_inst_excp = false; 1123 /* Check for compressed insn */ 1124 if (insn_len(opcode) == 2) { 1125 ctx->opcode = opcode; 1126 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1127 if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) { 1128 return; 1129 } 1130 } else { 1131 uint32_t opcode32 = opcode; 1132 opcode32 = deposit32(opcode32, 16, 16, 1133 translator_lduw(env, &ctx->base, 1134 ctx->base.pc_next + 2)); 1135 ctx->opcode = opcode32; 1136 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1137 1138 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1139 if (decoders[i].guard_func(ctx) && 1140 decoders[i].decode_func(ctx, opcode32)) { 1141 return; 1142 } 1143 } 1144 } 1145 1146 gen_exception_illegal(ctx); 1147 } 1148 1149 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1150 { 1151 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1152 CPURISCVState *env = cs->env_ptr; 1153 RISCVCPU *cpu = RISCV_CPU(cs); 1154 uint32_t tb_flags = ctx->base.tb->flags; 1155 1156 ctx->pc_succ_insn = ctx->base.pc_first; 1157 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1158 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1159 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1160 ctx->priv_ver = env->priv_ver; 1161 #if !defined(CONFIG_USER_ONLY) 1162 if (riscv_has_ext(env, RVH)) { 1163 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1164 } else { 1165 ctx->virt_enabled = false; 1166 } 1167 #else 1168 ctx->virt_enabled = false; 1169 #endif 1170 ctx->misa_ext = env->misa_ext; 1171 ctx->frm = -1; /* unknown rounding mode */ 1172 ctx->cfg_ptr = &(cpu->cfg); 1173 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1174 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1175 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1176 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1177 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1178 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1179 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1180 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1181 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1182 ctx->vstart = env->vstart; 1183 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1184 ctx->misa_mxl_max = env->misa_mxl_max; 1185 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1186 ctx->cs = cs; 1187 ctx->ntemp = 0; 1188 memset(ctx->temp, 0, sizeof(ctx->temp)); 1189 ctx->nftemp = 0; 1190 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1191 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1192 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1193 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1194 ctx->zero = tcg_constant_tl(0); 1195 } 1196 1197 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1198 { 1199 } 1200 1201 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1202 { 1203 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1204 1205 tcg_gen_insn_start(ctx->base.pc_next, 0); 1206 ctx->insn_start = tcg_last_op(); 1207 } 1208 1209 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1210 { 1211 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1212 CPURISCVState *env = cpu->env_ptr; 1213 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1214 int i; 1215 1216 ctx->ol = ctx->xl; 1217 decode_opc(env, ctx, opcode16); 1218 ctx->base.pc_next = ctx->pc_succ_insn; 1219 1220 for (i = ctx->ntemp - 1; i >= 0; --i) { 1221 tcg_temp_free(ctx->temp[i]); 1222 ctx->temp[i] = NULL; 1223 } 1224 ctx->ntemp = 0; 1225 for (i = ctx->nftemp - 1; i >= 0; --i) { 1226 tcg_temp_free_i64(ctx->ftemp[i]); 1227 ctx->ftemp[i] = NULL; 1228 } 1229 ctx->nftemp = 0; 1230 1231 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1232 if (ctx->base.is_jmp == DISAS_NEXT) { 1233 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1234 ctx->base.is_jmp = DISAS_TOO_MANY; 1235 } else { 1236 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1237 1238 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1239 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1240 int len = insn_len(next_insn); 1241 1242 if (!is_same_page(&ctx->base, ctx->base.pc_next + len)) { 1243 ctx->base.is_jmp = DISAS_TOO_MANY; 1244 } 1245 } 1246 } 1247 } 1248 } 1249 1250 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1251 { 1252 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1253 1254 switch (ctx->base.is_jmp) { 1255 case DISAS_TOO_MANY: 1256 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1257 break; 1258 case DISAS_NORETURN: 1259 break; 1260 default: 1261 g_assert_not_reached(); 1262 } 1263 } 1264 1265 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1266 CPUState *cpu, FILE *logfile) 1267 { 1268 #ifndef CONFIG_USER_ONLY 1269 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1270 CPURISCVState *env = &rvcpu->env; 1271 #endif 1272 1273 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1274 #ifndef CONFIG_USER_ONLY 1275 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1276 env->priv, env->virt); 1277 #endif 1278 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1279 } 1280 1281 static const TranslatorOps riscv_tr_ops = { 1282 .init_disas_context = riscv_tr_init_disas_context, 1283 .tb_start = riscv_tr_tb_start, 1284 .insn_start = riscv_tr_insn_start, 1285 .translate_insn = riscv_tr_translate_insn, 1286 .tb_stop = riscv_tr_tb_stop, 1287 .disas_log = riscv_tr_disas_log, 1288 }; 1289 1290 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 1291 target_ulong pc, void *host_pc) 1292 { 1293 DisasContext ctx; 1294 1295 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1296 } 1297 1298 void riscv_translate_init(void) 1299 { 1300 int i; 1301 1302 /* 1303 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1304 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1305 * unless you specifically block reads/writes to reg 0. 1306 */ 1307 cpu_gpr[0] = NULL; 1308 cpu_gprh[0] = NULL; 1309 1310 for (i = 1; i < 32; i++) { 1311 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1312 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1313 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1314 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1315 } 1316 1317 for (i = 0; i < 32; i++) { 1318 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1319 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1320 } 1321 1322 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1323 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1324 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1325 "vstart"); 1326 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1327 "load_res"); 1328 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1329 "load_val"); 1330 /* Assign PM CSRs to tcg globals */ 1331 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1332 "pmmask"); 1333 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1334 "pmbase"); 1335 } 1336