1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "exec/helper-gen.h" 26 27 #include "exec/translator.h" 28 #include "exec/log.h" 29 #include "semihosting/semihost.h" 30 31 #include "internals.h" 32 33 #define HELPER_H "helper.h" 34 #include "exec/helper-info.c.inc" 35 #undef HELPER_H 36 37 #include "tcg/tcg-cpu.h" 38 39 /* global register indices */ 40 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 41 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 42 static TCGv load_res; 43 static TCGv load_val; 44 /* globals for PM CSRs */ 45 static TCGv pm_mask; 46 static TCGv pm_base; 47 48 /* 49 * If an operation is being performed on less than TARGET_LONG_BITS, 50 * it may require the inputs to be sign- or zero-extended; which will 51 * depend on the exact operation being performed. 52 */ 53 typedef enum { 54 EXT_NONE, 55 EXT_SIGN, 56 EXT_ZERO, 57 } DisasExtend; 58 59 typedef struct DisasContext { 60 DisasContextBase base; 61 target_ulong cur_insn_len; 62 target_ulong pc_save; 63 target_ulong priv_ver; 64 RISCVMXL misa_mxl_max; 65 RISCVMXL xl; 66 RISCVMXL address_xl; 67 uint32_t misa_ext; 68 uint32_t opcode; 69 RISCVExtStatus mstatus_fs; 70 RISCVExtStatus mstatus_vs; 71 uint32_t mem_idx; 72 uint32_t priv; 73 /* 74 * Remember the rounding mode encoded in the previous fp instruction, 75 * which we have already installed into env->fp_status. Or -1 for 76 * no previous fp instruction. Note that we exit the TB when writing 77 * to any system register, which includes CSR_FRM, so we do not have 78 * to reset this known value. 79 */ 80 int frm; 81 RISCVMXL ol; 82 bool virt_inst_excp; 83 bool virt_enabled; 84 const RISCVCPUConfig *cfg_ptr; 85 /* vector extension */ 86 bool vill; 87 /* 88 * Encode LMUL to lmul as follows: 89 * LMUL vlmul lmul 90 * 1 000 0 91 * 2 001 1 92 * 4 010 2 93 * 8 011 3 94 * - 100 - 95 * 1/8 101 -3 96 * 1/4 110 -2 97 * 1/2 111 -1 98 */ 99 int8_t lmul; 100 uint8_t sew; 101 uint8_t vta; 102 uint8_t vma; 103 bool cfg_vta_all_1s; 104 bool vstart_eq_zero; 105 bool vl_eq_vlmax; 106 CPUState *cs; 107 TCGv zero; 108 /* PointerMasking extension */ 109 bool pm_mask_enabled; 110 bool pm_base_enabled; 111 /* Ztso */ 112 bool ztso; 113 /* Use icount trigger for native debug */ 114 bool itrigger; 115 /* FRM is known to contain a valid value. */ 116 bool frm_valid; 117 bool insn_start_updated; 118 const GPtrArray *decoders; 119 } DisasContext; 120 121 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 122 { 123 return ctx->misa_ext & ext; 124 } 125 126 #ifdef TARGET_RISCV32 127 #define get_xl(ctx) MXL_RV32 128 #elif defined(CONFIG_USER_ONLY) 129 #define get_xl(ctx) MXL_RV64 130 #else 131 #define get_xl(ctx) ((ctx)->xl) 132 #endif 133 134 #ifdef TARGET_RISCV32 135 #define get_address_xl(ctx) MXL_RV32 136 #elif defined(CONFIG_USER_ONLY) 137 #define get_address_xl(ctx) MXL_RV64 138 #else 139 #define get_address_xl(ctx) ((ctx)->address_xl) 140 #endif 141 142 /* The word size for this machine mode. */ 143 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 144 { 145 return 16 << get_xl(ctx); 146 } 147 148 /* The operation length, as opposed to the xlen. */ 149 #ifdef TARGET_RISCV32 150 #define get_ol(ctx) MXL_RV32 151 #else 152 #define get_ol(ctx) ((ctx)->ol) 153 #endif 154 155 static inline int get_olen(DisasContext *ctx) 156 { 157 return 16 << get_ol(ctx); 158 } 159 160 /* The maximum register length */ 161 #ifdef TARGET_RISCV32 162 #define get_xl_max(ctx) MXL_RV32 163 #else 164 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 165 #endif 166 167 /* 168 * RISC-V requires NaN-boxing of narrower width floating point values. 169 * This applies when a 32-bit value is assigned to a 64-bit FP register. 170 * For consistency and simplicity, we nanbox results even when the RVD 171 * extension is not present. 172 */ 173 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 174 { 175 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 176 } 177 178 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 179 { 180 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 181 } 182 183 /* 184 * A narrow n-bit operation, where n < FLEN, checks that input operands 185 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 186 * If so, the least-significant bits of the input are used, otherwise the 187 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 188 * 189 * Here, the result is always nan-boxed, even the canonical nan. 190 */ 191 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 192 { 193 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 194 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 195 196 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 197 } 198 199 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 200 { 201 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 202 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 203 204 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 205 } 206 207 static void decode_save_opc(DisasContext *ctx) 208 { 209 assert(!ctx->insn_start_updated); 210 ctx->insn_start_updated = true; 211 tcg_set_insn_start_param(ctx->base.insn_start, 1, ctx->opcode); 212 } 213 214 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, 215 target_long diff) 216 { 217 target_ulong dest = ctx->base.pc_next + diff; 218 219 assert(ctx->pc_save != -1); 220 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 221 tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save); 222 if (get_xl(ctx) == MXL_RV32) { 223 tcg_gen_ext32s_tl(target, target); 224 } 225 } else { 226 if (get_xl(ctx) == MXL_RV32) { 227 dest = (int32_t)dest; 228 } 229 tcg_gen_movi_tl(target, dest); 230 } 231 } 232 233 static void gen_update_pc(DisasContext *ctx, target_long diff) 234 { 235 gen_pc_plus_diff(cpu_pc, ctx, diff); 236 ctx->pc_save = ctx->base.pc_next + diff; 237 } 238 239 static void generate_exception(DisasContext *ctx, int excp) 240 { 241 gen_update_pc(ctx, 0); 242 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); 243 ctx->base.is_jmp = DISAS_NORETURN; 244 } 245 246 static void gen_exception_illegal(DisasContext *ctx) 247 { 248 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env, 249 offsetof(CPURISCVState, bins)); 250 if (ctx->virt_inst_excp) { 251 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 252 } else { 253 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 254 } 255 } 256 257 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) 258 { 259 tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); 260 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 261 } 262 263 static void lookup_and_goto_ptr(DisasContext *ctx) 264 { 265 #ifndef CONFIG_USER_ONLY 266 if (ctx->itrigger) { 267 gen_helper_itrigger_match(tcg_env); 268 } 269 #endif 270 tcg_gen_lookup_and_goto_ptr(); 271 } 272 273 static void exit_tb(DisasContext *ctx) 274 { 275 #ifndef CONFIG_USER_ONLY 276 if (ctx->itrigger) { 277 gen_helper_itrigger_match(tcg_env); 278 } 279 #endif 280 tcg_gen_exit_tb(NULL, 0); 281 } 282 283 static void gen_goto_tb(DisasContext *ctx, int n, target_long diff) 284 { 285 target_ulong dest = ctx->base.pc_next + diff; 286 287 /* 288 * Under itrigger, instruction executes one by one like singlestep, 289 * direct block chain benefits will be small. 290 */ 291 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 292 /* 293 * For pcrel, the pc must always be up-to-date on entry to 294 * the linked TB, so that it can use simple additions for all 295 * further adjustments. For !pcrel, the linked TB is compiled 296 * to know its full virtual address, so we can delay the 297 * update to pc to the unlinked path. A long chain of links 298 * can thus avoid many updates to the PC. 299 */ 300 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 301 gen_update_pc(ctx, diff); 302 tcg_gen_goto_tb(n); 303 } else { 304 tcg_gen_goto_tb(n); 305 gen_update_pc(ctx, diff); 306 } 307 tcg_gen_exit_tb(ctx->base.tb, n); 308 } else { 309 gen_update_pc(ctx, diff); 310 lookup_and_goto_ptr(ctx); 311 } 312 } 313 314 /* 315 * Wrappers for getting reg values. 316 * 317 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 318 * constant zero as a source, and an uninitialized sink as destination. 319 * 320 * Further, we may provide an extension for word operations. 321 */ 322 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 323 { 324 TCGv t; 325 326 if (reg_num == 0) { 327 return ctx->zero; 328 } 329 330 switch (get_ol(ctx)) { 331 case MXL_RV32: 332 switch (ext) { 333 case EXT_NONE: 334 break; 335 case EXT_SIGN: 336 t = tcg_temp_new(); 337 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 338 return t; 339 case EXT_ZERO: 340 t = tcg_temp_new(); 341 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 342 return t; 343 default: 344 g_assert_not_reached(); 345 } 346 break; 347 case MXL_RV64: 348 case MXL_RV128: 349 break; 350 default: 351 g_assert_not_reached(); 352 } 353 return cpu_gpr[reg_num]; 354 } 355 356 static TCGv get_gprh(DisasContext *ctx, int reg_num) 357 { 358 assert(get_xl(ctx) == MXL_RV128); 359 if (reg_num == 0) { 360 return ctx->zero; 361 } 362 return cpu_gprh[reg_num]; 363 } 364 365 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 366 { 367 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 368 return tcg_temp_new(); 369 } 370 return cpu_gpr[reg_num]; 371 } 372 373 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 374 { 375 if (reg_num == 0) { 376 return tcg_temp_new(); 377 } 378 return cpu_gprh[reg_num]; 379 } 380 381 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 382 { 383 if (reg_num != 0) { 384 switch (get_ol(ctx)) { 385 case MXL_RV32: 386 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 387 break; 388 case MXL_RV64: 389 case MXL_RV128: 390 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 391 break; 392 default: 393 g_assert_not_reached(); 394 } 395 396 if (get_xl_max(ctx) == MXL_RV128) { 397 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 398 } 399 } 400 } 401 402 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 403 { 404 if (reg_num != 0) { 405 switch (get_ol(ctx)) { 406 case MXL_RV32: 407 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 408 break; 409 case MXL_RV64: 410 case MXL_RV128: 411 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 412 break; 413 default: 414 g_assert_not_reached(); 415 } 416 417 if (get_xl_max(ctx) == MXL_RV128) { 418 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 419 } 420 } 421 } 422 423 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 424 { 425 assert(get_ol(ctx) == MXL_RV128); 426 if (reg_num != 0) { 427 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 428 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 429 } 430 } 431 432 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 433 { 434 if (!ctx->cfg_ptr->ext_zfinx) { 435 return cpu_fpr[reg_num]; 436 } 437 438 if (reg_num == 0) { 439 return tcg_constant_i64(0); 440 } 441 switch (get_xl(ctx)) { 442 case MXL_RV32: 443 #ifdef TARGET_RISCV32 444 { 445 TCGv_i64 t = tcg_temp_new_i64(); 446 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 447 return t; 448 } 449 #else 450 /* fall through */ 451 case MXL_RV64: 452 return cpu_gpr[reg_num]; 453 #endif 454 default: 455 g_assert_not_reached(); 456 } 457 } 458 459 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 460 { 461 if (!ctx->cfg_ptr->ext_zfinx) { 462 return cpu_fpr[reg_num]; 463 } 464 465 if (reg_num == 0) { 466 return tcg_constant_i64(0); 467 } 468 switch (get_xl(ctx)) { 469 case MXL_RV32: 470 { 471 TCGv_i64 t = tcg_temp_new_i64(); 472 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 473 return t; 474 } 475 #ifdef TARGET_RISCV64 476 case MXL_RV64: 477 return cpu_gpr[reg_num]; 478 #endif 479 default: 480 g_assert_not_reached(); 481 } 482 } 483 484 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 485 { 486 if (!ctx->cfg_ptr->ext_zfinx) { 487 return cpu_fpr[reg_num]; 488 } 489 490 if (reg_num == 0) { 491 return tcg_temp_new_i64(); 492 } 493 494 switch (get_xl(ctx)) { 495 case MXL_RV32: 496 return tcg_temp_new_i64(); 497 #ifdef TARGET_RISCV64 498 case MXL_RV64: 499 return cpu_gpr[reg_num]; 500 #endif 501 default: 502 g_assert_not_reached(); 503 } 504 } 505 506 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 507 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 508 { 509 if (!ctx->cfg_ptr->ext_zfinx) { 510 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 511 return; 512 } 513 if (reg_num != 0) { 514 switch (get_xl(ctx)) { 515 case MXL_RV32: 516 #ifdef TARGET_RISCV32 517 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 518 break; 519 #else 520 /* fall through */ 521 case MXL_RV64: 522 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 523 break; 524 #endif 525 default: 526 g_assert_not_reached(); 527 } 528 } 529 } 530 531 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 532 { 533 if (!ctx->cfg_ptr->ext_zfinx) { 534 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 535 return; 536 } 537 538 if (reg_num != 0) { 539 switch (get_xl(ctx)) { 540 case MXL_RV32: 541 #ifdef TARGET_RISCV32 542 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 543 break; 544 #else 545 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 546 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 547 break; 548 case MXL_RV64: 549 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 550 break; 551 #endif 552 default: 553 g_assert_not_reached(); 554 } 555 } 556 } 557 558 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 559 { 560 TCGv succ_pc = dest_gpr(ctx, rd); 561 562 /* check misaligned: */ 563 if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { 564 if ((imm & 0x3) != 0) { 565 TCGv target_pc = tcg_temp_new(); 566 gen_pc_plus_diff(target_pc, ctx, imm); 567 gen_exception_inst_addr_mis(ctx, target_pc); 568 return; 569 } 570 } 571 572 gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); 573 gen_set_gpr(ctx, rd, succ_pc); 574 575 gen_goto_tb(ctx, 0, imm); /* must use this for safety */ 576 ctx->base.is_jmp = DISAS_NORETURN; 577 } 578 579 /* Compute a canonical address from a register plus offset. */ 580 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 581 { 582 TCGv addr = tcg_temp_new(); 583 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 584 585 tcg_gen_addi_tl(addr, src1, imm); 586 if (ctx->pm_mask_enabled) { 587 tcg_gen_andc_tl(addr, addr, pm_mask); 588 } else if (get_address_xl(ctx) == MXL_RV32) { 589 tcg_gen_ext32u_tl(addr, addr); 590 } 591 if (ctx->pm_base_enabled) { 592 tcg_gen_or_tl(addr, addr, pm_base); 593 } 594 595 return addr; 596 } 597 598 /* Compute a canonical address from a register plus reg offset. */ 599 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 600 { 601 TCGv addr = tcg_temp_new(); 602 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 603 604 tcg_gen_add_tl(addr, src1, offs); 605 if (ctx->pm_mask_enabled) { 606 tcg_gen_andc_tl(addr, addr, pm_mask); 607 } else if (get_xl(ctx) == MXL_RV32) { 608 tcg_gen_ext32u_tl(addr, addr); 609 } 610 if (ctx->pm_base_enabled) { 611 tcg_gen_or_tl(addr, addr, pm_base); 612 } 613 return addr; 614 } 615 616 #ifndef CONFIG_USER_ONLY 617 /* 618 * We will have already diagnosed disabled state, 619 * and need to turn initial/clean into dirty. 620 */ 621 static void mark_fs_dirty(DisasContext *ctx) 622 { 623 TCGv tmp; 624 625 if (!has_ext(ctx, RVF)) { 626 return; 627 } 628 629 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 630 /* Remember the state change for the rest of the TB. */ 631 ctx->mstatus_fs = EXT_STATUS_DIRTY; 632 633 tmp = tcg_temp_new(); 634 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 635 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 636 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 637 638 if (ctx->virt_enabled) { 639 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 640 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 641 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 642 } 643 } 644 } 645 #else 646 static inline void mark_fs_dirty(DisasContext *ctx) { } 647 #endif 648 649 #ifndef CONFIG_USER_ONLY 650 /* 651 * We will have already diagnosed disabled state, 652 * and need to turn initial/clean into dirty. 653 */ 654 static void mark_vs_dirty(DisasContext *ctx) 655 { 656 TCGv tmp; 657 658 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 659 /* Remember the state change for the rest of the TB. */ 660 ctx->mstatus_vs = EXT_STATUS_DIRTY; 661 662 tmp = tcg_temp_new(); 663 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 664 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 665 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 666 667 if (ctx->virt_enabled) { 668 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 669 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 670 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 671 } 672 } 673 } 674 #else 675 static inline void mark_vs_dirty(DisasContext *ctx) { } 676 #endif 677 678 static void finalize_rvv_inst(DisasContext *ctx) 679 { 680 mark_vs_dirty(ctx); 681 ctx->vstart_eq_zero = true; 682 } 683 684 static void gen_set_rm(DisasContext *ctx, int rm) 685 { 686 if (ctx->frm == rm) { 687 return; 688 } 689 ctx->frm = rm; 690 691 if (rm == RISCV_FRM_DYN) { 692 /* The helper will return only if frm valid. */ 693 ctx->frm_valid = true; 694 } 695 696 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 697 decode_save_opc(ctx); 698 gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm)); 699 } 700 701 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 702 { 703 if (ctx->frm == rm && ctx->frm_valid) { 704 return; 705 } 706 ctx->frm = rm; 707 ctx->frm_valid = true; 708 709 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 710 decode_save_opc(ctx); 711 gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm)); 712 } 713 714 static int ex_plus_1(DisasContext *ctx, int nf) 715 { 716 return nf + 1; 717 } 718 719 #define EX_SH(amount) \ 720 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 721 { \ 722 return imm << amount; \ 723 } 724 EX_SH(1) 725 EX_SH(2) 726 EX_SH(3) 727 EX_SH(4) 728 EX_SH(12) 729 730 #define REQUIRE_EXT(ctx, ext) do { \ 731 if (!has_ext(ctx, ext)) { \ 732 return false; \ 733 } \ 734 } while (0) 735 736 #define REQUIRE_32BIT(ctx) do { \ 737 if (get_xl(ctx) != MXL_RV32) { \ 738 return false; \ 739 } \ 740 } while (0) 741 742 #define REQUIRE_64BIT(ctx) do { \ 743 if (get_xl(ctx) != MXL_RV64) { \ 744 return false; \ 745 } \ 746 } while (0) 747 748 #define REQUIRE_128BIT(ctx) do { \ 749 if (get_xl(ctx) != MXL_RV128) { \ 750 return false; \ 751 } \ 752 } while (0) 753 754 #define REQUIRE_64_OR_128BIT(ctx) do { \ 755 if (get_xl(ctx) == MXL_RV32) { \ 756 return false; \ 757 } \ 758 } while (0) 759 760 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 761 if (!ctx->cfg_ptr->ext_##A && \ 762 !ctx->cfg_ptr->ext_##B) { \ 763 return false; \ 764 } \ 765 } while (0) 766 767 static int ex_rvc_register(DisasContext *ctx, int reg) 768 { 769 return 8 + reg; 770 } 771 772 static int ex_sreg_register(DisasContext *ctx, int reg) 773 { 774 return reg < 2 ? reg + 8 : reg + 16; 775 } 776 777 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 778 { 779 /* For RV128 a shamt of 0 means a shift by 64. */ 780 if (get_ol(ctx) == MXL_RV128) { 781 imm = imm ? imm : 64; 782 } 783 return imm; 784 } 785 786 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 787 { 788 /* 789 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 790 * shifts, the shamt is sign-extended. 791 */ 792 if (get_ol(ctx) == MXL_RV128) { 793 imm = imm | (imm & 32) << 1; 794 imm = imm ? imm : 64; 795 } 796 return imm; 797 } 798 799 /* Include the auto-generated decoder for 32 bit insn */ 800 #include "decode-insn32.c.inc" 801 802 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 803 void (*func)(TCGv, TCGv, target_long)) 804 { 805 TCGv dest = dest_gpr(ctx, a->rd); 806 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 807 808 func(dest, src1, a->imm); 809 810 if (get_xl(ctx) == MXL_RV128) { 811 TCGv src1h = get_gprh(ctx, a->rs1); 812 TCGv desth = dest_gprh(ctx, a->rd); 813 814 func(desth, src1h, -(a->imm < 0)); 815 gen_set_gpr128(ctx, a->rd, dest, desth); 816 } else { 817 gen_set_gpr(ctx, a->rd, dest); 818 } 819 820 return true; 821 } 822 823 static bool gen_logic(DisasContext *ctx, arg_r *a, 824 void (*func)(TCGv, TCGv, TCGv)) 825 { 826 TCGv dest = dest_gpr(ctx, a->rd); 827 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 828 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 829 830 func(dest, src1, src2); 831 832 if (get_xl(ctx) == MXL_RV128) { 833 TCGv src1h = get_gprh(ctx, a->rs1); 834 TCGv src2h = get_gprh(ctx, a->rs2); 835 TCGv desth = dest_gprh(ctx, a->rd); 836 837 func(desth, src1h, src2h); 838 gen_set_gpr128(ctx, a->rd, dest, desth); 839 } else { 840 gen_set_gpr(ctx, a->rd, dest); 841 } 842 843 return true; 844 } 845 846 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 847 void (*func)(TCGv, TCGv, target_long), 848 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 849 { 850 TCGv dest = dest_gpr(ctx, a->rd); 851 TCGv src1 = get_gpr(ctx, a->rs1, ext); 852 853 if (get_ol(ctx) < MXL_RV128) { 854 func(dest, src1, a->imm); 855 gen_set_gpr(ctx, a->rd, dest); 856 } else { 857 if (f128 == NULL) { 858 return false; 859 } 860 861 TCGv src1h = get_gprh(ctx, a->rs1); 862 TCGv desth = dest_gprh(ctx, a->rd); 863 864 f128(dest, desth, src1, src1h, a->imm); 865 gen_set_gpr128(ctx, a->rd, dest, desth); 866 } 867 return true; 868 } 869 870 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 871 void (*func)(TCGv, TCGv, TCGv), 872 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 873 { 874 TCGv dest = dest_gpr(ctx, a->rd); 875 TCGv src1 = get_gpr(ctx, a->rs1, ext); 876 TCGv src2 = tcg_constant_tl(a->imm); 877 878 if (get_ol(ctx) < MXL_RV128) { 879 func(dest, src1, src2); 880 gen_set_gpr(ctx, a->rd, dest); 881 } else { 882 if (f128 == NULL) { 883 return false; 884 } 885 886 TCGv src1h = get_gprh(ctx, a->rs1); 887 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 888 TCGv desth = dest_gprh(ctx, a->rd); 889 890 f128(dest, desth, src1, src1h, src2, src2h); 891 gen_set_gpr128(ctx, a->rd, dest, desth); 892 } 893 return true; 894 } 895 896 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 897 void (*func)(TCGv, TCGv, TCGv), 898 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 899 { 900 TCGv dest = dest_gpr(ctx, a->rd); 901 TCGv src1 = get_gpr(ctx, a->rs1, ext); 902 TCGv src2 = get_gpr(ctx, a->rs2, ext); 903 904 if (get_ol(ctx) < MXL_RV128) { 905 func(dest, src1, src2); 906 gen_set_gpr(ctx, a->rd, dest); 907 } else { 908 if (f128 == NULL) { 909 return false; 910 } 911 912 TCGv src1h = get_gprh(ctx, a->rs1); 913 TCGv src2h = get_gprh(ctx, a->rs2); 914 TCGv desth = dest_gprh(ctx, a->rd); 915 916 f128(dest, desth, src1, src1h, src2, src2h); 917 gen_set_gpr128(ctx, a->rd, dest, desth); 918 } 919 return true; 920 } 921 922 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 923 void (*f_tl)(TCGv, TCGv, TCGv), 924 void (*f_32)(TCGv, TCGv, TCGv), 925 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 926 { 927 int olen = get_olen(ctx); 928 929 if (olen != TARGET_LONG_BITS) { 930 if (olen == 32) { 931 f_tl = f_32; 932 } else if (olen != 128) { 933 g_assert_not_reached(); 934 } 935 } 936 return gen_arith(ctx, a, ext, f_tl, f_128); 937 } 938 939 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 940 void (*func)(TCGv, TCGv, target_long), 941 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 942 { 943 TCGv dest, src1; 944 int max_len = get_olen(ctx); 945 946 if (a->shamt >= max_len) { 947 return false; 948 } 949 950 dest = dest_gpr(ctx, a->rd); 951 src1 = get_gpr(ctx, a->rs1, ext); 952 953 if (max_len < 128) { 954 func(dest, src1, a->shamt); 955 gen_set_gpr(ctx, a->rd, dest); 956 } else { 957 TCGv src1h = get_gprh(ctx, a->rs1); 958 TCGv desth = dest_gprh(ctx, a->rd); 959 960 if (f128 == NULL) { 961 return false; 962 } 963 f128(dest, desth, src1, src1h, a->shamt); 964 gen_set_gpr128(ctx, a->rd, dest, desth); 965 } 966 return true; 967 } 968 969 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 970 DisasExtend ext, 971 void (*f_tl)(TCGv, TCGv, target_long), 972 void (*f_32)(TCGv, TCGv, target_long), 973 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 974 target_long)) 975 { 976 int olen = get_olen(ctx); 977 if (olen != TARGET_LONG_BITS) { 978 if (olen == 32) { 979 f_tl = f_32; 980 } else if (olen != 128) { 981 g_assert_not_reached(); 982 } 983 } 984 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 985 } 986 987 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 988 void (*func)(TCGv, TCGv, TCGv)) 989 { 990 TCGv dest, src1, src2; 991 int max_len = get_olen(ctx); 992 993 if (a->shamt >= max_len) { 994 return false; 995 } 996 997 dest = dest_gpr(ctx, a->rd); 998 src1 = get_gpr(ctx, a->rs1, ext); 999 src2 = tcg_constant_tl(a->shamt); 1000 1001 func(dest, src1, src2); 1002 1003 gen_set_gpr(ctx, a->rd, dest); 1004 return true; 1005 } 1006 1007 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 1008 void (*func)(TCGv, TCGv, TCGv), 1009 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1010 { 1011 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1012 TCGv ext2 = tcg_temp_new(); 1013 int max_len = get_olen(ctx); 1014 1015 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1016 1017 TCGv dest = dest_gpr(ctx, a->rd); 1018 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1019 1020 if (max_len < 128) { 1021 func(dest, src1, ext2); 1022 gen_set_gpr(ctx, a->rd, dest); 1023 } else { 1024 TCGv src1h = get_gprh(ctx, a->rs1); 1025 TCGv desth = dest_gprh(ctx, a->rd); 1026 1027 if (f128 == NULL) { 1028 return false; 1029 } 1030 f128(dest, desth, src1, src1h, ext2); 1031 gen_set_gpr128(ctx, a->rd, dest, desth); 1032 } 1033 return true; 1034 } 1035 1036 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1037 void (*f_tl)(TCGv, TCGv, TCGv), 1038 void (*f_32)(TCGv, TCGv, TCGv), 1039 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1040 { 1041 int olen = get_olen(ctx); 1042 if (olen != TARGET_LONG_BITS) { 1043 if (olen == 32) { 1044 f_tl = f_32; 1045 } else if (olen != 128) { 1046 g_assert_not_reached(); 1047 } 1048 } 1049 return gen_shift(ctx, a, ext, f_tl, f_128); 1050 } 1051 1052 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1053 void (*func)(TCGv, TCGv)) 1054 { 1055 TCGv dest = dest_gpr(ctx, a->rd); 1056 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1057 1058 func(dest, src1); 1059 1060 gen_set_gpr(ctx, a->rd, dest); 1061 return true; 1062 } 1063 1064 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1065 void (*f_tl)(TCGv, TCGv), 1066 void (*f_32)(TCGv, TCGv)) 1067 { 1068 int olen = get_olen(ctx); 1069 1070 if (olen != TARGET_LONG_BITS) { 1071 if (olen == 32) { 1072 f_tl = f_32; 1073 } else { 1074 g_assert_not_reached(); 1075 } 1076 } 1077 return gen_unary(ctx, a, ext, f_tl); 1078 } 1079 1080 static bool gen_amo(DisasContext *ctx, arg_atomic *a, 1081 void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), 1082 MemOp mop) 1083 { 1084 TCGv dest = dest_gpr(ctx, a->rd); 1085 TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1086 MemOp size = mop & MO_SIZE; 1087 1088 if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) { 1089 mop |= MO_ATOM_WITHIN16; 1090 } else { 1091 mop |= MO_ALIGN; 1092 } 1093 1094 decode_save_opc(ctx); 1095 src1 = get_address(ctx, a->rs1, 0); 1096 func(dest, src1, src2, ctx->mem_idx, mop); 1097 1098 gen_set_gpr(ctx, a->rd, dest); 1099 return true; 1100 } 1101 1102 static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop) 1103 { 1104 TCGv dest = get_gpr(ctx, a->rd, EXT_NONE); 1105 TCGv src1 = get_address(ctx, a->rs1, 0); 1106 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1107 1108 decode_save_opc(ctx); 1109 tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); 1110 1111 gen_set_gpr(ctx, a->rd, dest); 1112 return true; 1113 } 1114 1115 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1116 { 1117 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1118 CPUState *cpu = ctx->cs; 1119 CPURISCVState *env = cpu_env(cpu); 1120 1121 return translator_ldl(env, &ctx->base, pc); 1122 } 1123 1124 /* Include insn module translation function */ 1125 #include "insn_trans/trans_rvi.c.inc" 1126 #include "insn_trans/trans_rvm.c.inc" 1127 #include "insn_trans/trans_rva.c.inc" 1128 #include "insn_trans/trans_rvf.c.inc" 1129 #include "insn_trans/trans_rvd.c.inc" 1130 #include "insn_trans/trans_rvh.c.inc" 1131 #include "insn_trans/trans_rvv.c.inc" 1132 #include "insn_trans/trans_rvb.c.inc" 1133 #include "insn_trans/trans_rvzicond.c.inc" 1134 #include "insn_trans/trans_rvzacas.c.inc" 1135 #include "insn_trans/trans_rvzabha.c.inc" 1136 #include "insn_trans/trans_rvzawrs.c.inc" 1137 #include "insn_trans/trans_rvzicbo.c.inc" 1138 #include "insn_trans/trans_rvzimop.c.inc" 1139 #include "insn_trans/trans_rvzfa.c.inc" 1140 #include "insn_trans/trans_rvzfh.c.inc" 1141 #include "insn_trans/trans_rvk.c.inc" 1142 #include "insn_trans/trans_rvvk.c.inc" 1143 #include "insn_trans/trans_privileged.c.inc" 1144 #include "insn_trans/trans_svinval.c.inc" 1145 #include "insn_trans/trans_rvbf16.c.inc" 1146 #include "decode-xthead.c.inc" 1147 #include "insn_trans/trans_xthead.c.inc" 1148 #include "insn_trans/trans_xventanacondops.c.inc" 1149 1150 /* Include the auto-generated decoder for 16 bit insn */ 1151 #include "decode-insn16.c.inc" 1152 #include "insn_trans/trans_rvzce.c.inc" 1153 #include "insn_trans/trans_rvzcmop.c.inc" 1154 1155 /* Include decoders for factored-out extensions */ 1156 #include "decode-XVentanaCondOps.c.inc" 1157 1158 /* The specification allows for longer insns, but not supported by qemu. */ 1159 #define MAX_INSN_LEN 4 1160 1161 static inline int insn_len(uint16_t first_word) 1162 { 1163 return (first_word & 3) == 3 ? 4 : 2; 1164 } 1165 1166 const RISCVDecoder decoder_table[] = { 1167 { always_true_p, decode_insn32 }, 1168 { has_xthead_p, decode_xthead}, 1169 { has_XVentanaCondOps_p, decode_XVentanaCodeOps}, 1170 }; 1171 1172 const size_t decoder_table_size = ARRAY_SIZE(decoder_table); 1173 1174 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1175 { 1176 ctx->virt_inst_excp = false; 1177 ctx->cur_insn_len = insn_len(opcode); 1178 /* Check for compressed insn */ 1179 if (ctx->cur_insn_len == 2) { 1180 ctx->opcode = opcode; 1181 /* 1182 * The Zca extension is added as way to refer to instructions in the C 1183 * extension that do not include the floating-point loads and stores 1184 */ 1185 if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && 1186 decode_insn16(ctx, opcode)) { 1187 return; 1188 } 1189 } else { 1190 uint32_t opcode32 = opcode; 1191 opcode32 = deposit32(opcode32, 16, 16, 1192 translator_lduw(env, &ctx->base, 1193 ctx->base.pc_next + 2)); 1194 ctx->opcode = opcode32; 1195 1196 for (guint i = 0; i < ctx->decoders->len; ++i) { 1197 riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i); 1198 if (func(ctx, opcode32)) { 1199 return; 1200 } 1201 } 1202 } 1203 1204 gen_exception_illegal(ctx); 1205 } 1206 1207 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1208 { 1209 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1210 CPURISCVState *env = cpu_env(cs); 1211 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); 1212 RISCVCPU *cpu = RISCV_CPU(cs); 1213 uint32_t tb_flags = ctx->base.tb->flags; 1214 1215 ctx->pc_save = ctx->base.pc_first; 1216 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1217 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1218 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1219 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1220 ctx->priv_ver = env->priv_ver; 1221 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1222 ctx->misa_ext = env->misa_ext; 1223 ctx->frm = -1; /* unknown rounding mode */ 1224 ctx->cfg_ptr = &(cpu->cfg); 1225 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1226 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1227 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1228 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1229 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1230 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1231 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1232 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1233 ctx->misa_mxl_max = mcc->misa_mxl_max; 1234 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1235 ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); 1236 ctx->cs = cs; 1237 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1238 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1239 ctx->ztso = cpu->cfg.ext_ztso; 1240 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1241 ctx->zero = tcg_constant_tl(0); 1242 ctx->virt_inst_excp = false; 1243 ctx->decoders = cpu->decoders; 1244 } 1245 1246 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1247 { 1248 } 1249 1250 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1251 { 1252 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1253 target_ulong pc_next = ctx->base.pc_next; 1254 1255 if (tb_cflags(dcbase->tb) & CF_PCREL) { 1256 pc_next &= ~TARGET_PAGE_MASK; 1257 } 1258 1259 tcg_gen_insn_start(pc_next, 0); 1260 ctx->insn_start_updated = false; 1261 } 1262 1263 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1264 { 1265 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1266 CPURISCVState *env = cpu_env(cpu); 1267 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1268 1269 ctx->ol = ctx->xl; 1270 decode_opc(env, ctx, opcode16); 1271 ctx->base.pc_next += ctx->cur_insn_len; 1272 1273 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1274 if (ctx->base.is_jmp == DISAS_NEXT) { 1275 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1276 ctx->base.is_jmp = DISAS_TOO_MANY; 1277 } else { 1278 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1279 1280 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1281 uint16_t next_insn = 1282 translator_lduw(env, &ctx->base, ctx->base.pc_next); 1283 int len = insn_len(next_insn); 1284 1285 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1286 ctx->base.is_jmp = DISAS_TOO_MANY; 1287 } 1288 } 1289 } 1290 } 1291 } 1292 1293 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1294 { 1295 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1296 1297 switch (ctx->base.is_jmp) { 1298 case DISAS_TOO_MANY: 1299 gen_goto_tb(ctx, 0, 0); 1300 break; 1301 case DISAS_NORETURN: 1302 break; 1303 default: 1304 g_assert_not_reached(); 1305 } 1306 } 1307 1308 static const TranslatorOps riscv_tr_ops = { 1309 .init_disas_context = riscv_tr_init_disas_context, 1310 .tb_start = riscv_tr_tb_start, 1311 .insn_start = riscv_tr_insn_start, 1312 .translate_insn = riscv_tr_translate_insn, 1313 .tb_stop = riscv_tr_tb_stop, 1314 }; 1315 1316 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1317 vaddr pc, void *host_pc) 1318 { 1319 DisasContext ctx; 1320 1321 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1322 } 1323 1324 void riscv_translate_init(void) 1325 { 1326 int i; 1327 1328 /* 1329 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1330 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1331 * unless you specifically block reads/writes to reg 0. 1332 */ 1333 cpu_gpr[0] = NULL; 1334 cpu_gprh[0] = NULL; 1335 1336 for (i = 1; i < 32; i++) { 1337 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 1338 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1339 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 1340 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1341 } 1342 1343 for (i = 0; i < 32; i++) { 1344 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env, 1345 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1346 } 1347 1348 cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc"); 1349 cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl"); 1350 cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart), 1351 "vstart"); 1352 load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res), 1353 "load_res"); 1354 load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val), 1355 "load_val"); 1356 /* Assign PM CSRs to tcg globals */ 1357 pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask), 1358 "pmmask"); 1359 pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase), 1360 "pmbase"); 1361 } 1362