1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 #define HELPER_H "helper.h" 37 #include "exec/helper-info.c.inc" 38 #undef HELPER_H 39 40 /* global register indices */ 41 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 42 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 43 static TCGv load_res; 44 static TCGv load_val; 45 /* globals for PM CSRs */ 46 static TCGv pm_mask; 47 static TCGv pm_base; 48 49 /* 50 * If an operation is being performed on less than TARGET_LONG_BITS, 51 * it may require the inputs to be sign- or zero-extended; which will 52 * depend on the exact operation being performed. 53 */ 54 typedef enum { 55 EXT_NONE, 56 EXT_SIGN, 57 EXT_ZERO, 58 } DisasExtend; 59 60 typedef struct DisasContext { 61 DisasContextBase base; 62 target_ulong cur_insn_len; 63 target_ulong pc_save; 64 target_ulong priv_ver; 65 RISCVMXL misa_mxl_max; 66 RISCVMXL xl; 67 RISCVMXL address_xl; 68 uint32_t misa_ext; 69 uint32_t opcode; 70 RISCVExtStatus mstatus_fs; 71 RISCVExtStatus mstatus_vs; 72 uint32_t mem_idx; 73 uint32_t priv; 74 /* 75 * Remember the rounding mode encoded in the previous fp instruction, 76 * which we have already installed into env->fp_status. Or -1 for 77 * no previous fp instruction. Note that we exit the TB when writing 78 * to any system register, which includes CSR_FRM, so we do not have 79 * to reset this known value. 80 */ 81 int frm; 82 RISCVMXL ol; 83 bool virt_inst_excp; 84 bool virt_enabled; 85 const RISCVCPUConfig *cfg_ptr; 86 /* vector extension */ 87 bool vill; 88 /* 89 * Encode LMUL to lmul as follows: 90 * LMUL vlmul lmul 91 * 1 000 0 92 * 2 001 1 93 * 4 010 2 94 * 8 011 3 95 * - 100 - 96 * 1/8 101 -3 97 * 1/4 110 -2 98 * 1/2 111 -1 99 */ 100 int8_t lmul; 101 uint8_t sew; 102 uint8_t vta; 103 uint8_t vma; 104 bool cfg_vta_all_1s; 105 bool vstart_eq_zero; 106 bool vl_eq_vlmax; 107 CPUState *cs; 108 TCGv zero; 109 /* PointerMasking extension */ 110 bool pm_mask_enabled; 111 bool pm_base_enabled; 112 /* Use icount trigger for native debug */ 113 bool itrigger; 114 /* FRM is known to contain a valid value. */ 115 bool frm_valid; 116 /* TCG of the current insn_start */ 117 TCGOp *insn_start; 118 } DisasContext; 119 120 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 121 { 122 return ctx->misa_ext & ext; 123 } 124 125 #ifdef TARGET_RISCV32 126 #define get_xl(ctx) MXL_RV32 127 #elif defined(CONFIG_USER_ONLY) 128 #define get_xl(ctx) MXL_RV64 129 #else 130 #define get_xl(ctx) ((ctx)->xl) 131 #endif 132 133 #ifdef TARGET_RISCV32 134 #define get_address_xl(ctx) MXL_RV32 135 #elif defined(CONFIG_USER_ONLY) 136 #define get_address_xl(ctx) MXL_RV64 137 #else 138 #define get_address_xl(ctx) ((ctx)->address_xl) 139 #endif 140 141 /* The word size for this machine mode. */ 142 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 143 { 144 return 16 << get_xl(ctx); 145 } 146 147 /* The operation length, as opposed to the xlen. */ 148 #ifdef TARGET_RISCV32 149 #define get_ol(ctx) MXL_RV32 150 #else 151 #define get_ol(ctx) ((ctx)->ol) 152 #endif 153 154 static inline int get_olen(DisasContext *ctx) 155 { 156 return 16 << get_ol(ctx); 157 } 158 159 /* The maximum register length */ 160 #ifdef TARGET_RISCV32 161 #define get_xl_max(ctx) MXL_RV32 162 #else 163 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 164 #endif 165 166 /* 167 * RISC-V requires NaN-boxing of narrower width floating point values. 168 * This applies when a 32-bit value is assigned to a 64-bit FP register. 169 * For consistency and simplicity, we nanbox results even when the RVD 170 * extension is not present. 171 */ 172 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 173 { 174 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 175 } 176 177 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 178 { 179 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 180 } 181 182 /* 183 * A narrow n-bit operation, where n < FLEN, checks that input operands 184 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 185 * If so, the least-significant bits of the input are used, otherwise the 186 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 187 * 188 * Here, the result is always nan-boxed, even the canonical nan. 189 */ 190 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 191 { 192 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 193 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 194 195 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 196 } 197 198 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 199 { 200 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 201 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 202 203 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 204 } 205 206 static void decode_save_opc(DisasContext *ctx) 207 { 208 assert(ctx->insn_start != NULL); 209 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 210 ctx->insn_start = NULL; 211 } 212 213 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, 214 target_long diff) 215 { 216 target_ulong dest = ctx->base.pc_next + diff; 217 218 assert(ctx->pc_save != -1); 219 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 220 tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save); 221 if (get_xl(ctx) == MXL_RV32) { 222 tcg_gen_ext32s_tl(target, target); 223 } 224 } else { 225 if (get_xl(ctx) == MXL_RV32) { 226 dest = (int32_t)dest; 227 } 228 tcg_gen_movi_tl(target, dest); 229 } 230 } 231 232 static void gen_update_pc(DisasContext *ctx, target_long diff) 233 { 234 gen_pc_plus_diff(cpu_pc, ctx, diff); 235 ctx->pc_save = ctx->base.pc_next + diff; 236 } 237 238 static void generate_exception(DisasContext *ctx, int excp) 239 { 240 gen_update_pc(ctx, 0); 241 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); 242 ctx->base.is_jmp = DISAS_NORETURN; 243 } 244 245 static void gen_exception_illegal(DisasContext *ctx) 246 { 247 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env, 248 offsetof(CPURISCVState, bins)); 249 if (ctx->virt_inst_excp) { 250 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 251 } else { 252 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 253 } 254 } 255 256 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) 257 { 258 tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); 259 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 260 } 261 262 static void lookup_and_goto_ptr(DisasContext *ctx) 263 { 264 #ifndef CONFIG_USER_ONLY 265 if (ctx->itrigger) { 266 gen_helper_itrigger_match(tcg_env); 267 } 268 #endif 269 tcg_gen_lookup_and_goto_ptr(); 270 } 271 272 static void exit_tb(DisasContext *ctx) 273 { 274 #ifndef CONFIG_USER_ONLY 275 if (ctx->itrigger) { 276 gen_helper_itrigger_match(tcg_env); 277 } 278 #endif 279 tcg_gen_exit_tb(NULL, 0); 280 } 281 282 static void gen_goto_tb(DisasContext *ctx, int n, target_long diff) 283 { 284 target_ulong dest = ctx->base.pc_next + diff; 285 286 /* 287 * Under itrigger, instruction executes one by one like singlestep, 288 * direct block chain benefits will be small. 289 */ 290 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 291 /* 292 * For pcrel, the pc must always be up-to-date on entry to 293 * the linked TB, so that it can use simple additions for all 294 * further adjustments. For !pcrel, the linked TB is compiled 295 * to know its full virtual address, so we can delay the 296 * update to pc to the unlinked path. A long chain of links 297 * can thus avoid many updates to the PC. 298 */ 299 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 300 gen_update_pc(ctx, diff); 301 tcg_gen_goto_tb(n); 302 } else { 303 tcg_gen_goto_tb(n); 304 gen_update_pc(ctx, diff); 305 } 306 tcg_gen_exit_tb(ctx->base.tb, n); 307 } else { 308 gen_update_pc(ctx, diff); 309 lookup_and_goto_ptr(ctx); 310 } 311 } 312 313 /* 314 * Wrappers for getting reg values. 315 * 316 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 317 * constant zero as a source, and an uninitialized sink as destination. 318 * 319 * Further, we may provide an extension for word operations. 320 */ 321 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 322 { 323 TCGv t; 324 325 if (reg_num == 0) { 326 return ctx->zero; 327 } 328 329 switch (get_ol(ctx)) { 330 case MXL_RV32: 331 switch (ext) { 332 case EXT_NONE: 333 break; 334 case EXT_SIGN: 335 t = tcg_temp_new(); 336 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 337 return t; 338 case EXT_ZERO: 339 t = tcg_temp_new(); 340 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 341 return t; 342 default: 343 g_assert_not_reached(); 344 } 345 break; 346 case MXL_RV64: 347 case MXL_RV128: 348 break; 349 default: 350 g_assert_not_reached(); 351 } 352 return cpu_gpr[reg_num]; 353 } 354 355 static TCGv get_gprh(DisasContext *ctx, int reg_num) 356 { 357 assert(get_xl(ctx) == MXL_RV128); 358 if (reg_num == 0) { 359 return ctx->zero; 360 } 361 return cpu_gprh[reg_num]; 362 } 363 364 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 365 { 366 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 367 return tcg_temp_new(); 368 } 369 return cpu_gpr[reg_num]; 370 } 371 372 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 373 { 374 if (reg_num == 0) { 375 return tcg_temp_new(); 376 } 377 return cpu_gprh[reg_num]; 378 } 379 380 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 381 { 382 if (reg_num != 0) { 383 switch (get_ol(ctx)) { 384 case MXL_RV32: 385 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 386 break; 387 case MXL_RV64: 388 case MXL_RV128: 389 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 390 break; 391 default: 392 g_assert_not_reached(); 393 } 394 395 if (get_xl_max(ctx) == MXL_RV128) { 396 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 397 } 398 } 399 } 400 401 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 402 { 403 if (reg_num != 0) { 404 switch (get_ol(ctx)) { 405 case MXL_RV32: 406 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 407 break; 408 case MXL_RV64: 409 case MXL_RV128: 410 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 411 break; 412 default: 413 g_assert_not_reached(); 414 } 415 416 if (get_xl_max(ctx) == MXL_RV128) { 417 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 418 } 419 } 420 } 421 422 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 423 { 424 assert(get_ol(ctx) == MXL_RV128); 425 if (reg_num != 0) { 426 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 427 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 428 } 429 } 430 431 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 432 { 433 if (!ctx->cfg_ptr->ext_zfinx) { 434 return cpu_fpr[reg_num]; 435 } 436 437 if (reg_num == 0) { 438 return tcg_constant_i64(0); 439 } 440 switch (get_xl(ctx)) { 441 case MXL_RV32: 442 #ifdef TARGET_RISCV32 443 { 444 TCGv_i64 t = tcg_temp_new_i64(); 445 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 446 return t; 447 } 448 #else 449 /* fall through */ 450 case MXL_RV64: 451 return cpu_gpr[reg_num]; 452 #endif 453 default: 454 g_assert_not_reached(); 455 } 456 } 457 458 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 459 { 460 if (!ctx->cfg_ptr->ext_zfinx) { 461 return cpu_fpr[reg_num]; 462 } 463 464 if (reg_num == 0) { 465 return tcg_constant_i64(0); 466 } 467 switch (get_xl(ctx)) { 468 case MXL_RV32: 469 { 470 TCGv_i64 t = tcg_temp_new_i64(); 471 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 472 return t; 473 } 474 #ifdef TARGET_RISCV64 475 case MXL_RV64: 476 return cpu_gpr[reg_num]; 477 #endif 478 default: 479 g_assert_not_reached(); 480 } 481 } 482 483 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 484 { 485 if (!ctx->cfg_ptr->ext_zfinx) { 486 return cpu_fpr[reg_num]; 487 } 488 489 if (reg_num == 0) { 490 return tcg_temp_new_i64(); 491 } 492 493 switch (get_xl(ctx)) { 494 case MXL_RV32: 495 return tcg_temp_new_i64(); 496 #ifdef TARGET_RISCV64 497 case MXL_RV64: 498 return cpu_gpr[reg_num]; 499 #endif 500 default: 501 g_assert_not_reached(); 502 } 503 } 504 505 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 506 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 507 { 508 if (!ctx->cfg_ptr->ext_zfinx) { 509 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 510 return; 511 } 512 if (reg_num != 0) { 513 switch (get_xl(ctx)) { 514 case MXL_RV32: 515 #ifdef TARGET_RISCV32 516 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 517 break; 518 #else 519 /* fall through */ 520 case MXL_RV64: 521 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 522 break; 523 #endif 524 default: 525 g_assert_not_reached(); 526 } 527 } 528 } 529 530 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 531 { 532 if (!ctx->cfg_ptr->ext_zfinx) { 533 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 534 return; 535 } 536 537 if (reg_num != 0) { 538 switch (get_xl(ctx)) { 539 case MXL_RV32: 540 #ifdef TARGET_RISCV32 541 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 542 break; 543 #else 544 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 545 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 546 break; 547 case MXL_RV64: 548 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 549 break; 550 #endif 551 default: 552 g_assert_not_reached(); 553 } 554 } 555 } 556 557 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 558 { 559 TCGv succ_pc = dest_gpr(ctx, rd); 560 561 /* check misaligned: */ 562 if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { 563 if ((imm & 0x3) != 0) { 564 TCGv target_pc = tcg_temp_new(); 565 gen_pc_plus_diff(target_pc, ctx, imm); 566 gen_exception_inst_addr_mis(ctx, target_pc); 567 return; 568 } 569 } 570 571 gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); 572 gen_set_gpr(ctx, rd, succ_pc); 573 574 gen_goto_tb(ctx, 0, imm); /* must use this for safety */ 575 ctx->base.is_jmp = DISAS_NORETURN; 576 } 577 578 /* Compute a canonical address from a register plus offset. */ 579 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 580 { 581 TCGv addr = tcg_temp_new(); 582 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 583 584 tcg_gen_addi_tl(addr, src1, imm); 585 if (ctx->pm_mask_enabled) { 586 tcg_gen_andc_tl(addr, addr, pm_mask); 587 } else if (get_address_xl(ctx) == MXL_RV32) { 588 tcg_gen_ext32u_tl(addr, addr); 589 } 590 if (ctx->pm_base_enabled) { 591 tcg_gen_or_tl(addr, addr, pm_base); 592 } 593 594 return addr; 595 } 596 597 /* Compute a canonical address from a register plus reg offset. */ 598 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 599 { 600 TCGv addr = tcg_temp_new(); 601 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 602 603 tcg_gen_add_tl(addr, src1, offs); 604 if (ctx->pm_mask_enabled) { 605 tcg_gen_andc_tl(addr, addr, pm_mask); 606 } else if (get_xl(ctx) == MXL_RV32) { 607 tcg_gen_ext32u_tl(addr, addr); 608 } 609 if (ctx->pm_base_enabled) { 610 tcg_gen_or_tl(addr, addr, pm_base); 611 } 612 return addr; 613 } 614 615 #ifndef CONFIG_USER_ONLY 616 /* 617 * We will have already diagnosed disabled state, 618 * and need to turn initial/clean into dirty. 619 */ 620 static void mark_fs_dirty(DisasContext *ctx) 621 { 622 TCGv tmp; 623 624 if (!has_ext(ctx, RVF)) { 625 return; 626 } 627 628 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 629 /* Remember the state change for the rest of the TB. */ 630 ctx->mstatus_fs = EXT_STATUS_DIRTY; 631 632 tmp = tcg_temp_new(); 633 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 634 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 635 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 636 637 if (ctx->virt_enabled) { 638 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 639 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 640 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 641 } 642 } 643 } 644 #else 645 static inline void mark_fs_dirty(DisasContext *ctx) { } 646 #endif 647 648 #ifndef CONFIG_USER_ONLY 649 /* 650 * We will have already diagnosed disabled state, 651 * and need to turn initial/clean into dirty. 652 */ 653 static void mark_vs_dirty(DisasContext *ctx) 654 { 655 TCGv tmp; 656 657 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 658 /* Remember the state change for the rest of the TB. */ 659 ctx->mstatus_vs = EXT_STATUS_DIRTY; 660 661 tmp = tcg_temp_new(); 662 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 663 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 664 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 665 666 if (ctx->virt_enabled) { 667 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 668 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 669 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 670 } 671 } 672 } 673 #else 674 static inline void mark_vs_dirty(DisasContext *ctx) { } 675 #endif 676 677 static void gen_set_rm(DisasContext *ctx, int rm) 678 { 679 if (ctx->frm == rm) { 680 return; 681 } 682 ctx->frm = rm; 683 684 if (rm == RISCV_FRM_DYN) { 685 /* The helper will return only if frm valid. */ 686 ctx->frm_valid = true; 687 } 688 689 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 690 decode_save_opc(ctx); 691 gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm)); 692 } 693 694 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 695 { 696 if (ctx->frm == rm && ctx->frm_valid) { 697 return; 698 } 699 ctx->frm = rm; 700 ctx->frm_valid = true; 701 702 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 703 decode_save_opc(ctx); 704 gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm)); 705 } 706 707 static int ex_plus_1(DisasContext *ctx, int nf) 708 { 709 return nf + 1; 710 } 711 712 #define EX_SH(amount) \ 713 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 714 { \ 715 return imm << amount; \ 716 } 717 EX_SH(1) 718 EX_SH(2) 719 EX_SH(3) 720 EX_SH(4) 721 EX_SH(12) 722 723 #define REQUIRE_EXT(ctx, ext) do { \ 724 if (!has_ext(ctx, ext)) { \ 725 return false; \ 726 } \ 727 } while (0) 728 729 #define REQUIRE_32BIT(ctx) do { \ 730 if (get_xl(ctx) != MXL_RV32) { \ 731 return false; \ 732 } \ 733 } while (0) 734 735 #define REQUIRE_64BIT(ctx) do { \ 736 if (get_xl(ctx) != MXL_RV64) { \ 737 return false; \ 738 } \ 739 } while (0) 740 741 #define REQUIRE_128BIT(ctx) do { \ 742 if (get_xl(ctx) != MXL_RV128) { \ 743 return false; \ 744 } \ 745 } while (0) 746 747 #define REQUIRE_64_OR_128BIT(ctx) do { \ 748 if (get_xl(ctx) == MXL_RV32) { \ 749 return false; \ 750 } \ 751 } while (0) 752 753 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 754 if (!ctx->cfg_ptr->ext_##A && \ 755 !ctx->cfg_ptr->ext_##B) { \ 756 return false; \ 757 } \ 758 } while (0) 759 760 static int ex_rvc_register(DisasContext *ctx, int reg) 761 { 762 return 8 + reg; 763 } 764 765 static int ex_sreg_register(DisasContext *ctx, int reg) 766 { 767 return reg < 2 ? reg + 8 : reg + 16; 768 } 769 770 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 771 { 772 /* For RV128 a shamt of 0 means a shift by 64. */ 773 if (get_ol(ctx) == MXL_RV128) { 774 imm = imm ? imm : 64; 775 } 776 return imm; 777 } 778 779 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 780 { 781 /* 782 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 783 * shifts, the shamt is sign-extended. 784 */ 785 if (get_ol(ctx) == MXL_RV128) { 786 imm = imm | (imm & 32) << 1; 787 imm = imm ? imm : 64; 788 } 789 return imm; 790 } 791 792 /* Include the auto-generated decoder for 32 bit insn */ 793 #include "decode-insn32.c.inc" 794 795 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 796 void (*func)(TCGv, TCGv, target_long)) 797 { 798 TCGv dest = dest_gpr(ctx, a->rd); 799 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 800 801 func(dest, src1, a->imm); 802 803 if (get_xl(ctx) == MXL_RV128) { 804 TCGv src1h = get_gprh(ctx, a->rs1); 805 TCGv desth = dest_gprh(ctx, a->rd); 806 807 func(desth, src1h, -(a->imm < 0)); 808 gen_set_gpr128(ctx, a->rd, dest, desth); 809 } else { 810 gen_set_gpr(ctx, a->rd, dest); 811 } 812 813 return true; 814 } 815 816 static bool gen_logic(DisasContext *ctx, arg_r *a, 817 void (*func)(TCGv, TCGv, TCGv)) 818 { 819 TCGv dest = dest_gpr(ctx, a->rd); 820 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 821 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 822 823 func(dest, src1, src2); 824 825 if (get_xl(ctx) == MXL_RV128) { 826 TCGv src1h = get_gprh(ctx, a->rs1); 827 TCGv src2h = get_gprh(ctx, a->rs2); 828 TCGv desth = dest_gprh(ctx, a->rd); 829 830 func(desth, src1h, src2h); 831 gen_set_gpr128(ctx, a->rd, dest, desth); 832 } else { 833 gen_set_gpr(ctx, a->rd, dest); 834 } 835 836 return true; 837 } 838 839 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 840 void (*func)(TCGv, TCGv, target_long), 841 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 842 { 843 TCGv dest = dest_gpr(ctx, a->rd); 844 TCGv src1 = get_gpr(ctx, a->rs1, ext); 845 846 if (get_ol(ctx) < MXL_RV128) { 847 func(dest, src1, a->imm); 848 gen_set_gpr(ctx, a->rd, dest); 849 } else { 850 if (f128 == NULL) { 851 return false; 852 } 853 854 TCGv src1h = get_gprh(ctx, a->rs1); 855 TCGv desth = dest_gprh(ctx, a->rd); 856 857 f128(dest, desth, src1, src1h, a->imm); 858 gen_set_gpr128(ctx, a->rd, dest, desth); 859 } 860 return true; 861 } 862 863 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 864 void (*func)(TCGv, TCGv, TCGv), 865 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 866 { 867 TCGv dest = dest_gpr(ctx, a->rd); 868 TCGv src1 = get_gpr(ctx, a->rs1, ext); 869 TCGv src2 = tcg_constant_tl(a->imm); 870 871 if (get_ol(ctx) < MXL_RV128) { 872 func(dest, src1, src2); 873 gen_set_gpr(ctx, a->rd, dest); 874 } else { 875 if (f128 == NULL) { 876 return false; 877 } 878 879 TCGv src1h = get_gprh(ctx, a->rs1); 880 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 881 TCGv desth = dest_gprh(ctx, a->rd); 882 883 f128(dest, desth, src1, src1h, src2, src2h); 884 gen_set_gpr128(ctx, a->rd, dest, desth); 885 } 886 return true; 887 } 888 889 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 890 void (*func)(TCGv, TCGv, TCGv), 891 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 892 { 893 TCGv dest = dest_gpr(ctx, a->rd); 894 TCGv src1 = get_gpr(ctx, a->rs1, ext); 895 TCGv src2 = get_gpr(ctx, a->rs2, ext); 896 897 if (get_ol(ctx) < MXL_RV128) { 898 func(dest, src1, src2); 899 gen_set_gpr(ctx, a->rd, dest); 900 } else { 901 if (f128 == NULL) { 902 return false; 903 } 904 905 TCGv src1h = get_gprh(ctx, a->rs1); 906 TCGv src2h = get_gprh(ctx, a->rs2); 907 TCGv desth = dest_gprh(ctx, a->rd); 908 909 f128(dest, desth, src1, src1h, src2, src2h); 910 gen_set_gpr128(ctx, a->rd, dest, desth); 911 } 912 return true; 913 } 914 915 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 916 void (*f_tl)(TCGv, TCGv, TCGv), 917 void (*f_32)(TCGv, TCGv, TCGv), 918 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 919 { 920 int olen = get_olen(ctx); 921 922 if (olen != TARGET_LONG_BITS) { 923 if (olen == 32) { 924 f_tl = f_32; 925 } else if (olen != 128) { 926 g_assert_not_reached(); 927 } 928 } 929 return gen_arith(ctx, a, ext, f_tl, f_128); 930 } 931 932 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 933 void (*func)(TCGv, TCGv, target_long), 934 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 935 { 936 TCGv dest, src1; 937 int max_len = get_olen(ctx); 938 939 if (a->shamt >= max_len) { 940 return false; 941 } 942 943 dest = dest_gpr(ctx, a->rd); 944 src1 = get_gpr(ctx, a->rs1, ext); 945 946 if (max_len < 128) { 947 func(dest, src1, a->shamt); 948 gen_set_gpr(ctx, a->rd, dest); 949 } else { 950 TCGv src1h = get_gprh(ctx, a->rs1); 951 TCGv desth = dest_gprh(ctx, a->rd); 952 953 if (f128 == NULL) { 954 return false; 955 } 956 f128(dest, desth, src1, src1h, a->shamt); 957 gen_set_gpr128(ctx, a->rd, dest, desth); 958 } 959 return true; 960 } 961 962 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 963 DisasExtend ext, 964 void (*f_tl)(TCGv, TCGv, target_long), 965 void (*f_32)(TCGv, TCGv, target_long), 966 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 967 target_long)) 968 { 969 int olen = get_olen(ctx); 970 if (olen != TARGET_LONG_BITS) { 971 if (olen == 32) { 972 f_tl = f_32; 973 } else if (olen != 128) { 974 g_assert_not_reached(); 975 } 976 } 977 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 978 } 979 980 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 981 void (*func)(TCGv, TCGv, TCGv)) 982 { 983 TCGv dest, src1, src2; 984 int max_len = get_olen(ctx); 985 986 if (a->shamt >= max_len) { 987 return false; 988 } 989 990 dest = dest_gpr(ctx, a->rd); 991 src1 = get_gpr(ctx, a->rs1, ext); 992 src2 = tcg_constant_tl(a->shamt); 993 994 func(dest, src1, src2); 995 996 gen_set_gpr(ctx, a->rd, dest); 997 return true; 998 } 999 1000 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 1001 void (*func)(TCGv, TCGv, TCGv), 1002 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1003 { 1004 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1005 TCGv ext2 = tcg_temp_new(); 1006 int max_len = get_olen(ctx); 1007 1008 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1009 1010 TCGv dest = dest_gpr(ctx, a->rd); 1011 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1012 1013 if (max_len < 128) { 1014 func(dest, src1, ext2); 1015 gen_set_gpr(ctx, a->rd, dest); 1016 } else { 1017 TCGv src1h = get_gprh(ctx, a->rs1); 1018 TCGv desth = dest_gprh(ctx, a->rd); 1019 1020 if (f128 == NULL) { 1021 return false; 1022 } 1023 f128(dest, desth, src1, src1h, ext2); 1024 gen_set_gpr128(ctx, a->rd, dest, desth); 1025 } 1026 return true; 1027 } 1028 1029 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1030 void (*f_tl)(TCGv, TCGv, TCGv), 1031 void (*f_32)(TCGv, TCGv, TCGv), 1032 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1033 { 1034 int olen = get_olen(ctx); 1035 if (olen != TARGET_LONG_BITS) { 1036 if (olen == 32) { 1037 f_tl = f_32; 1038 } else if (olen != 128) { 1039 g_assert_not_reached(); 1040 } 1041 } 1042 return gen_shift(ctx, a, ext, f_tl, f_128); 1043 } 1044 1045 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1046 void (*func)(TCGv, TCGv)) 1047 { 1048 TCGv dest = dest_gpr(ctx, a->rd); 1049 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1050 1051 func(dest, src1); 1052 1053 gen_set_gpr(ctx, a->rd, dest); 1054 return true; 1055 } 1056 1057 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1058 void (*f_tl)(TCGv, TCGv), 1059 void (*f_32)(TCGv, TCGv)) 1060 { 1061 int olen = get_olen(ctx); 1062 1063 if (olen != TARGET_LONG_BITS) { 1064 if (olen == 32) { 1065 f_tl = f_32; 1066 } else { 1067 g_assert_not_reached(); 1068 } 1069 } 1070 return gen_unary(ctx, a, ext, f_tl); 1071 } 1072 1073 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1074 { 1075 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1076 CPUState *cpu = ctx->cs; 1077 CPURISCVState *env = cpu_env(cpu); 1078 1079 return cpu_ldl_code(env, pc); 1080 } 1081 1082 /* Include insn module translation function */ 1083 #include "insn_trans/trans_rvi.c.inc" 1084 #include "insn_trans/trans_rvm.c.inc" 1085 #include "insn_trans/trans_rva.c.inc" 1086 #include "insn_trans/trans_rvf.c.inc" 1087 #include "insn_trans/trans_rvd.c.inc" 1088 #include "insn_trans/trans_rvh.c.inc" 1089 #include "insn_trans/trans_rvv.c.inc" 1090 #include "insn_trans/trans_rvb.c.inc" 1091 #include "insn_trans/trans_rvzicond.c.inc" 1092 #include "insn_trans/trans_rvzacas.c.inc" 1093 #include "insn_trans/trans_rvzawrs.c.inc" 1094 #include "insn_trans/trans_rvzicbo.c.inc" 1095 #include "insn_trans/trans_rvzfa.c.inc" 1096 #include "insn_trans/trans_rvzfh.c.inc" 1097 #include "insn_trans/trans_rvk.c.inc" 1098 #include "insn_trans/trans_rvvk.c.inc" 1099 #include "insn_trans/trans_privileged.c.inc" 1100 #include "insn_trans/trans_svinval.c.inc" 1101 #include "insn_trans/trans_rvbf16.c.inc" 1102 #include "decode-xthead.c.inc" 1103 #include "insn_trans/trans_xthead.c.inc" 1104 #include "insn_trans/trans_xventanacondops.c.inc" 1105 1106 /* Include the auto-generated decoder for 16 bit insn */ 1107 #include "decode-insn16.c.inc" 1108 #include "insn_trans/trans_rvzce.c.inc" 1109 1110 /* Include decoders for factored-out extensions */ 1111 #include "decode-XVentanaCondOps.c.inc" 1112 1113 /* The specification allows for longer insns, but not supported by qemu. */ 1114 #define MAX_INSN_LEN 4 1115 1116 static inline int insn_len(uint16_t first_word) 1117 { 1118 return (first_word & 3) == 3 ? 4 : 2; 1119 } 1120 1121 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1122 { 1123 /* 1124 * A table with predicate (i.e., guard) functions and decoder functions 1125 * that are tested in-order until a decoder matches onto the opcode. 1126 */ 1127 static const struct { 1128 bool (*guard_func)(const RISCVCPUConfig *); 1129 bool (*decode_func)(DisasContext *, uint32_t); 1130 } decoders[] = { 1131 { always_true_p, decode_insn32 }, 1132 { has_xthead_p, decode_xthead }, 1133 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1134 }; 1135 1136 ctx->virt_inst_excp = false; 1137 ctx->cur_insn_len = insn_len(opcode); 1138 /* Check for compressed insn */ 1139 if (ctx->cur_insn_len == 2) { 1140 ctx->opcode = opcode; 1141 /* 1142 * The Zca extension is added as way to refer to instructions in the C 1143 * extension that do not include the floating-point loads and stores 1144 */ 1145 if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && 1146 decode_insn16(ctx, opcode)) { 1147 return; 1148 } 1149 } else { 1150 uint32_t opcode32 = opcode; 1151 opcode32 = deposit32(opcode32, 16, 16, 1152 translator_lduw(env, &ctx->base, 1153 ctx->base.pc_next + 2)); 1154 ctx->opcode = opcode32; 1155 1156 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1157 if (decoders[i].guard_func(ctx->cfg_ptr) && 1158 decoders[i].decode_func(ctx, opcode32)) { 1159 return; 1160 } 1161 } 1162 } 1163 1164 gen_exception_illegal(ctx); 1165 } 1166 1167 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1168 { 1169 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1170 CPURISCVState *env = cpu_env(cs); 1171 RISCVCPU *cpu = RISCV_CPU(cs); 1172 uint32_t tb_flags = ctx->base.tb->flags; 1173 1174 ctx->pc_save = ctx->base.pc_first; 1175 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1176 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1177 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1178 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1179 ctx->priv_ver = env->priv_ver; 1180 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1181 ctx->misa_ext = env->misa_ext; 1182 ctx->frm = -1; /* unknown rounding mode */ 1183 ctx->cfg_ptr = &(cpu->cfg); 1184 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1185 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1186 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1187 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1188 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1189 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1190 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1191 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1192 ctx->misa_mxl_max = env->misa_mxl_max; 1193 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1194 ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); 1195 ctx->cs = cs; 1196 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1197 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1198 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1199 ctx->zero = tcg_constant_tl(0); 1200 ctx->virt_inst_excp = false; 1201 } 1202 1203 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1204 { 1205 } 1206 1207 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1208 { 1209 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1210 target_ulong pc_next = ctx->base.pc_next; 1211 1212 if (tb_cflags(dcbase->tb) & CF_PCREL) { 1213 pc_next &= ~TARGET_PAGE_MASK; 1214 } 1215 1216 tcg_gen_insn_start(pc_next, 0); 1217 ctx->insn_start = tcg_last_op(); 1218 } 1219 1220 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1221 { 1222 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1223 CPURISCVState *env = cpu_env(cpu); 1224 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1225 1226 ctx->ol = ctx->xl; 1227 decode_opc(env, ctx, opcode16); 1228 ctx->base.pc_next += ctx->cur_insn_len; 1229 1230 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1231 if (ctx->base.is_jmp == DISAS_NEXT) { 1232 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1233 ctx->base.is_jmp = DISAS_TOO_MANY; 1234 } else { 1235 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1236 1237 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1238 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1239 int len = insn_len(next_insn); 1240 1241 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1242 ctx->base.is_jmp = DISAS_TOO_MANY; 1243 } 1244 } 1245 } 1246 } 1247 } 1248 1249 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1250 { 1251 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1252 1253 switch (ctx->base.is_jmp) { 1254 case DISAS_TOO_MANY: 1255 gen_goto_tb(ctx, 0, 0); 1256 break; 1257 case DISAS_NORETURN: 1258 break; 1259 default: 1260 g_assert_not_reached(); 1261 } 1262 } 1263 1264 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1265 CPUState *cpu, FILE *logfile) 1266 { 1267 #ifndef CONFIG_USER_ONLY 1268 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1269 CPURISCVState *env = &rvcpu->env; 1270 #endif 1271 1272 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1273 #ifndef CONFIG_USER_ONLY 1274 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n", 1275 env->priv, env->virt_enabled); 1276 #endif 1277 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1278 } 1279 1280 static const TranslatorOps riscv_tr_ops = { 1281 .init_disas_context = riscv_tr_init_disas_context, 1282 .tb_start = riscv_tr_tb_start, 1283 .insn_start = riscv_tr_insn_start, 1284 .translate_insn = riscv_tr_translate_insn, 1285 .tb_stop = riscv_tr_tb_stop, 1286 .disas_log = riscv_tr_disas_log, 1287 }; 1288 1289 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1290 vaddr pc, void *host_pc) 1291 { 1292 DisasContext ctx; 1293 1294 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1295 } 1296 1297 void riscv_translate_init(void) 1298 { 1299 int i; 1300 1301 /* 1302 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1303 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1304 * unless you specifically block reads/writes to reg 0. 1305 */ 1306 cpu_gpr[0] = NULL; 1307 cpu_gprh[0] = NULL; 1308 1309 for (i = 1; i < 32; i++) { 1310 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 1311 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1312 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 1313 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1314 } 1315 1316 for (i = 0; i < 32; i++) { 1317 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env, 1318 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1319 } 1320 1321 cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc"); 1322 cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl"); 1323 cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart), 1324 "vstart"); 1325 load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res), 1326 "load_res"); 1327 load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val), 1328 "load_val"); 1329 /* Assign PM CSRs to tcg globals */ 1330 pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask), 1331 "pmmask"); 1332 pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase), 1333 "pmbase"); 1334 } 1335