1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 34 /* global register indices */ 35 static TCGv cpu_gpr[32], cpu_pc, cpu_vl; 36 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 37 static TCGv load_res; 38 static TCGv load_val; 39 40 #include "exec/gen-icount.h" 41 42 typedef struct DisasContext { 43 DisasContextBase base; 44 /* pc_succ_insn points to the instruction following base.pc_next */ 45 target_ulong pc_succ_insn; 46 target_ulong priv_ver; 47 bool virt_enabled; 48 uint32_t opcode; 49 uint32_t mstatus_fs; 50 uint32_t misa; 51 uint32_t mem_idx; 52 /* Remember the rounding mode encoded in the previous fp instruction, 53 which we have already installed into env->fp_status. Or -1 for 54 no previous fp instruction. Note that we exit the TB when writing 55 to any system register, which includes CSR_FRM, so we do not have 56 to reset this known value. */ 57 int frm; 58 bool ext_ifencei; 59 /* vector extension */ 60 bool vill; 61 uint8_t lmul; 62 uint8_t sew; 63 uint16_t vlen; 64 bool vl_eq_vlmax; 65 } DisasContext; 66 67 #ifdef TARGET_RISCV64 68 /* convert riscv funct3 to qemu memop for load/store */ 69 static const int tcg_memop_lookup[8] = { 70 [0 ... 7] = -1, 71 [0] = MO_SB, 72 [1] = MO_TESW, 73 [2] = MO_TESL, 74 [3] = MO_TEQ, 75 [4] = MO_UB, 76 [5] = MO_TEUW, 77 [6] = MO_TEUL, 78 }; 79 #endif 80 81 #ifdef TARGET_RISCV64 82 #define CASE_OP_32_64(X) case X: case glue(X, W) 83 #else 84 #define CASE_OP_32_64(X) case X 85 #endif 86 87 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 88 { 89 return ctx->misa & ext; 90 } 91 92 static void generate_exception(DisasContext *ctx, int excp) 93 { 94 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 95 TCGv_i32 helper_tmp = tcg_const_i32(excp); 96 gen_helper_raise_exception(cpu_env, helper_tmp); 97 tcg_temp_free_i32(helper_tmp); 98 ctx->base.is_jmp = DISAS_NORETURN; 99 } 100 101 static void generate_exception_mbadaddr(DisasContext *ctx, int excp) 102 { 103 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 104 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 105 TCGv_i32 helper_tmp = tcg_const_i32(excp); 106 gen_helper_raise_exception(cpu_env, helper_tmp); 107 tcg_temp_free_i32(helper_tmp); 108 ctx->base.is_jmp = DISAS_NORETURN; 109 } 110 111 static void gen_exception_debug(void) 112 { 113 TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG); 114 gen_helper_raise_exception(cpu_env, helper_tmp); 115 tcg_temp_free_i32(helper_tmp); 116 } 117 118 /* Wrapper around tcg_gen_exit_tb that handles single stepping */ 119 static void exit_tb(DisasContext *ctx) 120 { 121 if (ctx->base.singlestep_enabled) { 122 gen_exception_debug(); 123 } else { 124 tcg_gen_exit_tb(NULL, 0); 125 } 126 } 127 128 /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */ 129 static void lookup_and_goto_ptr(DisasContext *ctx) 130 { 131 if (ctx->base.singlestep_enabled) { 132 gen_exception_debug(); 133 } else { 134 tcg_gen_lookup_and_goto_ptr(); 135 } 136 } 137 138 static void gen_exception_illegal(DisasContext *ctx) 139 { 140 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 141 } 142 143 static void gen_exception_inst_addr_mis(DisasContext *ctx) 144 { 145 generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS); 146 } 147 148 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 149 { 150 if (unlikely(ctx->base.singlestep_enabled)) { 151 return false; 152 } 153 154 #ifndef CONFIG_USER_ONLY 155 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 156 #else 157 return true; 158 #endif 159 } 160 161 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 162 { 163 if (use_goto_tb(ctx, dest)) { 164 /* chaining is only allowed when the jump is to the same page */ 165 tcg_gen_goto_tb(n); 166 tcg_gen_movi_tl(cpu_pc, dest); 167 168 /* No need to check for single stepping here as use_goto_tb() will 169 * return false in case of single stepping. 170 */ 171 tcg_gen_exit_tb(ctx->base.tb, n); 172 } else { 173 tcg_gen_movi_tl(cpu_pc, dest); 174 lookup_and_goto_ptr(ctx); 175 } 176 } 177 178 /* Wrapper for getting reg values - need to check of reg is zero since 179 * cpu_gpr[0] is not actually allocated 180 */ 181 static inline void gen_get_gpr(TCGv t, int reg_num) 182 { 183 if (reg_num == 0) { 184 tcg_gen_movi_tl(t, 0); 185 } else { 186 tcg_gen_mov_tl(t, cpu_gpr[reg_num]); 187 } 188 } 189 190 /* Wrapper for setting reg values - need to check of reg is zero since 191 * cpu_gpr[0] is not actually allocated. this is more for safety purposes, 192 * since we usually avoid calling the OP_TYPE_gen function if we see a write to 193 * $zero 194 */ 195 static inline void gen_set_gpr(int reg_num_dst, TCGv t) 196 { 197 if (reg_num_dst != 0) { 198 tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); 199 } 200 } 201 202 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) 203 { 204 TCGv rl = tcg_temp_new(); 205 TCGv rh = tcg_temp_new(); 206 207 tcg_gen_mulu2_tl(rl, rh, arg1, arg2); 208 /* fix up for one negative */ 209 tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); 210 tcg_gen_and_tl(rl, rl, arg2); 211 tcg_gen_sub_tl(ret, rh, rl); 212 213 tcg_temp_free(rl); 214 tcg_temp_free(rh); 215 } 216 217 static void gen_div(TCGv ret, TCGv source1, TCGv source2) 218 { 219 TCGv cond1, cond2, zeroreg, resultopt1; 220 /* 221 * Handle by altering args to tcg_gen_div to produce req'd results: 222 * For overflow: want source1 in source1 and 1 in source2 223 * For div by zero: want -1 in source1 and 1 in source2 -> -1 result 224 */ 225 cond1 = tcg_temp_new(); 226 cond2 = tcg_temp_new(); 227 zeroreg = tcg_const_tl(0); 228 resultopt1 = tcg_temp_new(); 229 230 tcg_gen_movi_tl(resultopt1, (target_ulong)-1); 231 tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); 232 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, 233 ((target_ulong)1) << (TARGET_LONG_BITS - 1)); 234 tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ 235 tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ 236 /* if div by zero, set source1 to -1, otherwise don't change */ 237 tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, 238 resultopt1); 239 /* if overflow or div by zero, set source2 to 1, else don't change */ 240 tcg_gen_or_tl(cond1, cond1, cond2); 241 tcg_gen_movi_tl(resultopt1, (target_ulong)1); 242 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, 243 resultopt1); 244 tcg_gen_div_tl(ret, source1, source2); 245 246 tcg_temp_free(cond1); 247 tcg_temp_free(cond2); 248 tcg_temp_free(zeroreg); 249 tcg_temp_free(resultopt1); 250 } 251 252 static void gen_divu(TCGv ret, TCGv source1, TCGv source2) 253 { 254 TCGv cond1, zeroreg, resultopt1; 255 cond1 = tcg_temp_new(); 256 257 zeroreg = tcg_const_tl(0); 258 resultopt1 = tcg_temp_new(); 259 260 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); 261 tcg_gen_movi_tl(resultopt1, (target_ulong)-1); 262 tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, 263 resultopt1); 264 tcg_gen_movi_tl(resultopt1, (target_ulong)1); 265 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, 266 resultopt1); 267 tcg_gen_divu_tl(ret, source1, source2); 268 269 tcg_temp_free(cond1); 270 tcg_temp_free(zeroreg); 271 tcg_temp_free(resultopt1); 272 } 273 274 static void gen_rem(TCGv ret, TCGv source1, TCGv source2) 275 { 276 TCGv cond1, cond2, zeroreg, resultopt1; 277 278 cond1 = tcg_temp_new(); 279 cond2 = tcg_temp_new(); 280 zeroreg = tcg_const_tl(0); 281 resultopt1 = tcg_temp_new(); 282 283 tcg_gen_movi_tl(resultopt1, 1L); 284 tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); 285 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, 286 (target_ulong)1 << (TARGET_LONG_BITS - 1)); 287 tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ 288 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ 289 /* if overflow or div by zero, set source2 to 1, else don't change */ 290 tcg_gen_or_tl(cond2, cond1, cond2); 291 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, 292 resultopt1); 293 tcg_gen_rem_tl(resultopt1, source1, source2); 294 /* if div by zero, just return the original dividend */ 295 tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, 296 source1); 297 298 tcg_temp_free(cond1); 299 tcg_temp_free(cond2); 300 tcg_temp_free(zeroreg); 301 tcg_temp_free(resultopt1); 302 } 303 304 static void gen_remu(TCGv ret, TCGv source1, TCGv source2) 305 { 306 TCGv cond1, zeroreg, resultopt1; 307 cond1 = tcg_temp_new(); 308 zeroreg = tcg_const_tl(0); 309 resultopt1 = tcg_temp_new(); 310 311 tcg_gen_movi_tl(resultopt1, (target_ulong)1); 312 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); 313 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, 314 resultopt1); 315 tcg_gen_remu_tl(resultopt1, source1, source2); 316 /* if div by zero, just return the original dividend */ 317 tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, 318 source1); 319 320 tcg_temp_free(cond1); 321 tcg_temp_free(zeroreg); 322 tcg_temp_free(resultopt1); 323 } 324 325 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 326 { 327 target_ulong next_pc; 328 329 /* check misaligned: */ 330 next_pc = ctx->base.pc_next + imm; 331 if (!has_ext(ctx, RVC)) { 332 if ((next_pc & 0x3) != 0) { 333 gen_exception_inst_addr_mis(ctx); 334 return; 335 } 336 } 337 if (rd != 0) { 338 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 339 } 340 341 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 342 ctx->base.is_jmp = DISAS_NORETURN; 343 } 344 345 #ifdef TARGET_RISCV64 346 static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, 347 target_long imm) 348 { 349 TCGv t0 = tcg_temp_new(); 350 TCGv t1 = tcg_temp_new(); 351 gen_get_gpr(t0, rs1); 352 tcg_gen_addi_tl(t0, t0, imm); 353 int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; 354 355 if (memop < 0) { 356 gen_exception_illegal(ctx); 357 return; 358 } 359 360 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); 361 gen_set_gpr(rd, t1); 362 tcg_temp_free(t0); 363 tcg_temp_free(t1); 364 } 365 366 static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, 367 target_long imm) 368 { 369 TCGv t0 = tcg_temp_new(); 370 TCGv dat = tcg_temp_new(); 371 gen_get_gpr(t0, rs1); 372 tcg_gen_addi_tl(t0, t0, imm); 373 gen_get_gpr(dat, rs2); 374 int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; 375 376 if (memop < 0) { 377 gen_exception_illegal(ctx); 378 return; 379 } 380 381 tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); 382 tcg_temp_free(t0); 383 tcg_temp_free(dat); 384 } 385 #endif 386 387 #ifndef CONFIG_USER_ONLY 388 /* The states of mstatus_fs are: 389 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 390 * We will have already diagnosed disabled state, 391 * and need to turn initial/clean into dirty. 392 */ 393 static void mark_fs_dirty(DisasContext *ctx) 394 { 395 TCGv tmp; 396 if (ctx->mstatus_fs == MSTATUS_FS) { 397 return; 398 } 399 /* Remember the state change for the rest of the TB. */ 400 ctx->mstatus_fs = MSTATUS_FS; 401 402 tmp = tcg_temp_new(); 403 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 404 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); 405 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 406 407 if (ctx->virt_enabled) { 408 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 409 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); 410 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 411 } 412 tcg_temp_free(tmp); 413 } 414 #else 415 static inline void mark_fs_dirty(DisasContext *ctx) { } 416 #endif 417 418 #if !defined(TARGET_RISCV64) 419 static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, 420 int rs1, target_long imm) 421 { 422 TCGv t0; 423 424 if (ctx->mstatus_fs == 0) { 425 gen_exception_illegal(ctx); 426 return; 427 } 428 429 t0 = tcg_temp_new(); 430 gen_get_gpr(t0, rs1); 431 tcg_gen_addi_tl(t0, t0, imm); 432 433 switch (opc) { 434 case OPC_RISC_FLW: 435 if (!has_ext(ctx, RVF)) { 436 goto do_illegal; 437 } 438 tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL); 439 /* RISC-V requires NaN-boxing of narrower width floating point values */ 440 tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL); 441 break; 442 case OPC_RISC_FLD: 443 if (!has_ext(ctx, RVD)) { 444 goto do_illegal; 445 } 446 tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ); 447 break; 448 do_illegal: 449 default: 450 gen_exception_illegal(ctx); 451 break; 452 } 453 tcg_temp_free(t0); 454 455 mark_fs_dirty(ctx); 456 } 457 458 static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, 459 int rs2, target_long imm) 460 { 461 TCGv t0; 462 463 if (ctx->mstatus_fs == 0) { 464 gen_exception_illegal(ctx); 465 return; 466 } 467 468 t0 = tcg_temp_new(); 469 gen_get_gpr(t0, rs1); 470 tcg_gen_addi_tl(t0, t0, imm); 471 472 switch (opc) { 473 case OPC_RISC_FSW: 474 if (!has_ext(ctx, RVF)) { 475 goto do_illegal; 476 } 477 tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL); 478 break; 479 case OPC_RISC_FSD: 480 if (!has_ext(ctx, RVD)) { 481 goto do_illegal; 482 } 483 tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ); 484 break; 485 do_illegal: 486 default: 487 gen_exception_illegal(ctx); 488 break; 489 } 490 491 tcg_temp_free(t0); 492 } 493 #endif 494 495 static void gen_set_rm(DisasContext *ctx, int rm) 496 { 497 TCGv_i32 t0; 498 499 if (ctx->frm == rm) { 500 return; 501 } 502 ctx->frm = rm; 503 t0 = tcg_const_i32(rm); 504 gen_helper_set_rounding_mode(cpu_env, t0); 505 tcg_temp_free_i32(t0); 506 } 507 508 static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode) 509 { 510 uint8_t funct3 = extract16(opcode, 13, 3); 511 uint8_t rd_rs2 = GET_C_RS2S(opcode); 512 uint8_t rs1s = GET_C_RS1S(opcode); 513 514 switch (funct3) { 515 case 3: 516 #if defined(TARGET_RISCV64) 517 /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ 518 gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, 519 GET_C_LD_IMM(opcode)); 520 #else 521 /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ 522 gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s, 523 GET_C_LW_IMM(opcode)); 524 #endif 525 break; 526 case 7: 527 #if defined(TARGET_RISCV64) 528 /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ 529 gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, 530 GET_C_LD_IMM(opcode)); 531 #else 532 /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ 533 gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2, 534 GET_C_LW_IMM(opcode)); 535 #endif 536 break; 537 } 538 } 539 540 static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode) 541 { 542 uint8_t op = extract16(opcode, 0, 2); 543 544 switch (op) { 545 case 0: 546 decode_RV32_64C0(ctx, opcode); 547 break; 548 } 549 } 550 551 #define EX_SH(amount) \ 552 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 553 { \ 554 return imm << amount; \ 555 } 556 EX_SH(1) 557 EX_SH(2) 558 EX_SH(3) 559 EX_SH(4) 560 EX_SH(12) 561 562 #define REQUIRE_EXT(ctx, ext) do { \ 563 if (!has_ext(ctx, ext)) { \ 564 return false; \ 565 } \ 566 } while (0) 567 568 static int ex_rvc_register(DisasContext *ctx, int reg) 569 { 570 return 8 + reg; 571 } 572 573 static int ex_rvc_shifti(DisasContext *ctx, int imm) 574 { 575 /* For RV128 a shamt of 0 means a shift by 64. */ 576 return imm ? imm : 64; 577 } 578 579 /* Include the auto-generated decoder for 32 bit insn */ 580 #include "decode_insn32.inc.c" 581 582 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, 583 void (*func)(TCGv, TCGv, target_long)) 584 { 585 TCGv source1; 586 source1 = tcg_temp_new(); 587 588 gen_get_gpr(source1, a->rs1); 589 590 (*func)(source1, source1, a->imm); 591 592 gen_set_gpr(a->rd, source1); 593 tcg_temp_free(source1); 594 return true; 595 } 596 597 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, 598 void (*func)(TCGv, TCGv, TCGv)) 599 { 600 TCGv source1, source2; 601 source1 = tcg_temp_new(); 602 source2 = tcg_temp_new(); 603 604 gen_get_gpr(source1, a->rs1); 605 tcg_gen_movi_tl(source2, a->imm); 606 607 (*func)(source1, source1, source2); 608 609 gen_set_gpr(a->rd, source1); 610 tcg_temp_free(source1); 611 tcg_temp_free(source2); 612 return true; 613 } 614 615 #ifdef TARGET_RISCV64 616 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) 617 { 618 tcg_gen_add_tl(ret, arg1, arg2); 619 tcg_gen_ext32s_tl(ret, ret); 620 } 621 622 static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) 623 { 624 tcg_gen_sub_tl(ret, arg1, arg2); 625 tcg_gen_ext32s_tl(ret, ret); 626 } 627 628 static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) 629 { 630 tcg_gen_mul_tl(ret, arg1, arg2); 631 tcg_gen_ext32s_tl(ret, ret); 632 } 633 634 static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, 635 void(*func)(TCGv, TCGv, TCGv)) 636 { 637 TCGv source1, source2; 638 source1 = tcg_temp_new(); 639 source2 = tcg_temp_new(); 640 641 gen_get_gpr(source1, a->rs1); 642 gen_get_gpr(source2, a->rs2); 643 tcg_gen_ext32s_tl(source1, source1); 644 tcg_gen_ext32s_tl(source2, source2); 645 646 (*func)(source1, source1, source2); 647 648 tcg_gen_ext32s_tl(source1, source1); 649 gen_set_gpr(a->rd, source1); 650 tcg_temp_free(source1); 651 tcg_temp_free(source2); 652 return true; 653 } 654 655 static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, 656 void(*func)(TCGv, TCGv, TCGv)) 657 { 658 TCGv source1, source2; 659 source1 = tcg_temp_new(); 660 source2 = tcg_temp_new(); 661 662 gen_get_gpr(source1, a->rs1); 663 gen_get_gpr(source2, a->rs2); 664 tcg_gen_ext32u_tl(source1, source1); 665 tcg_gen_ext32u_tl(source2, source2); 666 667 (*func)(source1, source1, source2); 668 669 tcg_gen_ext32s_tl(source1, source1); 670 gen_set_gpr(a->rd, source1); 671 tcg_temp_free(source1); 672 tcg_temp_free(source2); 673 return true; 674 } 675 676 #endif 677 678 static bool gen_arith(DisasContext *ctx, arg_r *a, 679 void(*func)(TCGv, TCGv, TCGv)) 680 { 681 TCGv source1, source2; 682 source1 = tcg_temp_new(); 683 source2 = tcg_temp_new(); 684 685 gen_get_gpr(source1, a->rs1); 686 gen_get_gpr(source2, a->rs2); 687 688 (*func)(source1, source1, source2); 689 690 gen_set_gpr(a->rd, source1); 691 tcg_temp_free(source1); 692 tcg_temp_free(source2); 693 return true; 694 } 695 696 static bool gen_shift(DisasContext *ctx, arg_r *a, 697 void(*func)(TCGv, TCGv, TCGv)) 698 { 699 TCGv source1 = tcg_temp_new(); 700 TCGv source2 = tcg_temp_new(); 701 702 gen_get_gpr(source1, a->rs1); 703 gen_get_gpr(source2, a->rs2); 704 705 tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); 706 (*func)(source1, source1, source2); 707 708 gen_set_gpr(a->rd, source1); 709 tcg_temp_free(source1); 710 tcg_temp_free(source2); 711 return true; 712 } 713 714 /* Include insn module translation function */ 715 #include "insn_trans/trans_rvi.inc.c" 716 #include "insn_trans/trans_rvm.inc.c" 717 #include "insn_trans/trans_rva.inc.c" 718 #include "insn_trans/trans_rvf.inc.c" 719 #include "insn_trans/trans_rvd.inc.c" 720 #include "insn_trans/trans_rvh.inc.c" 721 #include "insn_trans/trans_rvv.inc.c" 722 #include "insn_trans/trans_privileged.inc.c" 723 724 /* Include the auto-generated decoder for 16 bit insn */ 725 #include "decode_insn16.inc.c" 726 727 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 728 { 729 /* check for compressed insn */ 730 if (extract16(opcode, 0, 2) != 3) { 731 if (!has_ext(ctx, RVC)) { 732 gen_exception_illegal(ctx); 733 } else { 734 ctx->pc_succ_insn = ctx->base.pc_next + 2; 735 if (!decode_insn16(ctx, opcode)) { 736 /* fall back to old decoder */ 737 decode_RV32_64C(ctx, opcode); 738 } 739 } 740 } else { 741 uint32_t opcode32 = opcode; 742 opcode32 = deposit32(opcode32, 16, 16, 743 translator_lduw(env, ctx->base.pc_next + 2)); 744 ctx->pc_succ_insn = ctx->base.pc_next + 4; 745 if (!decode_insn32(ctx, opcode32)) { 746 gen_exception_illegal(ctx); 747 } 748 } 749 } 750 751 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 752 { 753 DisasContext *ctx = container_of(dcbase, DisasContext, base); 754 CPURISCVState *env = cs->env_ptr; 755 RISCVCPU *cpu = RISCV_CPU(cs); 756 uint32_t tb_flags = ctx->base.tb->flags; 757 758 ctx->pc_succ_insn = ctx->base.pc_first; 759 ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK; 760 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 761 ctx->priv_ver = env->priv_ver; 762 #if !defined(CONFIG_USER_ONLY) 763 if (riscv_has_ext(env, RVH)) { 764 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 765 if (env->priv_ver == PRV_M && 766 get_field(env->mstatus, MSTATUS_MPRV) && 767 MSTATUS_MPV_ISSET(env)) { 768 ctx->virt_enabled = true; 769 } else if (env->priv == PRV_S && 770 !riscv_cpu_virt_enabled(env) && 771 get_field(env->hstatus, HSTATUS_SPRV) && 772 get_field(env->hstatus, HSTATUS_SPV)) { 773 ctx->virt_enabled = true; 774 } 775 } else { 776 ctx->virt_enabled = false; 777 } 778 #else 779 ctx->virt_enabled = false; 780 #endif 781 ctx->misa = env->misa; 782 ctx->frm = -1; /* unknown rounding mode */ 783 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 784 ctx->vlen = cpu->cfg.vlen; 785 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 786 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 787 ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); 788 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 789 } 790 791 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 792 { 793 } 794 795 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 796 { 797 DisasContext *ctx = container_of(dcbase, DisasContext, base); 798 799 tcg_gen_insn_start(ctx->base.pc_next); 800 } 801 802 static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, 803 const CPUBreakpoint *bp) 804 { 805 DisasContext *ctx = container_of(dcbase, DisasContext, base); 806 807 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 808 ctx->base.is_jmp = DISAS_NORETURN; 809 gen_exception_debug(); 810 /* The address covered by the breakpoint must be included in 811 [tb->pc, tb->pc + tb->size) in order to for it to be 812 properly cleared -- thus we increment the PC here so that 813 the logic setting tb->size below does the right thing. */ 814 ctx->base.pc_next += 4; 815 return true; 816 } 817 818 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 819 { 820 DisasContext *ctx = container_of(dcbase, DisasContext, base); 821 CPURISCVState *env = cpu->env_ptr; 822 uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); 823 824 decode_opc(env, ctx, opcode16); 825 ctx->base.pc_next = ctx->pc_succ_insn; 826 827 if (ctx->base.is_jmp == DISAS_NEXT) { 828 target_ulong page_start; 829 830 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 831 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 832 ctx->base.is_jmp = DISAS_TOO_MANY; 833 } 834 } 835 } 836 837 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 838 { 839 DisasContext *ctx = container_of(dcbase, DisasContext, base); 840 841 switch (ctx->base.is_jmp) { 842 case DISAS_TOO_MANY: 843 gen_goto_tb(ctx, 0, ctx->base.pc_next); 844 break; 845 case DISAS_NORETURN: 846 break; 847 default: 848 g_assert_not_reached(); 849 } 850 } 851 852 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 853 { 854 #ifndef CONFIG_USER_ONLY 855 RISCVCPU *rvcpu = RISCV_CPU(cpu); 856 CPURISCVState *env = &rvcpu->env; 857 #endif 858 859 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 860 #ifndef CONFIG_USER_ONLY 861 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 862 #endif 863 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 864 } 865 866 static const TranslatorOps riscv_tr_ops = { 867 .init_disas_context = riscv_tr_init_disas_context, 868 .tb_start = riscv_tr_tb_start, 869 .insn_start = riscv_tr_insn_start, 870 .breakpoint_check = riscv_tr_breakpoint_check, 871 .translate_insn = riscv_tr_translate_insn, 872 .tb_stop = riscv_tr_tb_stop, 873 .disas_log = riscv_tr_disas_log, 874 }; 875 876 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 877 { 878 DisasContext ctx; 879 880 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 881 } 882 883 void riscv_translate_init(void) 884 { 885 int i; 886 887 /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ 888 /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ 889 /* registers, unless you specifically block reads/writes to reg 0 */ 890 cpu_gpr[0] = NULL; 891 892 for (i = 1; i < 32; i++) { 893 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 894 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 895 } 896 897 for (i = 0; i < 32; i++) { 898 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 899 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 900 } 901 902 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 903 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 904 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 905 "load_res"); 906 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 907 "load_val"); 908 } 909