1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask[4]; 42 static TCGv pm_base[4]; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL xl; 63 uint32_t misa_ext; 64 uint32_t opcode; 65 uint32_t mstatus_fs; 66 uint32_t mstatus_vs; 67 uint32_t mstatus_hs_fs; 68 uint32_t mstatus_hs_vs; 69 uint32_t mem_idx; 70 /* Remember the rounding mode encoded in the previous fp instruction, 71 which we have already installed into env->fp_status. Or -1 for 72 no previous fp instruction. Note that we exit the TB when writing 73 to any system register, which includes CSR_FRM, so we do not have 74 to reset this known value. */ 75 int frm; 76 RISCVMXL ol; 77 bool virt_enabled; 78 bool ext_ifencei; 79 bool ext_zfh; 80 bool ext_zfhmin; 81 bool hlsx; 82 /* vector extension */ 83 bool vill; 84 /* 85 * Encode LMUL to lmul as follows: 86 * LMUL vlmul lmul 87 * 1 000 0 88 * 2 001 1 89 * 4 010 2 90 * 8 011 3 91 * - 100 - 92 * 1/8 101 -3 93 * 1/4 110 -2 94 * 1/2 111 -1 95 */ 96 int8_t lmul; 97 uint8_t sew; 98 uint16_t vlen; 99 uint16_t elen; 100 target_ulong vstart; 101 bool vl_eq_vlmax; 102 uint8_t ntemp; 103 CPUState *cs; 104 TCGv zero; 105 /* Space for 3 operands plus 1 extra for address computation. */ 106 TCGv temp[4]; 107 /* PointerMasking extension */ 108 bool pm_enabled; 109 TCGv pm_mask; 110 TCGv pm_base; 111 } DisasContext; 112 113 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 114 { 115 return ctx->misa_ext & ext; 116 } 117 118 #ifdef TARGET_RISCV32 119 #define get_xl(ctx) MXL_RV32 120 #elif defined(CONFIG_USER_ONLY) 121 #define get_xl(ctx) MXL_RV64 122 #else 123 #define get_xl(ctx) ((ctx)->xl) 124 #endif 125 126 /* The word size for this machine mode. */ 127 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 128 { 129 return 16 << get_xl(ctx); 130 } 131 132 /* The operation length, as opposed to the xlen. */ 133 #ifdef TARGET_RISCV32 134 #define get_ol(ctx) MXL_RV32 135 #else 136 #define get_ol(ctx) ((ctx)->ol) 137 #endif 138 139 static inline int get_olen(DisasContext *ctx) 140 { 141 return 16 << get_ol(ctx); 142 } 143 144 /* 145 * RISC-V requires NaN-boxing of narrower width floating point values. 146 * This applies when a 32-bit value is assigned to a 64-bit FP register. 147 * For consistency and simplicity, we nanbox results even when the RVD 148 * extension is not present. 149 */ 150 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 151 { 152 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 153 } 154 155 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 156 { 157 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 158 } 159 160 /* 161 * A narrow n-bit operation, where n < FLEN, checks that input operands 162 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 163 * If so, the least-significant bits of the input are used, otherwise the 164 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 165 * 166 * Here, the result is always nan-boxed, even the canonical nan. 167 */ 168 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 169 { 170 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 171 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 172 173 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 174 tcg_temp_free_i64(t_max); 175 tcg_temp_free_i64(t_nan); 176 } 177 178 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 179 { 180 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 181 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 182 183 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 184 } 185 186 static void generate_exception(DisasContext *ctx, int excp) 187 { 188 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 189 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 190 ctx->base.is_jmp = DISAS_NORETURN; 191 } 192 193 static void generate_exception_mtval(DisasContext *ctx, int excp) 194 { 195 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 196 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 197 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 198 ctx->base.is_jmp = DISAS_NORETURN; 199 } 200 201 static void gen_exception_illegal(DisasContext *ctx) 202 { 203 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 204 } 205 206 static void gen_exception_inst_addr_mis(DisasContext *ctx) 207 { 208 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 209 } 210 211 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 212 { 213 if (translator_use_goto_tb(&ctx->base, dest)) { 214 tcg_gen_goto_tb(n); 215 tcg_gen_movi_tl(cpu_pc, dest); 216 tcg_gen_exit_tb(ctx->base.tb, n); 217 } else { 218 tcg_gen_movi_tl(cpu_pc, dest); 219 tcg_gen_lookup_and_goto_ptr(); 220 } 221 } 222 223 /* 224 * Wrappers for getting reg values. 225 * 226 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 227 * constant zero as a source, and an uninitialized sink as destination. 228 * 229 * Further, we may provide an extension for word operations. 230 */ 231 static TCGv temp_new(DisasContext *ctx) 232 { 233 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 234 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 235 } 236 237 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 238 { 239 TCGv t; 240 241 if (reg_num == 0) { 242 return ctx->zero; 243 } 244 245 switch (get_ol(ctx)) { 246 case MXL_RV32: 247 switch (ext) { 248 case EXT_NONE: 249 break; 250 case EXT_SIGN: 251 t = temp_new(ctx); 252 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 253 return t; 254 case EXT_ZERO: 255 t = temp_new(ctx); 256 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 257 return t; 258 default: 259 g_assert_not_reached(); 260 } 261 break; 262 case MXL_RV64: 263 break; 264 default: 265 g_assert_not_reached(); 266 } 267 return cpu_gpr[reg_num]; 268 } 269 270 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 271 { 272 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 273 return temp_new(ctx); 274 } 275 return cpu_gpr[reg_num]; 276 } 277 278 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 279 { 280 if (reg_num != 0) { 281 switch (get_ol(ctx)) { 282 case MXL_RV32: 283 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 284 break; 285 case MXL_RV64: 286 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 287 break; 288 default: 289 g_assert_not_reached(); 290 } 291 } 292 } 293 294 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 295 { 296 target_ulong next_pc; 297 298 /* check misaligned: */ 299 next_pc = ctx->base.pc_next + imm; 300 if (!has_ext(ctx, RVC)) { 301 if ((next_pc & 0x3) != 0) { 302 gen_exception_inst_addr_mis(ctx); 303 return; 304 } 305 } 306 if (rd != 0) { 307 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 308 } 309 310 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 311 ctx->base.is_jmp = DISAS_NORETURN; 312 } 313 314 /* 315 * Generates address adjustment for PointerMasking 316 */ 317 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) 318 { 319 TCGv temp; 320 if (!s->pm_enabled) { 321 /* Load unmodified address */ 322 return src; 323 } else { 324 temp = temp_new(s); 325 tcg_gen_andc_tl(temp, src, s->pm_mask); 326 tcg_gen_or_tl(temp, temp, s->pm_base); 327 return temp; 328 } 329 } 330 331 #ifndef CONFIG_USER_ONLY 332 /* The states of mstatus_fs are: 333 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 334 * We will have already diagnosed disabled state, 335 * and need to turn initial/clean into dirty. 336 */ 337 static void mark_fs_dirty(DisasContext *ctx) 338 { 339 TCGv tmp; 340 341 if (ctx->mstatus_fs != MSTATUS_FS) { 342 /* Remember the state change for the rest of the TB. */ 343 ctx->mstatus_fs = MSTATUS_FS; 344 345 tmp = tcg_temp_new(); 346 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 347 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 348 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 349 tcg_temp_free(tmp); 350 } 351 352 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 353 /* Remember the stage change for the rest of the TB. */ 354 ctx->mstatus_hs_fs = MSTATUS_FS; 355 356 tmp = tcg_temp_new(); 357 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 358 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 359 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 360 tcg_temp_free(tmp); 361 } 362 } 363 #else 364 static inline void mark_fs_dirty(DisasContext *ctx) { } 365 #endif 366 367 #ifndef CONFIG_USER_ONLY 368 /* The states of mstatus_vs are: 369 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 370 * We will have already diagnosed disabled state, 371 * and need to turn initial/clean into dirty. 372 */ 373 static void mark_vs_dirty(DisasContext *ctx) 374 { 375 TCGv tmp; 376 377 if (ctx->mstatus_vs != MSTATUS_VS) { 378 /* Remember the state change for the rest of the TB. */ 379 ctx->mstatus_vs = MSTATUS_VS; 380 381 tmp = tcg_temp_new(); 382 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 383 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 384 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 385 tcg_temp_free(tmp); 386 } 387 388 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 389 /* Remember the stage change for the rest of the TB. */ 390 ctx->mstatus_hs_vs = MSTATUS_VS; 391 392 tmp = tcg_temp_new(); 393 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 394 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 395 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 396 tcg_temp_free(tmp); 397 } 398 } 399 #else 400 static inline void mark_vs_dirty(DisasContext *ctx) { } 401 #endif 402 403 static void gen_set_rm(DisasContext *ctx, int rm) 404 { 405 if (ctx->frm == rm) { 406 return; 407 } 408 ctx->frm = rm; 409 410 if (rm == RISCV_FRM_ROD) { 411 gen_helper_set_rod_rounding_mode(cpu_env); 412 return; 413 } 414 415 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 416 } 417 418 static int ex_plus_1(DisasContext *ctx, int nf) 419 { 420 return nf + 1; 421 } 422 423 #define EX_SH(amount) \ 424 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 425 { \ 426 return imm << amount; \ 427 } 428 EX_SH(1) 429 EX_SH(2) 430 EX_SH(3) 431 EX_SH(4) 432 EX_SH(12) 433 434 #define REQUIRE_EXT(ctx, ext) do { \ 435 if (!has_ext(ctx, ext)) { \ 436 return false; \ 437 } \ 438 } while (0) 439 440 #define REQUIRE_32BIT(ctx) do { \ 441 if (get_xl(ctx) != MXL_RV32) { \ 442 return false; \ 443 } \ 444 } while (0) 445 446 #define REQUIRE_64BIT(ctx) do { \ 447 if (get_xl(ctx) != MXL_RV64) { \ 448 return false; \ 449 } \ 450 } while (0) 451 452 #define REQUIRE_128BIT(ctx) do { \ 453 if (get_xl(ctx) != MXL_RV128) { \ 454 return false; \ 455 } \ 456 } while (0) 457 458 #define REQUIRE_64_OR_128BIT(ctx) do { \ 459 if (get_xl(ctx) == MXL_RV32) { \ 460 return false; \ 461 } \ 462 } while (0) 463 464 static int ex_rvc_register(DisasContext *ctx, int reg) 465 { 466 return 8 + reg; 467 } 468 469 static int ex_rvc_shifti(DisasContext *ctx, int imm) 470 { 471 /* For RV128 a shamt of 0 means a shift by 64. */ 472 return imm ? imm : 64; 473 } 474 475 /* Include the auto-generated decoder for 32 bit insn */ 476 #include "decode-insn32.c.inc" 477 478 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 479 void (*func)(TCGv, TCGv, target_long)) 480 { 481 TCGv dest = dest_gpr(ctx, a->rd); 482 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 483 484 func(dest, src1, a->imm); 485 486 gen_set_gpr(ctx, a->rd, dest); 487 488 return true; 489 } 490 491 static bool gen_logic(DisasContext *ctx, arg_r *a, 492 void (*func)(TCGv, TCGv, TCGv)) 493 { 494 TCGv dest = dest_gpr(ctx, a->rd); 495 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 496 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 497 498 func(dest, src1, src2); 499 500 gen_set_gpr(ctx, a->rd, dest); 501 502 return true; 503 } 504 505 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 506 void (*func)(TCGv, TCGv, target_long)) 507 { 508 TCGv dest = dest_gpr(ctx, a->rd); 509 TCGv src1 = get_gpr(ctx, a->rs1, ext); 510 511 func(dest, src1, a->imm); 512 513 gen_set_gpr(ctx, a->rd, dest); 514 return true; 515 } 516 517 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 518 void (*func)(TCGv, TCGv, TCGv)) 519 { 520 TCGv dest = dest_gpr(ctx, a->rd); 521 TCGv src1 = get_gpr(ctx, a->rs1, ext); 522 TCGv src2 = tcg_constant_tl(a->imm); 523 524 func(dest, src1, src2); 525 526 gen_set_gpr(ctx, a->rd, dest); 527 return true; 528 } 529 530 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 531 void (*func)(TCGv, TCGv, TCGv)) 532 { 533 TCGv dest = dest_gpr(ctx, a->rd); 534 TCGv src1 = get_gpr(ctx, a->rs1, ext); 535 TCGv src2 = get_gpr(ctx, a->rs2, ext); 536 537 func(dest, src1, src2); 538 539 gen_set_gpr(ctx, a->rd, dest); 540 return true; 541 } 542 543 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 544 void (*f_tl)(TCGv, TCGv, TCGv), 545 void (*f_32)(TCGv, TCGv, TCGv)) 546 { 547 int olen = get_olen(ctx); 548 549 if (olen != TARGET_LONG_BITS) { 550 if (olen == 32) { 551 f_tl = f_32; 552 } else { 553 g_assert_not_reached(); 554 } 555 } 556 return gen_arith(ctx, a, ext, f_tl); 557 } 558 559 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 560 void (*func)(TCGv, TCGv, target_long)) 561 { 562 TCGv dest, src1; 563 int max_len = get_olen(ctx); 564 565 if (a->shamt >= max_len) { 566 return false; 567 } 568 569 dest = dest_gpr(ctx, a->rd); 570 src1 = get_gpr(ctx, a->rs1, ext); 571 572 func(dest, src1, a->shamt); 573 574 gen_set_gpr(ctx, a->rd, dest); 575 return true; 576 } 577 578 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 579 DisasExtend ext, 580 void (*f_tl)(TCGv, TCGv, target_long), 581 void (*f_32)(TCGv, TCGv, target_long)) 582 { 583 int olen = get_olen(ctx); 584 if (olen != TARGET_LONG_BITS) { 585 if (olen == 32) { 586 f_tl = f_32; 587 } else { 588 g_assert_not_reached(); 589 } 590 } 591 return gen_shift_imm_fn(ctx, a, ext, f_tl); 592 } 593 594 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 595 void (*func)(TCGv, TCGv, TCGv)) 596 { 597 TCGv dest, src1, src2; 598 int max_len = get_olen(ctx); 599 600 if (a->shamt >= max_len) { 601 return false; 602 } 603 604 dest = dest_gpr(ctx, a->rd); 605 src1 = get_gpr(ctx, a->rs1, ext); 606 src2 = tcg_constant_tl(a->shamt); 607 608 func(dest, src1, src2); 609 610 gen_set_gpr(ctx, a->rd, dest); 611 return true; 612 } 613 614 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 615 void (*func)(TCGv, TCGv, TCGv)) 616 { 617 TCGv dest = dest_gpr(ctx, a->rd); 618 TCGv src1 = get_gpr(ctx, a->rs1, ext); 619 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 620 TCGv ext2 = tcg_temp_new(); 621 622 tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); 623 func(dest, src1, ext2); 624 625 gen_set_gpr(ctx, a->rd, dest); 626 tcg_temp_free(ext2); 627 return true; 628 } 629 630 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 631 void (*f_tl)(TCGv, TCGv, TCGv), 632 void (*f_32)(TCGv, TCGv, TCGv)) 633 { 634 int olen = get_olen(ctx); 635 if (olen != TARGET_LONG_BITS) { 636 if (olen == 32) { 637 f_tl = f_32; 638 } else { 639 g_assert_not_reached(); 640 } 641 } 642 return gen_shift(ctx, a, ext, f_tl); 643 } 644 645 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 646 void (*func)(TCGv, TCGv)) 647 { 648 TCGv dest = dest_gpr(ctx, a->rd); 649 TCGv src1 = get_gpr(ctx, a->rs1, ext); 650 651 func(dest, src1); 652 653 gen_set_gpr(ctx, a->rd, dest); 654 return true; 655 } 656 657 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 658 void (*f_tl)(TCGv, TCGv), 659 void (*f_32)(TCGv, TCGv)) 660 { 661 int olen = get_olen(ctx); 662 663 if (olen != TARGET_LONG_BITS) { 664 if (olen == 32) { 665 f_tl = f_32; 666 } else { 667 g_assert_not_reached(); 668 } 669 } 670 return gen_unary(ctx, a, ext, f_tl); 671 } 672 673 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 674 { 675 DisasContext *ctx = container_of(dcbase, DisasContext, base); 676 CPUState *cpu = ctx->cs; 677 CPURISCVState *env = cpu->env_ptr; 678 679 return cpu_ldl_code(env, pc); 680 } 681 682 /* Include insn module translation function */ 683 #include "insn_trans/trans_rvi.c.inc" 684 #include "insn_trans/trans_rvm.c.inc" 685 #include "insn_trans/trans_rva.c.inc" 686 #include "insn_trans/trans_rvf.c.inc" 687 #include "insn_trans/trans_rvd.c.inc" 688 #include "insn_trans/trans_rvh.c.inc" 689 #include "insn_trans/trans_rvv.c.inc" 690 #include "insn_trans/trans_rvb.c.inc" 691 #include "insn_trans/trans_rvzfh.c.inc" 692 #include "insn_trans/trans_privileged.c.inc" 693 694 /* Include the auto-generated decoder for 16 bit insn */ 695 #include "decode-insn16.c.inc" 696 697 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 698 { 699 /* check for compressed insn */ 700 if (extract16(opcode, 0, 2) != 3) { 701 if (!has_ext(ctx, RVC)) { 702 gen_exception_illegal(ctx); 703 } else { 704 ctx->pc_succ_insn = ctx->base.pc_next + 2; 705 if (!decode_insn16(ctx, opcode)) { 706 gen_exception_illegal(ctx); 707 } 708 } 709 } else { 710 uint32_t opcode32 = opcode; 711 opcode32 = deposit32(opcode32, 16, 16, 712 translator_lduw(env, &ctx->base, 713 ctx->base.pc_next + 2)); 714 ctx->pc_succ_insn = ctx->base.pc_next + 4; 715 if (!decode_insn32(ctx, opcode32)) { 716 gen_exception_illegal(ctx); 717 } 718 } 719 } 720 721 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 722 { 723 DisasContext *ctx = container_of(dcbase, DisasContext, base); 724 CPURISCVState *env = cs->env_ptr; 725 RISCVCPU *cpu = RISCV_CPU(cs); 726 uint32_t tb_flags = ctx->base.tb->flags; 727 728 ctx->pc_succ_insn = ctx->base.pc_first; 729 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 730 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 731 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 732 ctx->priv_ver = env->priv_ver; 733 #if !defined(CONFIG_USER_ONLY) 734 if (riscv_has_ext(env, RVH)) { 735 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 736 } else { 737 ctx->virt_enabled = false; 738 } 739 #else 740 ctx->virt_enabled = false; 741 #endif 742 ctx->misa_ext = env->misa_ext; 743 ctx->frm = -1; /* unknown rounding mode */ 744 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 745 ctx->ext_zfh = cpu->cfg.ext_zfh; 746 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; 747 ctx->vlen = cpu->cfg.vlen; 748 ctx->elen = cpu->cfg.elen; 749 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 750 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 751 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 752 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 753 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 754 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 755 ctx->vstart = env->vstart; 756 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 757 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 758 ctx->cs = cs; 759 ctx->ntemp = 0; 760 memset(ctx->temp, 0, sizeof(ctx->temp)); 761 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); 762 int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK; 763 ctx->pm_mask = pm_mask[priv]; 764 ctx->pm_base = pm_base[priv]; 765 766 ctx->zero = tcg_constant_tl(0); 767 } 768 769 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 770 { 771 } 772 773 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 774 { 775 DisasContext *ctx = container_of(dcbase, DisasContext, base); 776 777 tcg_gen_insn_start(ctx->base.pc_next); 778 } 779 780 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 781 { 782 DisasContext *ctx = container_of(dcbase, DisasContext, base); 783 CPURISCVState *env = cpu->env_ptr; 784 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 785 786 ctx->ol = ctx->xl; 787 decode_opc(env, ctx, opcode16); 788 ctx->base.pc_next = ctx->pc_succ_insn; 789 790 for (int i = ctx->ntemp - 1; i >= 0; --i) { 791 tcg_temp_free(ctx->temp[i]); 792 ctx->temp[i] = NULL; 793 } 794 ctx->ntemp = 0; 795 796 if (ctx->base.is_jmp == DISAS_NEXT) { 797 target_ulong page_start; 798 799 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 800 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 801 ctx->base.is_jmp = DISAS_TOO_MANY; 802 } 803 } 804 } 805 806 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 807 { 808 DisasContext *ctx = container_of(dcbase, DisasContext, base); 809 810 switch (ctx->base.is_jmp) { 811 case DISAS_TOO_MANY: 812 gen_goto_tb(ctx, 0, ctx->base.pc_next); 813 break; 814 case DISAS_NORETURN: 815 break; 816 default: 817 g_assert_not_reached(); 818 } 819 } 820 821 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 822 { 823 #ifndef CONFIG_USER_ONLY 824 RISCVCPU *rvcpu = RISCV_CPU(cpu); 825 CPURISCVState *env = &rvcpu->env; 826 #endif 827 828 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 829 #ifndef CONFIG_USER_ONLY 830 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 831 #endif 832 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 833 } 834 835 static const TranslatorOps riscv_tr_ops = { 836 .init_disas_context = riscv_tr_init_disas_context, 837 .tb_start = riscv_tr_tb_start, 838 .insn_start = riscv_tr_insn_start, 839 .translate_insn = riscv_tr_translate_insn, 840 .tb_stop = riscv_tr_tb_stop, 841 .disas_log = riscv_tr_disas_log, 842 }; 843 844 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 845 { 846 DisasContext ctx; 847 848 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 849 } 850 851 void riscv_translate_init(void) 852 { 853 int i; 854 855 /* 856 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 857 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 858 * unless you specifically block reads/writes to reg 0. 859 */ 860 cpu_gpr[0] = NULL; 861 cpu_gprh[0] = NULL; 862 863 for (i = 1; i < 32; i++) { 864 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 865 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 866 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 867 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 868 } 869 870 for (i = 0; i < 32; i++) { 871 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 872 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 873 } 874 875 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 876 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 877 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 878 "vstart"); 879 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 880 "load_res"); 881 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 882 "load_val"); 883 #ifndef CONFIG_USER_ONLY 884 /* Assign PM CSRs to tcg globals */ 885 pm_mask[PRV_U] = 886 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); 887 pm_base[PRV_U] = 888 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); 889 pm_mask[PRV_S] = 890 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask"); 891 pm_base[PRV_S] = 892 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase"); 893 pm_mask[PRV_M] = 894 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask"); 895 pm_base[PRV_M] = 896 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase"); 897 #endif 898 } 899