1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 /* global register indices */ 37 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 38 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 39 static TCGv load_res; 40 static TCGv load_val; 41 /* globals for PM CSRs */ 42 static TCGv pm_mask; 43 static TCGv pm_base; 44 45 #include "exec/gen-icount.h" 46 47 /* 48 * If an operation is being performed on less than TARGET_LONG_BITS, 49 * it may require the inputs to be sign- or zero-extended; which will 50 * depend on the exact operation being performed. 51 */ 52 typedef enum { 53 EXT_NONE, 54 EXT_SIGN, 55 EXT_ZERO, 56 } DisasExtend; 57 58 typedef struct DisasContext { 59 DisasContextBase base; 60 /* pc_succ_insn points to the instruction following base.pc_next */ 61 target_ulong pc_succ_insn; 62 target_ulong priv_ver; 63 RISCVMXL misa_mxl_max; 64 RISCVMXL xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 uint32_t mstatus_fs; 68 uint32_t mstatus_vs; 69 uint32_t mstatus_hs_fs; 70 uint32_t mstatus_hs_vs; 71 uint32_t mem_idx; 72 /* Remember the rounding mode encoded in the previous fp instruction, 73 which we have already installed into env->fp_status. Or -1 for 74 no previous fp instruction. Note that we exit the TB when writing 75 to any system register, which includes CSR_FRM, so we do not have 76 to reset this known value. */ 77 int frm; 78 RISCVMXL ol; 79 bool virt_inst_excp; 80 bool virt_enabled; 81 const RISCVCPUConfig *cfg_ptr; 82 bool hlsx; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint8_t vta; 100 uint8_t vma; 101 bool cfg_vta_all_1s; 102 target_ulong vstart; 103 bool vl_eq_vlmax; 104 uint8_t ntemp; 105 CPUState *cs; 106 TCGv zero; 107 /* Space for 3 operands plus 1 extra for address computation. */ 108 TCGv temp[4]; 109 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 110 TCGv_i64 ftemp[4]; 111 uint8_t nftemp; 112 /* PointerMasking extension */ 113 bool pm_mask_enabled; 114 bool pm_base_enabled; 115 /* Use icount trigger for native debug */ 116 bool itrigger; 117 /* FRM is known to contain a valid value. */ 118 bool frm_valid; 119 /* TCG of the current insn_start */ 120 TCGOp *insn_start; 121 } DisasContext; 122 123 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 124 { 125 return ctx->misa_ext & ext; 126 } 127 128 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 129 { 130 return true; 131 } 132 133 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) 134 { 135 return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || 136 ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || 137 ctx->cfg_ptr->ext_xtheadcondmov || 138 ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || 139 ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || 140 ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; 141 } 142 143 #define MATERIALISE_EXT_PREDICATE(ext) \ 144 static bool has_ ## ext ## _p(DisasContext *ctx) \ 145 { \ 146 return ctx->cfg_ptr->ext_ ## ext ; \ 147 } 148 149 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 150 151 #ifdef TARGET_RISCV32 152 #define get_xl(ctx) MXL_RV32 153 #elif defined(CONFIG_USER_ONLY) 154 #define get_xl(ctx) MXL_RV64 155 #else 156 #define get_xl(ctx) ((ctx)->xl) 157 #endif 158 159 /* The word size for this machine mode. */ 160 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 161 { 162 return 16 << get_xl(ctx); 163 } 164 165 /* The operation length, as opposed to the xlen. */ 166 #ifdef TARGET_RISCV32 167 #define get_ol(ctx) MXL_RV32 168 #else 169 #define get_ol(ctx) ((ctx)->ol) 170 #endif 171 172 static inline int get_olen(DisasContext *ctx) 173 { 174 return 16 << get_ol(ctx); 175 } 176 177 /* The maximum register length */ 178 #ifdef TARGET_RISCV32 179 #define get_xl_max(ctx) MXL_RV32 180 #else 181 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 182 #endif 183 184 /* 185 * RISC-V requires NaN-boxing of narrower width floating point values. 186 * This applies when a 32-bit value is assigned to a 64-bit FP register. 187 * For consistency and simplicity, we nanbox results even when the RVD 188 * extension is not present. 189 */ 190 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 191 { 192 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 193 } 194 195 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 196 { 197 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 198 } 199 200 /* 201 * A narrow n-bit operation, where n < FLEN, checks that input operands 202 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 203 * If so, the least-significant bits of the input are used, otherwise the 204 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 205 * 206 * Here, the result is always nan-boxed, even the canonical nan. 207 */ 208 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 209 { 210 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 211 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 212 213 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 214 tcg_temp_free_i64(t_max); 215 tcg_temp_free_i64(t_nan); 216 } 217 218 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 219 { 220 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 221 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 222 223 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 224 } 225 226 static void decode_save_opc(DisasContext *ctx) 227 { 228 assert(ctx->insn_start != NULL); 229 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 230 ctx->insn_start = NULL; 231 } 232 233 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 234 { 235 if (get_xl(ctx) == MXL_RV32) { 236 dest = (int32_t)dest; 237 } 238 tcg_gen_movi_tl(cpu_pc, dest); 239 } 240 241 static void gen_set_pc(DisasContext *ctx, TCGv dest) 242 { 243 if (get_xl(ctx) == MXL_RV32) { 244 tcg_gen_ext32s_tl(cpu_pc, dest); 245 } else { 246 tcg_gen_mov_tl(cpu_pc, dest); 247 } 248 } 249 250 static void generate_exception(DisasContext *ctx, int excp) 251 { 252 gen_set_pc_imm(ctx, ctx->base.pc_next); 253 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 254 ctx->base.is_jmp = DISAS_NORETURN; 255 } 256 257 static void gen_exception_illegal(DisasContext *ctx) 258 { 259 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 260 offsetof(CPURISCVState, bins)); 261 if (ctx->virt_inst_excp) { 262 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 263 } else { 264 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 265 } 266 } 267 268 static void gen_exception_inst_addr_mis(DisasContext *ctx) 269 { 270 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 271 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 272 } 273 274 static void lookup_and_goto_ptr(DisasContext *ctx) 275 { 276 #ifndef CONFIG_USER_ONLY 277 if (ctx->itrigger) { 278 gen_helper_itrigger_match(cpu_env); 279 } 280 #endif 281 tcg_gen_lookup_and_goto_ptr(); 282 } 283 284 static void exit_tb(DisasContext *ctx) 285 { 286 #ifndef CONFIG_USER_ONLY 287 if (ctx->itrigger) { 288 gen_helper_itrigger_match(cpu_env); 289 } 290 #endif 291 tcg_gen_exit_tb(NULL, 0); 292 } 293 294 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 295 { 296 /* 297 * Under itrigger, instruction executes one by one like singlestep, 298 * direct block chain benefits will be small. 299 */ 300 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 301 tcg_gen_goto_tb(n); 302 gen_set_pc_imm(ctx, dest); 303 tcg_gen_exit_tb(ctx->base.tb, n); 304 } else { 305 gen_set_pc_imm(ctx, dest); 306 lookup_and_goto_ptr(ctx); 307 } 308 } 309 310 /* 311 * Wrappers for getting reg values. 312 * 313 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 314 * constant zero as a source, and an uninitialized sink as destination. 315 * 316 * Further, we may provide an extension for word operations. 317 */ 318 static TCGv temp_new(DisasContext *ctx) 319 { 320 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 321 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 322 } 323 324 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 325 { 326 TCGv t; 327 328 if (reg_num == 0) { 329 return ctx->zero; 330 } 331 332 switch (get_ol(ctx)) { 333 case MXL_RV32: 334 switch (ext) { 335 case EXT_NONE: 336 break; 337 case EXT_SIGN: 338 t = temp_new(ctx); 339 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 340 return t; 341 case EXT_ZERO: 342 t = temp_new(ctx); 343 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 344 return t; 345 default: 346 g_assert_not_reached(); 347 } 348 break; 349 case MXL_RV64: 350 case MXL_RV128: 351 break; 352 default: 353 g_assert_not_reached(); 354 } 355 return cpu_gpr[reg_num]; 356 } 357 358 static TCGv get_gprh(DisasContext *ctx, int reg_num) 359 { 360 assert(get_xl(ctx) == MXL_RV128); 361 if (reg_num == 0) { 362 return ctx->zero; 363 } 364 return cpu_gprh[reg_num]; 365 } 366 367 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 368 { 369 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 370 return temp_new(ctx); 371 } 372 return cpu_gpr[reg_num]; 373 } 374 375 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 376 { 377 if (reg_num == 0) { 378 return temp_new(ctx); 379 } 380 return cpu_gprh[reg_num]; 381 } 382 383 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 384 { 385 if (reg_num != 0) { 386 switch (get_ol(ctx)) { 387 case MXL_RV32: 388 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 389 break; 390 case MXL_RV64: 391 case MXL_RV128: 392 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 393 break; 394 default: 395 g_assert_not_reached(); 396 } 397 398 if (get_xl_max(ctx) == MXL_RV128) { 399 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 400 } 401 } 402 } 403 404 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 405 { 406 if (reg_num != 0) { 407 switch (get_ol(ctx)) { 408 case MXL_RV32: 409 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 410 break; 411 case MXL_RV64: 412 case MXL_RV128: 413 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 414 break; 415 default: 416 g_assert_not_reached(); 417 } 418 419 if (get_xl_max(ctx) == MXL_RV128) { 420 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 421 } 422 } 423 } 424 425 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 426 { 427 assert(get_ol(ctx) == MXL_RV128); 428 if (reg_num != 0) { 429 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 430 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 431 } 432 } 433 434 static TCGv_i64 ftemp_new(DisasContext *ctx) 435 { 436 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 437 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 438 } 439 440 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 441 { 442 if (!ctx->cfg_ptr->ext_zfinx) { 443 return cpu_fpr[reg_num]; 444 } 445 446 if (reg_num == 0) { 447 return tcg_constant_i64(0); 448 } 449 switch (get_xl(ctx)) { 450 case MXL_RV32: 451 #ifdef TARGET_RISCV32 452 { 453 TCGv_i64 t = ftemp_new(ctx); 454 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 455 return t; 456 } 457 #else 458 /* fall through */ 459 case MXL_RV64: 460 return cpu_gpr[reg_num]; 461 #endif 462 default: 463 g_assert_not_reached(); 464 } 465 } 466 467 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 468 { 469 if (!ctx->cfg_ptr->ext_zfinx) { 470 return cpu_fpr[reg_num]; 471 } 472 473 if (reg_num == 0) { 474 return tcg_constant_i64(0); 475 } 476 switch (get_xl(ctx)) { 477 case MXL_RV32: 478 { 479 TCGv_i64 t = ftemp_new(ctx); 480 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 481 return t; 482 } 483 #ifdef TARGET_RISCV64 484 case MXL_RV64: 485 return cpu_gpr[reg_num]; 486 #endif 487 default: 488 g_assert_not_reached(); 489 } 490 } 491 492 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 493 { 494 if (!ctx->cfg_ptr->ext_zfinx) { 495 return cpu_fpr[reg_num]; 496 } 497 498 if (reg_num == 0) { 499 return ftemp_new(ctx); 500 } 501 502 switch (get_xl(ctx)) { 503 case MXL_RV32: 504 return ftemp_new(ctx); 505 #ifdef TARGET_RISCV64 506 case MXL_RV64: 507 return cpu_gpr[reg_num]; 508 #endif 509 default: 510 g_assert_not_reached(); 511 } 512 } 513 514 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 515 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 516 { 517 if (!ctx->cfg_ptr->ext_zfinx) { 518 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 519 return; 520 } 521 if (reg_num != 0) { 522 switch (get_xl(ctx)) { 523 case MXL_RV32: 524 #ifdef TARGET_RISCV32 525 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 526 break; 527 #else 528 /* fall through */ 529 case MXL_RV64: 530 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 531 break; 532 #endif 533 default: 534 g_assert_not_reached(); 535 } 536 } 537 } 538 539 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 540 { 541 if (!ctx->cfg_ptr->ext_zfinx) { 542 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 543 return; 544 } 545 546 if (reg_num != 0) { 547 switch (get_xl(ctx)) { 548 case MXL_RV32: 549 #ifdef TARGET_RISCV32 550 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 551 break; 552 #else 553 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 554 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 555 break; 556 case MXL_RV64: 557 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 558 break; 559 #endif 560 default: 561 g_assert_not_reached(); 562 } 563 } 564 } 565 566 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 567 { 568 target_ulong next_pc; 569 570 /* check misaligned: */ 571 next_pc = ctx->base.pc_next + imm; 572 if (!has_ext(ctx, RVC)) { 573 if ((next_pc & 0x3) != 0) { 574 gen_exception_inst_addr_mis(ctx); 575 return; 576 } 577 } 578 579 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 580 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 581 ctx->base.is_jmp = DISAS_NORETURN; 582 } 583 584 /* Compute a canonical address from a register plus offset. */ 585 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 586 { 587 TCGv addr = temp_new(ctx); 588 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 589 590 tcg_gen_addi_tl(addr, src1, imm); 591 if (ctx->pm_mask_enabled) { 592 tcg_gen_andc_tl(addr, addr, pm_mask); 593 } else if (get_xl(ctx) == MXL_RV32) { 594 tcg_gen_ext32u_tl(addr, addr); 595 } 596 if (ctx->pm_base_enabled) { 597 tcg_gen_or_tl(addr, addr, pm_base); 598 } 599 return addr; 600 } 601 602 /* Compute a canonical address from a register plus reg offset. */ 603 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 604 { 605 TCGv addr = temp_new(ctx); 606 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 607 608 tcg_gen_add_tl(addr, src1, offs); 609 if (ctx->pm_mask_enabled) { 610 tcg_gen_andc_tl(addr, addr, pm_mask); 611 } else if (get_xl(ctx) == MXL_RV32) { 612 tcg_gen_ext32u_tl(addr, addr); 613 } 614 if (ctx->pm_base_enabled) { 615 tcg_gen_or_tl(addr, addr, pm_base); 616 } 617 return addr; 618 } 619 620 #ifndef CONFIG_USER_ONLY 621 /* The states of mstatus_fs are: 622 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 623 * We will have already diagnosed disabled state, 624 * and need to turn initial/clean into dirty. 625 */ 626 static void mark_fs_dirty(DisasContext *ctx) 627 { 628 TCGv tmp; 629 630 if (!has_ext(ctx, RVF)) { 631 return; 632 } 633 634 if (ctx->mstatus_fs != MSTATUS_FS) { 635 /* Remember the state change for the rest of the TB. */ 636 ctx->mstatus_fs = MSTATUS_FS; 637 638 tmp = tcg_temp_new(); 639 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 640 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 641 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 642 tcg_temp_free(tmp); 643 } 644 645 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 646 /* Remember the stage change for the rest of the TB. */ 647 ctx->mstatus_hs_fs = MSTATUS_FS; 648 649 tmp = tcg_temp_new(); 650 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 651 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 652 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 653 tcg_temp_free(tmp); 654 } 655 } 656 #else 657 static inline void mark_fs_dirty(DisasContext *ctx) { } 658 #endif 659 660 #ifndef CONFIG_USER_ONLY 661 /* The states of mstatus_vs are: 662 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 663 * We will have already diagnosed disabled state, 664 * and need to turn initial/clean into dirty. 665 */ 666 static void mark_vs_dirty(DisasContext *ctx) 667 { 668 TCGv tmp; 669 670 if (ctx->mstatus_vs != MSTATUS_VS) { 671 /* Remember the state change for the rest of the TB. */ 672 ctx->mstatus_vs = MSTATUS_VS; 673 674 tmp = tcg_temp_new(); 675 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 676 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 677 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 678 tcg_temp_free(tmp); 679 } 680 681 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 682 /* Remember the stage change for the rest of the TB. */ 683 ctx->mstatus_hs_vs = MSTATUS_VS; 684 685 tmp = tcg_temp_new(); 686 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 687 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 688 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 689 tcg_temp_free(tmp); 690 } 691 } 692 #else 693 static inline void mark_vs_dirty(DisasContext *ctx) { } 694 #endif 695 696 static void gen_set_rm(DisasContext *ctx, int rm) 697 { 698 if (ctx->frm == rm) { 699 return; 700 } 701 ctx->frm = rm; 702 703 if (rm == RISCV_FRM_DYN) { 704 /* The helper will return only if frm valid. */ 705 ctx->frm_valid = true; 706 } 707 708 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 709 decode_save_opc(ctx); 710 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 711 } 712 713 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 714 { 715 if (ctx->frm == rm && ctx->frm_valid) { 716 return; 717 } 718 ctx->frm = rm; 719 ctx->frm_valid = true; 720 721 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 722 decode_save_opc(ctx); 723 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 724 } 725 726 static int ex_plus_1(DisasContext *ctx, int nf) 727 { 728 return nf + 1; 729 } 730 731 #define EX_SH(amount) \ 732 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 733 { \ 734 return imm << amount; \ 735 } 736 EX_SH(1) 737 EX_SH(2) 738 EX_SH(3) 739 EX_SH(4) 740 EX_SH(12) 741 742 #define REQUIRE_EXT(ctx, ext) do { \ 743 if (!has_ext(ctx, ext)) { \ 744 return false; \ 745 } \ 746 } while (0) 747 748 #define REQUIRE_32BIT(ctx) do { \ 749 if (get_xl(ctx) != MXL_RV32) { \ 750 return false; \ 751 } \ 752 } while (0) 753 754 #define REQUIRE_64BIT(ctx) do { \ 755 if (get_xl(ctx) != MXL_RV64) { \ 756 return false; \ 757 } \ 758 } while (0) 759 760 #define REQUIRE_128BIT(ctx) do { \ 761 if (get_xl(ctx) != MXL_RV128) { \ 762 return false; \ 763 } \ 764 } while (0) 765 766 #define REQUIRE_64_OR_128BIT(ctx) do { \ 767 if (get_xl(ctx) == MXL_RV32) { \ 768 return false; \ 769 } \ 770 } while (0) 771 772 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 773 if (!ctx->cfg_ptr->ext_##A && \ 774 !ctx->cfg_ptr->ext_##B) { \ 775 return false; \ 776 } \ 777 } while (0) 778 779 static int ex_rvc_register(DisasContext *ctx, int reg) 780 { 781 return 8 + reg; 782 } 783 784 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 785 { 786 /* For RV128 a shamt of 0 means a shift by 64. */ 787 if (get_ol(ctx) == MXL_RV128) { 788 imm = imm ? imm : 64; 789 } 790 return imm; 791 } 792 793 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 794 { 795 /* 796 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 797 * shifts, the shamt is sign-extended. 798 */ 799 if (get_ol(ctx) == MXL_RV128) { 800 imm = imm | (imm & 32) << 1; 801 imm = imm ? imm : 64; 802 } 803 return imm; 804 } 805 806 /* Include the auto-generated decoder for 32 bit insn */ 807 #include "decode-insn32.c.inc" 808 809 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 810 void (*func)(TCGv, TCGv, target_long)) 811 { 812 TCGv dest = dest_gpr(ctx, a->rd); 813 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 814 815 func(dest, src1, a->imm); 816 817 if (get_xl(ctx) == MXL_RV128) { 818 TCGv src1h = get_gprh(ctx, a->rs1); 819 TCGv desth = dest_gprh(ctx, a->rd); 820 821 func(desth, src1h, -(a->imm < 0)); 822 gen_set_gpr128(ctx, a->rd, dest, desth); 823 } else { 824 gen_set_gpr(ctx, a->rd, dest); 825 } 826 827 return true; 828 } 829 830 static bool gen_logic(DisasContext *ctx, arg_r *a, 831 void (*func)(TCGv, TCGv, TCGv)) 832 { 833 TCGv dest = dest_gpr(ctx, a->rd); 834 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 835 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 836 837 func(dest, src1, src2); 838 839 if (get_xl(ctx) == MXL_RV128) { 840 TCGv src1h = get_gprh(ctx, a->rs1); 841 TCGv src2h = get_gprh(ctx, a->rs2); 842 TCGv desth = dest_gprh(ctx, a->rd); 843 844 func(desth, src1h, src2h); 845 gen_set_gpr128(ctx, a->rd, dest, desth); 846 } else { 847 gen_set_gpr(ctx, a->rd, dest); 848 } 849 850 return true; 851 } 852 853 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 854 void (*func)(TCGv, TCGv, target_long), 855 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 856 { 857 TCGv dest = dest_gpr(ctx, a->rd); 858 TCGv src1 = get_gpr(ctx, a->rs1, ext); 859 860 if (get_ol(ctx) < MXL_RV128) { 861 func(dest, src1, a->imm); 862 gen_set_gpr(ctx, a->rd, dest); 863 } else { 864 if (f128 == NULL) { 865 return false; 866 } 867 868 TCGv src1h = get_gprh(ctx, a->rs1); 869 TCGv desth = dest_gprh(ctx, a->rd); 870 871 f128(dest, desth, src1, src1h, a->imm); 872 gen_set_gpr128(ctx, a->rd, dest, desth); 873 } 874 return true; 875 } 876 877 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 878 void (*func)(TCGv, TCGv, TCGv), 879 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 880 { 881 TCGv dest = dest_gpr(ctx, a->rd); 882 TCGv src1 = get_gpr(ctx, a->rs1, ext); 883 TCGv src2 = tcg_constant_tl(a->imm); 884 885 if (get_ol(ctx) < MXL_RV128) { 886 func(dest, src1, src2); 887 gen_set_gpr(ctx, a->rd, dest); 888 } else { 889 if (f128 == NULL) { 890 return false; 891 } 892 893 TCGv src1h = get_gprh(ctx, a->rs1); 894 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 895 TCGv desth = dest_gprh(ctx, a->rd); 896 897 f128(dest, desth, src1, src1h, src2, src2h); 898 gen_set_gpr128(ctx, a->rd, dest, desth); 899 } 900 return true; 901 } 902 903 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 904 void (*func)(TCGv, TCGv, TCGv), 905 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 906 { 907 TCGv dest = dest_gpr(ctx, a->rd); 908 TCGv src1 = get_gpr(ctx, a->rs1, ext); 909 TCGv src2 = get_gpr(ctx, a->rs2, ext); 910 911 if (get_ol(ctx) < MXL_RV128) { 912 func(dest, src1, src2); 913 gen_set_gpr(ctx, a->rd, dest); 914 } else { 915 if (f128 == NULL) { 916 return false; 917 } 918 919 TCGv src1h = get_gprh(ctx, a->rs1); 920 TCGv src2h = get_gprh(ctx, a->rs2); 921 TCGv desth = dest_gprh(ctx, a->rd); 922 923 f128(dest, desth, src1, src1h, src2, src2h); 924 gen_set_gpr128(ctx, a->rd, dest, desth); 925 } 926 return true; 927 } 928 929 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 930 void (*f_tl)(TCGv, TCGv, TCGv), 931 void (*f_32)(TCGv, TCGv, TCGv), 932 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 933 { 934 int olen = get_olen(ctx); 935 936 if (olen != TARGET_LONG_BITS) { 937 if (olen == 32) { 938 f_tl = f_32; 939 } else if (olen != 128) { 940 g_assert_not_reached(); 941 } 942 } 943 return gen_arith(ctx, a, ext, f_tl, f_128); 944 } 945 946 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 947 void (*func)(TCGv, TCGv, target_long), 948 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 949 { 950 TCGv dest, src1; 951 int max_len = get_olen(ctx); 952 953 if (a->shamt >= max_len) { 954 return false; 955 } 956 957 dest = dest_gpr(ctx, a->rd); 958 src1 = get_gpr(ctx, a->rs1, ext); 959 960 if (max_len < 128) { 961 func(dest, src1, a->shamt); 962 gen_set_gpr(ctx, a->rd, dest); 963 } else { 964 TCGv src1h = get_gprh(ctx, a->rs1); 965 TCGv desth = dest_gprh(ctx, a->rd); 966 967 if (f128 == NULL) { 968 return false; 969 } 970 f128(dest, desth, src1, src1h, a->shamt); 971 gen_set_gpr128(ctx, a->rd, dest, desth); 972 } 973 return true; 974 } 975 976 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 977 DisasExtend ext, 978 void (*f_tl)(TCGv, TCGv, target_long), 979 void (*f_32)(TCGv, TCGv, target_long), 980 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 981 target_long)) 982 { 983 int olen = get_olen(ctx); 984 if (olen != TARGET_LONG_BITS) { 985 if (olen == 32) { 986 f_tl = f_32; 987 } else if (olen != 128) { 988 g_assert_not_reached(); 989 } 990 } 991 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 992 } 993 994 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 995 void (*func)(TCGv, TCGv, TCGv)) 996 { 997 TCGv dest, src1, src2; 998 int max_len = get_olen(ctx); 999 1000 if (a->shamt >= max_len) { 1001 return false; 1002 } 1003 1004 dest = dest_gpr(ctx, a->rd); 1005 src1 = get_gpr(ctx, a->rs1, ext); 1006 src2 = tcg_constant_tl(a->shamt); 1007 1008 func(dest, src1, src2); 1009 1010 gen_set_gpr(ctx, a->rd, dest); 1011 return true; 1012 } 1013 1014 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 1015 void (*func)(TCGv, TCGv, TCGv), 1016 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1017 { 1018 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1019 TCGv ext2 = tcg_temp_new(); 1020 int max_len = get_olen(ctx); 1021 1022 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1023 1024 TCGv dest = dest_gpr(ctx, a->rd); 1025 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1026 1027 if (max_len < 128) { 1028 func(dest, src1, ext2); 1029 gen_set_gpr(ctx, a->rd, dest); 1030 } else { 1031 TCGv src1h = get_gprh(ctx, a->rs1); 1032 TCGv desth = dest_gprh(ctx, a->rd); 1033 1034 if (f128 == NULL) { 1035 return false; 1036 } 1037 f128(dest, desth, src1, src1h, ext2); 1038 gen_set_gpr128(ctx, a->rd, dest, desth); 1039 } 1040 tcg_temp_free(ext2); 1041 return true; 1042 } 1043 1044 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1045 void (*f_tl)(TCGv, TCGv, TCGv), 1046 void (*f_32)(TCGv, TCGv, TCGv), 1047 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1048 { 1049 int olen = get_olen(ctx); 1050 if (olen != TARGET_LONG_BITS) { 1051 if (olen == 32) { 1052 f_tl = f_32; 1053 } else if (olen != 128) { 1054 g_assert_not_reached(); 1055 } 1056 } 1057 return gen_shift(ctx, a, ext, f_tl, f_128); 1058 } 1059 1060 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1061 void (*func)(TCGv, TCGv)) 1062 { 1063 TCGv dest = dest_gpr(ctx, a->rd); 1064 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1065 1066 func(dest, src1); 1067 1068 gen_set_gpr(ctx, a->rd, dest); 1069 return true; 1070 } 1071 1072 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1073 void (*f_tl)(TCGv, TCGv), 1074 void (*f_32)(TCGv, TCGv)) 1075 { 1076 int olen = get_olen(ctx); 1077 1078 if (olen != TARGET_LONG_BITS) { 1079 if (olen == 32) { 1080 f_tl = f_32; 1081 } else { 1082 g_assert_not_reached(); 1083 } 1084 } 1085 return gen_unary(ctx, a, ext, f_tl); 1086 } 1087 1088 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1089 { 1090 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1091 CPUState *cpu = ctx->cs; 1092 CPURISCVState *env = cpu->env_ptr; 1093 1094 return cpu_ldl_code(env, pc); 1095 } 1096 1097 /* Include insn module translation function */ 1098 #include "insn_trans/trans_rvi.c.inc" 1099 #include "insn_trans/trans_rvm.c.inc" 1100 #include "insn_trans/trans_rva.c.inc" 1101 #include "insn_trans/trans_rvf.c.inc" 1102 #include "insn_trans/trans_rvd.c.inc" 1103 #include "insn_trans/trans_rvh.c.inc" 1104 #include "insn_trans/trans_rvv.c.inc" 1105 #include "insn_trans/trans_rvb.c.inc" 1106 #include "insn_trans/trans_rvzawrs.c.inc" 1107 #include "insn_trans/trans_rvzfh.c.inc" 1108 #include "insn_trans/trans_rvk.c.inc" 1109 #include "insn_trans/trans_privileged.c.inc" 1110 #include "insn_trans/trans_svinval.c.inc" 1111 #include "decode-xthead.c.inc" 1112 #include "insn_trans/trans_xthead.c.inc" 1113 #include "insn_trans/trans_xventanacondops.c.inc" 1114 1115 /* Include the auto-generated decoder for 16 bit insn */ 1116 #include "decode-insn16.c.inc" 1117 /* Include decoders for factored-out extensions */ 1118 #include "decode-XVentanaCondOps.c.inc" 1119 1120 /* The specification allows for longer insns, but not supported by qemu. */ 1121 #define MAX_INSN_LEN 4 1122 1123 static inline int insn_len(uint16_t first_word) 1124 { 1125 return (first_word & 3) == 3 ? 4 : 2; 1126 } 1127 1128 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1129 { 1130 /* 1131 * A table with predicate (i.e., guard) functions and decoder functions 1132 * that are tested in-order until a decoder matches onto the opcode. 1133 */ 1134 static const struct { 1135 bool (*guard_func)(DisasContext *); 1136 bool (*decode_func)(DisasContext *, uint32_t); 1137 } decoders[] = { 1138 { always_true_p, decode_insn32 }, 1139 { has_xthead_p, decode_xthead }, 1140 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1141 }; 1142 1143 ctx->virt_inst_excp = false; 1144 /* Check for compressed insn */ 1145 if (insn_len(opcode) == 2) { 1146 ctx->opcode = opcode; 1147 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1148 if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) { 1149 return; 1150 } 1151 } else { 1152 uint32_t opcode32 = opcode; 1153 opcode32 = deposit32(opcode32, 16, 16, 1154 translator_lduw(env, &ctx->base, 1155 ctx->base.pc_next + 2)); 1156 ctx->opcode = opcode32; 1157 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1158 1159 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1160 if (decoders[i].guard_func(ctx) && 1161 decoders[i].decode_func(ctx, opcode32)) { 1162 return; 1163 } 1164 } 1165 } 1166 1167 gen_exception_illegal(ctx); 1168 } 1169 1170 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1171 { 1172 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1173 CPURISCVState *env = cs->env_ptr; 1174 RISCVCPU *cpu = RISCV_CPU(cs); 1175 uint32_t tb_flags = ctx->base.tb->flags; 1176 1177 ctx->pc_succ_insn = ctx->base.pc_first; 1178 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1179 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1180 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1181 ctx->priv_ver = env->priv_ver; 1182 #if !defined(CONFIG_USER_ONLY) 1183 if (riscv_has_ext(env, RVH)) { 1184 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1185 } else { 1186 ctx->virt_enabled = false; 1187 } 1188 #else 1189 ctx->virt_enabled = false; 1190 #endif 1191 ctx->misa_ext = env->misa_ext; 1192 ctx->frm = -1; /* unknown rounding mode */ 1193 ctx->cfg_ptr = &(cpu->cfg); 1194 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1195 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1196 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1197 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1198 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1199 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1200 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1201 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1202 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1203 ctx->vstart = env->vstart; 1204 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1205 ctx->misa_mxl_max = env->misa_mxl_max; 1206 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1207 ctx->cs = cs; 1208 ctx->ntemp = 0; 1209 memset(ctx->temp, 0, sizeof(ctx->temp)); 1210 ctx->nftemp = 0; 1211 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1212 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1213 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1214 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1215 ctx->zero = tcg_constant_tl(0); 1216 ctx->virt_inst_excp = false; 1217 } 1218 1219 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1220 { 1221 } 1222 1223 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1224 { 1225 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1226 1227 tcg_gen_insn_start(ctx->base.pc_next, 0); 1228 ctx->insn_start = tcg_last_op(); 1229 } 1230 1231 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1232 { 1233 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1234 CPURISCVState *env = cpu->env_ptr; 1235 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1236 int i; 1237 1238 ctx->ol = ctx->xl; 1239 decode_opc(env, ctx, opcode16); 1240 ctx->base.pc_next = ctx->pc_succ_insn; 1241 1242 for (i = ctx->ntemp - 1; i >= 0; --i) { 1243 tcg_temp_free(ctx->temp[i]); 1244 ctx->temp[i] = NULL; 1245 } 1246 ctx->ntemp = 0; 1247 for (i = ctx->nftemp - 1; i >= 0; --i) { 1248 tcg_temp_free_i64(ctx->ftemp[i]); 1249 ctx->ftemp[i] = NULL; 1250 } 1251 ctx->nftemp = 0; 1252 1253 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1254 if (ctx->base.is_jmp == DISAS_NEXT) { 1255 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1256 ctx->base.is_jmp = DISAS_TOO_MANY; 1257 } else { 1258 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1259 1260 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1261 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1262 int len = insn_len(next_insn); 1263 1264 if (!is_same_page(&ctx->base, ctx->base.pc_next + len)) { 1265 ctx->base.is_jmp = DISAS_TOO_MANY; 1266 } 1267 } 1268 } 1269 } 1270 } 1271 1272 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1273 { 1274 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1275 1276 switch (ctx->base.is_jmp) { 1277 case DISAS_TOO_MANY: 1278 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1279 break; 1280 case DISAS_NORETURN: 1281 break; 1282 default: 1283 g_assert_not_reached(); 1284 } 1285 } 1286 1287 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1288 CPUState *cpu, FILE *logfile) 1289 { 1290 #ifndef CONFIG_USER_ONLY 1291 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1292 CPURISCVState *env = &rvcpu->env; 1293 #endif 1294 1295 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1296 #ifndef CONFIG_USER_ONLY 1297 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1298 env->priv, env->virt); 1299 #endif 1300 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1301 } 1302 1303 static const TranslatorOps riscv_tr_ops = { 1304 .init_disas_context = riscv_tr_init_disas_context, 1305 .tb_start = riscv_tr_tb_start, 1306 .insn_start = riscv_tr_insn_start, 1307 .translate_insn = riscv_tr_translate_insn, 1308 .tb_stop = riscv_tr_tb_stop, 1309 .disas_log = riscv_tr_disas_log, 1310 }; 1311 1312 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 1313 target_ulong pc, void *host_pc) 1314 { 1315 DisasContext ctx; 1316 1317 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1318 } 1319 1320 void riscv_translate_init(void) 1321 { 1322 int i; 1323 1324 /* 1325 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1326 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1327 * unless you specifically block reads/writes to reg 0. 1328 */ 1329 cpu_gpr[0] = NULL; 1330 cpu_gprh[0] = NULL; 1331 1332 for (i = 1; i < 32; i++) { 1333 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1334 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1335 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1336 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1337 } 1338 1339 for (i = 0; i < 32; i++) { 1340 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1341 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1342 } 1343 1344 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1345 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1346 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1347 "vstart"); 1348 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1349 "load_res"); 1350 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1351 "load_val"); 1352 /* Assign PM CSRs to tcg globals */ 1353 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1354 "pmmask"); 1355 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1356 "pmbase"); 1357 } 1358