1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 /* global register indices */ 37 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 38 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 39 static TCGv load_res; 40 static TCGv load_val; 41 /* globals for PM CSRs */ 42 static TCGv pm_mask; 43 static TCGv pm_base; 44 45 #include "exec/gen-icount.h" 46 47 /* 48 * If an operation is being performed on less than TARGET_LONG_BITS, 49 * it may require the inputs to be sign- or zero-extended; which will 50 * depend on the exact operation being performed. 51 */ 52 typedef enum { 53 EXT_NONE, 54 EXT_SIGN, 55 EXT_ZERO, 56 } DisasExtend; 57 58 typedef struct DisasContext { 59 DisasContextBase base; 60 /* pc_succ_insn points to the instruction following base.pc_next */ 61 target_ulong pc_succ_insn; 62 target_ulong priv_ver; 63 RISCVMXL misa_mxl_max; 64 RISCVMXL xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 RISCVExtStatus mstatus_fs; 68 RISCVExtStatus mstatus_vs; 69 uint32_t mem_idx; 70 uint32_t priv; 71 /* 72 * Remember the rounding mode encoded in the previous fp instruction, 73 * which we have already installed into env->fp_status. Or -1 for 74 * no previous fp instruction. Note that we exit the TB when writing 75 * to any system register, which includes CSR_FRM, so we do not have 76 * to reset this known value. 77 */ 78 int frm; 79 RISCVMXL ol; 80 bool virt_inst_excp; 81 bool virt_enabled; 82 const RISCVCPUConfig *cfg_ptr; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint8_t vta; 100 uint8_t vma; 101 bool cfg_vta_all_1s; 102 bool vstart_eq_zero; 103 bool vl_eq_vlmax; 104 CPUState *cs; 105 TCGv zero; 106 /* PointerMasking extension */ 107 bool pm_mask_enabled; 108 bool pm_base_enabled; 109 /* Use icount trigger for native debug */ 110 bool itrigger; 111 /* FRM is known to contain a valid value. */ 112 bool frm_valid; 113 /* TCG of the current insn_start */ 114 TCGOp *insn_start; 115 } DisasContext; 116 117 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 118 { 119 return ctx->misa_ext & ext; 120 } 121 122 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 123 { 124 return true; 125 } 126 127 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) 128 { 129 return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || 130 ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || 131 ctx->cfg_ptr->ext_xtheadcondmov || 132 ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || 133 ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || 134 ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; 135 } 136 137 #define MATERIALISE_EXT_PREDICATE(ext) \ 138 static bool has_ ## ext ## _p(DisasContext *ctx) \ 139 { \ 140 return ctx->cfg_ptr->ext_ ## ext ; \ 141 } 142 143 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 144 145 #ifdef TARGET_RISCV32 146 #define get_xl(ctx) MXL_RV32 147 #elif defined(CONFIG_USER_ONLY) 148 #define get_xl(ctx) MXL_RV64 149 #else 150 #define get_xl(ctx) ((ctx)->xl) 151 #endif 152 153 /* The word size for this machine mode. */ 154 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 155 { 156 return 16 << get_xl(ctx); 157 } 158 159 /* The operation length, as opposed to the xlen. */ 160 #ifdef TARGET_RISCV32 161 #define get_ol(ctx) MXL_RV32 162 #else 163 #define get_ol(ctx) ((ctx)->ol) 164 #endif 165 166 static inline int get_olen(DisasContext *ctx) 167 { 168 return 16 << get_ol(ctx); 169 } 170 171 /* The maximum register length */ 172 #ifdef TARGET_RISCV32 173 #define get_xl_max(ctx) MXL_RV32 174 #else 175 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 176 #endif 177 178 /* 179 * RISC-V requires NaN-boxing of narrower width floating point values. 180 * This applies when a 32-bit value is assigned to a 64-bit FP register. 181 * For consistency and simplicity, we nanbox results even when the RVD 182 * extension is not present. 183 */ 184 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 185 { 186 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 187 } 188 189 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 190 { 191 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 192 } 193 194 /* 195 * A narrow n-bit operation, where n < FLEN, checks that input operands 196 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 197 * If so, the least-significant bits of the input are used, otherwise the 198 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 199 * 200 * Here, the result is always nan-boxed, even the canonical nan. 201 */ 202 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 203 { 204 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 205 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 206 207 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 208 } 209 210 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 211 { 212 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 213 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 214 215 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 216 } 217 218 static void decode_save_opc(DisasContext *ctx) 219 { 220 assert(ctx->insn_start != NULL); 221 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 222 ctx->insn_start = NULL; 223 } 224 225 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 226 { 227 if (get_xl(ctx) == MXL_RV32) { 228 dest = (int32_t)dest; 229 } 230 tcg_gen_movi_tl(cpu_pc, dest); 231 } 232 233 static void gen_set_pc(DisasContext *ctx, TCGv dest) 234 { 235 if (get_xl(ctx) == MXL_RV32) { 236 tcg_gen_ext32s_tl(cpu_pc, dest); 237 } else { 238 tcg_gen_mov_tl(cpu_pc, dest); 239 } 240 } 241 242 static void generate_exception(DisasContext *ctx, int excp) 243 { 244 gen_set_pc_imm(ctx, ctx->base.pc_next); 245 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 246 ctx->base.is_jmp = DISAS_NORETURN; 247 } 248 249 static void gen_exception_illegal(DisasContext *ctx) 250 { 251 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 252 offsetof(CPURISCVState, bins)); 253 if (ctx->virt_inst_excp) { 254 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 255 } else { 256 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 257 } 258 } 259 260 static void gen_exception_inst_addr_mis(DisasContext *ctx) 261 { 262 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 263 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 264 } 265 266 static void lookup_and_goto_ptr(DisasContext *ctx) 267 { 268 #ifndef CONFIG_USER_ONLY 269 if (ctx->itrigger) { 270 gen_helper_itrigger_match(cpu_env); 271 } 272 #endif 273 tcg_gen_lookup_and_goto_ptr(); 274 } 275 276 static void exit_tb(DisasContext *ctx) 277 { 278 #ifndef CONFIG_USER_ONLY 279 if (ctx->itrigger) { 280 gen_helper_itrigger_match(cpu_env); 281 } 282 #endif 283 tcg_gen_exit_tb(NULL, 0); 284 } 285 286 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 287 { 288 /* 289 * Under itrigger, instruction executes one by one like singlestep, 290 * direct block chain benefits will be small. 291 */ 292 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 293 tcg_gen_goto_tb(n); 294 gen_set_pc_imm(ctx, dest); 295 tcg_gen_exit_tb(ctx->base.tb, n); 296 } else { 297 gen_set_pc_imm(ctx, dest); 298 lookup_and_goto_ptr(ctx); 299 } 300 } 301 302 /* 303 * Wrappers for getting reg values. 304 * 305 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 306 * constant zero as a source, and an uninitialized sink as destination. 307 * 308 * Further, we may provide an extension for word operations. 309 */ 310 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 311 { 312 TCGv t; 313 314 if (reg_num == 0) { 315 return ctx->zero; 316 } 317 318 switch (get_ol(ctx)) { 319 case MXL_RV32: 320 switch (ext) { 321 case EXT_NONE: 322 break; 323 case EXT_SIGN: 324 t = tcg_temp_new(); 325 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 326 return t; 327 case EXT_ZERO: 328 t = tcg_temp_new(); 329 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 330 return t; 331 default: 332 g_assert_not_reached(); 333 } 334 break; 335 case MXL_RV64: 336 case MXL_RV128: 337 break; 338 default: 339 g_assert_not_reached(); 340 } 341 return cpu_gpr[reg_num]; 342 } 343 344 static TCGv get_gprh(DisasContext *ctx, int reg_num) 345 { 346 assert(get_xl(ctx) == MXL_RV128); 347 if (reg_num == 0) { 348 return ctx->zero; 349 } 350 return cpu_gprh[reg_num]; 351 } 352 353 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 354 { 355 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 356 return tcg_temp_new(); 357 } 358 return cpu_gpr[reg_num]; 359 } 360 361 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 362 { 363 if (reg_num == 0) { 364 return tcg_temp_new(); 365 } 366 return cpu_gprh[reg_num]; 367 } 368 369 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 370 { 371 if (reg_num != 0) { 372 switch (get_ol(ctx)) { 373 case MXL_RV32: 374 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 375 break; 376 case MXL_RV64: 377 case MXL_RV128: 378 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 379 break; 380 default: 381 g_assert_not_reached(); 382 } 383 384 if (get_xl_max(ctx) == MXL_RV128) { 385 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 386 } 387 } 388 } 389 390 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 391 { 392 if (reg_num != 0) { 393 switch (get_ol(ctx)) { 394 case MXL_RV32: 395 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 396 break; 397 case MXL_RV64: 398 case MXL_RV128: 399 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 400 break; 401 default: 402 g_assert_not_reached(); 403 } 404 405 if (get_xl_max(ctx) == MXL_RV128) { 406 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 407 } 408 } 409 } 410 411 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 412 { 413 assert(get_ol(ctx) == MXL_RV128); 414 if (reg_num != 0) { 415 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 416 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 417 } 418 } 419 420 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 421 { 422 if (!ctx->cfg_ptr->ext_zfinx) { 423 return cpu_fpr[reg_num]; 424 } 425 426 if (reg_num == 0) { 427 return tcg_constant_i64(0); 428 } 429 switch (get_xl(ctx)) { 430 case MXL_RV32: 431 #ifdef TARGET_RISCV32 432 { 433 TCGv_i64 t = tcg_temp_new_i64(); 434 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 435 return t; 436 } 437 #else 438 /* fall through */ 439 case MXL_RV64: 440 return cpu_gpr[reg_num]; 441 #endif 442 default: 443 g_assert_not_reached(); 444 } 445 } 446 447 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 448 { 449 if (!ctx->cfg_ptr->ext_zfinx) { 450 return cpu_fpr[reg_num]; 451 } 452 453 if (reg_num == 0) { 454 return tcg_constant_i64(0); 455 } 456 switch (get_xl(ctx)) { 457 case MXL_RV32: 458 { 459 TCGv_i64 t = tcg_temp_new_i64(); 460 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 461 return t; 462 } 463 #ifdef TARGET_RISCV64 464 case MXL_RV64: 465 return cpu_gpr[reg_num]; 466 #endif 467 default: 468 g_assert_not_reached(); 469 } 470 } 471 472 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 473 { 474 if (!ctx->cfg_ptr->ext_zfinx) { 475 return cpu_fpr[reg_num]; 476 } 477 478 if (reg_num == 0) { 479 return tcg_temp_new_i64(); 480 } 481 482 switch (get_xl(ctx)) { 483 case MXL_RV32: 484 return tcg_temp_new_i64(); 485 #ifdef TARGET_RISCV64 486 case MXL_RV64: 487 return cpu_gpr[reg_num]; 488 #endif 489 default: 490 g_assert_not_reached(); 491 } 492 } 493 494 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 495 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 496 { 497 if (!ctx->cfg_ptr->ext_zfinx) { 498 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 499 return; 500 } 501 if (reg_num != 0) { 502 switch (get_xl(ctx)) { 503 case MXL_RV32: 504 #ifdef TARGET_RISCV32 505 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 506 break; 507 #else 508 /* fall through */ 509 case MXL_RV64: 510 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 511 break; 512 #endif 513 default: 514 g_assert_not_reached(); 515 } 516 } 517 } 518 519 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 520 { 521 if (!ctx->cfg_ptr->ext_zfinx) { 522 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 523 return; 524 } 525 526 if (reg_num != 0) { 527 switch (get_xl(ctx)) { 528 case MXL_RV32: 529 #ifdef TARGET_RISCV32 530 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 531 break; 532 #else 533 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 534 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 535 break; 536 case MXL_RV64: 537 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 538 break; 539 #endif 540 default: 541 g_assert_not_reached(); 542 } 543 } 544 } 545 546 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 547 { 548 target_ulong next_pc; 549 550 /* check misaligned: */ 551 next_pc = ctx->base.pc_next + imm; 552 if (!ctx->cfg_ptr->ext_zca) { 553 if ((next_pc & 0x3) != 0) { 554 gen_exception_inst_addr_mis(ctx); 555 return; 556 } 557 } 558 559 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 560 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 561 ctx->base.is_jmp = DISAS_NORETURN; 562 } 563 564 /* Compute a canonical address from a register plus offset. */ 565 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 566 { 567 TCGv addr = tcg_temp_new(); 568 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 569 570 tcg_gen_addi_tl(addr, src1, imm); 571 if (ctx->pm_mask_enabled) { 572 tcg_gen_andc_tl(addr, addr, pm_mask); 573 } else if (get_xl(ctx) == MXL_RV32) { 574 tcg_gen_ext32u_tl(addr, addr); 575 } 576 if (ctx->pm_base_enabled) { 577 tcg_gen_or_tl(addr, addr, pm_base); 578 } 579 return addr; 580 } 581 582 /* Compute a canonical address from a register plus reg offset. */ 583 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 584 { 585 TCGv addr = tcg_temp_new(); 586 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 587 588 tcg_gen_add_tl(addr, src1, offs); 589 if (ctx->pm_mask_enabled) { 590 tcg_gen_andc_tl(addr, addr, pm_mask); 591 } else if (get_xl(ctx) == MXL_RV32) { 592 tcg_gen_ext32u_tl(addr, addr); 593 } 594 if (ctx->pm_base_enabled) { 595 tcg_gen_or_tl(addr, addr, pm_base); 596 } 597 return addr; 598 } 599 600 #ifndef CONFIG_USER_ONLY 601 /* 602 * We will have already diagnosed disabled state, 603 * and need to turn initial/clean into dirty. 604 */ 605 static void mark_fs_dirty(DisasContext *ctx) 606 { 607 TCGv tmp; 608 609 if (!has_ext(ctx, RVF)) { 610 return; 611 } 612 613 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 614 /* Remember the state change for the rest of the TB. */ 615 ctx->mstatus_fs = EXT_STATUS_DIRTY; 616 617 tmp = tcg_temp_new(); 618 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 619 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 620 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 621 622 if (ctx->virt_enabled) { 623 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 624 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 625 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 626 } 627 } 628 } 629 #else 630 static inline void mark_fs_dirty(DisasContext *ctx) { } 631 #endif 632 633 #ifndef CONFIG_USER_ONLY 634 /* 635 * We will have already diagnosed disabled state, 636 * and need to turn initial/clean into dirty. 637 */ 638 static void mark_vs_dirty(DisasContext *ctx) 639 { 640 TCGv tmp; 641 642 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 643 /* Remember the state change for the rest of the TB. */ 644 ctx->mstatus_vs = EXT_STATUS_DIRTY; 645 646 tmp = tcg_temp_new(); 647 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 648 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 649 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 650 651 if (ctx->virt_enabled) { 652 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 653 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 654 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 655 } 656 } 657 } 658 #else 659 static inline void mark_vs_dirty(DisasContext *ctx) { } 660 #endif 661 662 static void gen_set_rm(DisasContext *ctx, int rm) 663 { 664 if (ctx->frm == rm) { 665 return; 666 } 667 ctx->frm = rm; 668 669 if (rm == RISCV_FRM_DYN) { 670 /* The helper will return only if frm valid. */ 671 ctx->frm_valid = true; 672 } 673 674 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 675 decode_save_opc(ctx); 676 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 677 } 678 679 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 680 { 681 if (ctx->frm == rm && ctx->frm_valid) { 682 return; 683 } 684 ctx->frm = rm; 685 ctx->frm_valid = true; 686 687 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 688 decode_save_opc(ctx); 689 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 690 } 691 692 static int ex_plus_1(DisasContext *ctx, int nf) 693 { 694 return nf + 1; 695 } 696 697 #define EX_SH(amount) \ 698 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 699 { \ 700 return imm << amount; \ 701 } 702 EX_SH(1) 703 EX_SH(2) 704 EX_SH(3) 705 EX_SH(4) 706 EX_SH(12) 707 708 #define REQUIRE_EXT(ctx, ext) do { \ 709 if (!has_ext(ctx, ext)) { \ 710 return false; \ 711 } \ 712 } while (0) 713 714 #define REQUIRE_32BIT(ctx) do { \ 715 if (get_xl(ctx) != MXL_RV32) { \ 716 return false; \ 717 } \ 718 } while (0) 719 720 #define REQUIRE_64BIT(ctx) do { \ 721 if (get_xl(ctx) != MXL_RV64) { \ 722 return false; \ 723 } \ 724 } while (0) 725 726 #define REQUIRE_128BIT(ctx) do { \ 727 if (get_xl(ctx) != MXL_RV128) { \ 728 return false; \ 729 } \ 730 } while (0) 731 732 #define REQUIRE_64_OR_128BIT(ctx) do { \ 733 if (get_xl(ctx) == MXL_RV32) { \ 734 return false; \ 735 } \ 736 } while (0) 737 738 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 739 if (!ctx->cfg_ptr->ext_##A && \ 740 !ctx->cfg_ptr->ext_##B) { \ 741 return false; \ 742 } \ 743 } while (0) 744 745 static int ex_rvc_register(DisasContext *ctx, int reg) 746 { 747 return 8 + reg; 748 } 749 750 static int ex_sreg_register(DisasContext *ctx, int reg) 751 { 752 return reg < 2 ? reg + 8 : reg + 16; 753 } 754 755 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 756 { 757 /* For RV128 a shamt of 0 means a shift by 64. */ 758 if (get_ol(ctx) == MXL_RV128) { 759 imm = imm ? imm : 64; 760 } 761 return imm; 762 } 763 764 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 765 { 766 /* 767 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 768 * shifts, the shamt is sign-extended. 769 */ 770 if (get_ol(ctx) == MXL_RV128) { 771 imm = imm | (imm & 32) << 1; 772 imm = imm ? imm : 64; 773 } 774 return imm; 775 } 776 777 /* Include the auto-generated decoder for 32 bit insn */ 778 #include "decode-insn32.c.inc" 779 780 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 781 void (*func)(TCGv, TCGv, target_long)) 782 { 783 TCGv dest = dest_gpr(ctx, a->rd); 784 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 785 786 func(dest, src1, a->imm); 787 788 if (get_xl(ctx) == MXL_RV128) { 789 TCGv src1h = get_gprh(ctx, a->rs1); 790 TCGv desth = dest_gprh(ctx, a->rd); 791 792 func(desth, src1h, -(a->imm < 0)); 793 gen_set_gpr128(ctx, a->rd, dest, desth); 794 } else { 795 gen_set_gpr(ctx, a->rd, dest); 796 } 797 798 return true; 799 } 800 801 static bool gen_logic(DisasContext *ctx, arg_r *a, 802 void (*func)(TCGv, TCGv, TCGv)) 803 { 804 TCGv dest = dest_gpr(ctx, a->rd); 805 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 806 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 807 808 func(dest, src1, src2); 809 810 if (get_xl(ctx) == MXL_RV128) { 811 TCGv src1h = get_gprh(ctx, a->rs1); 812 TCGv src2h = get_gprh(ctx, a->rs2); 813 TCGv desth = dest_gprh(ctx, a->rd); 814 815 func(desth, src1h, src2h); 816 gen_set_gpr128(ctx, a->rd, dest, desth); 817 } else { 818 gen_set_gpr(ctx, a->rd, dest); 819 } 820 821 return true; 822 } 823 824 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 825 void (*func)(TCGv, TCGv, target_long), 826 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 827 { 828 TCGv dest = dest_gpr(ctx, a->rd); 829 TCGv src1 = get_gpr(ctx, a->rs1, ext); 830 831 if (get_ol(ctx) < MXL_RV128) { 832 func(dest, src1, a->imm); 833 gen_set_gpr(ctx, a->rd, dest); 834 } else { 835 if (f128 == NULL) { 836 return false; 837 } 838 839 TCGv src1h = get_gprh(ctx, a->rs1); 840 TCGv desth = dest_gprh(ctx, a->rd); 841 842 f128(dest, desth, src1, src1h, a->imm); 843 gen_set_gpr128(ctx, a->rd, dest, desth); 844 } 845 return true; 846 } 847 848 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 849 void (*func)(TCGv, TCGv, TCGv), 850 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 851 { 852 TCGv dest = dest_gpr(ctx, a->rd); 853 TCGv src1 = get_gpr(ctx, a->rs1, ext); 854 TCGv src2 = tcg_constant_tl(a->imm); 855 856 if (get_ol(ctx) < MXL_RV128) { 857 func(dest, src1, src2); 858 gen_set_gpr(ctx, a->rd, dest); 859 } else { 860 if (f128 == NULL) { 861 return false; 862 } 863 864 TCGv src1h = get_gprh(ctx, a->rs1); 865 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 866 TCGv desth = dest_gprh(ctx, a->rd); 867 868 f128(dest, desth, src1, src1h, src2, src2h); 869 gen_set_gpr128(ctx, a->rd, dest, desth); 870 } 871 return true; 872 } 873 874 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 875 void (*func)(TCGv, TCGv, TCGv), 876 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 877 { 878 TCGv dest = dest_gpr(ctx, a->rd); 879 TCGv src1 = get_gpr(ctx, a->rs1, ext); 880 TCGv src2 = get_gpr(ctx, a->rs2, ext); 881 882 if (get_ol(ctx) < MXL_RV128) { 883 func(dest, src1, src2); 884 gen_set_gpr(ctx, a->rd, dest); 885 } else { 886 if (f128 == NULL) { 887 return false; 888 } 889 890 TCGv src1h = get_gprh(ctx, a->rs1); 891 TCGv src2h = get_gprh(ctx, a->rs2); 892 TCGv desth = dest_gprh(ctx, a->rd); 893 894 f128(dest, desth, src1, src1h, src2, src2h); 895 gen_set_gpr128(ctx, a->rd, dest, desth); 896 } 897 return true; 898 } 899 900 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 901 void (*f_tl)(TCGv, TCGv, TCGv), 902 void (*f_32)(TCGv, TCGv, TCGv), 903 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 904 { 905 int olen = get_olen(ctx); 906 907 if (olen != TARGET_LONG_BITS) { 908 if (olen == 32) { 909 f_tl = f_32; 910 } else if (olen != 128) { 911 g_assert_not_reached(); 912 } 913 } 914 return gen_arith(ctx, a, ext, f_tl, f_128); 915 } 916 917 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 918 void (*func)(TCGv, TCGv, target_long), 919 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 920 { 921 TCGv dest, src1; 922 int max_len = get_olen(ctx); 923 924 if (a->shamt >= max_len) { 925 return false; 926 } 927 928 dest = dest_gpr(ctx, a->rd); 929 src1 = get_gpr(ctx, a->rs1, ext); 930 931 if (max_len < 128) { 932 func(dest, src1, a->shamt); 933 gen_set_gpr(ctx, a->rd, dest); 934 } else { 935 TCGv src1h = get_gprh(ctx, a->rs1); 936 TCGv desth = dest_gprh(ctx, a->rd); 937 938 if (f128 == NULL) { 939 return false; 940 } 941 f128(dest, desth, src1, src1h, a->shamt); 942 gen_set_gpr128(ctx, a->rd, dest, desth); 943 } 944 return true; 945 } 946 947 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 948 DisasExtend ext, 949 void (*f_tl)(TCGv, TCGv, target_long), 950 void (*f_32)(TCGv, TCGv, target_long), 951 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 952 target_long)) 953 { 954 int olen = get_olen(ctx); 955 if (olen != TARGET_LONG_BITS) { 956 if (olen == 32) { 957 f_tl = f_32; 958 } else if (olen != 128) { 959 g_assert_not_reached(); 960 } 961 } 962 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 963 } 964 965 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 966 void (*func)(TCGv, TCGv, TCGv)) 967 { 968 TCGv dest, src1, src2; 969 int max_len = get_olen(ctx); 970 971 if (a->shamt >= max_len) { 972 return false; 973 } 974 975 dest = dest_gpr(ctx, a->rd); 976 src1 = get_gpr(ctx, a->rs1, ext); 977 src2 = tcg_constant_tl(a->shamt); 978 979 func(dest, src1, src2); 980 981 gen_set_gpr(ctx, a->rd, dest); 982 return true; 983 } 984 985 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 986 void (*func)(TCGv, TCGv, TCGv), 987 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 988 { 989 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 990 TCGv ext2 = tcg_temp_new(); 991 int max_len = get_olen(ctx); 992 993 tcg_gen_andi_tl(ext2, src2, max_len - 1); 994 995 TCGv dest = dest_gpr(ctx, a->rd); 996 TCGv src1 = get_gpr(ctx, a->rs1, ext); 997 998 if (max_len < 128) { 999 func(dest, src1, ext2); 1000 gen_set_gpr(ctx, a->rd, dest); 1001 } else { 1002 TCGv src1h = get_gprh(ctx, a->rs1); 1003 TCGv desth = dest_gprh(ctx, a->rd); 1004 1005 if (f128 == NULL) { 1006 return false; 1007 } 1008 f128(dest, desth, src1, src1h, ext2); 1009 gen_set_gpr128(ctx, a->rd, dest, desth); 1010 } 1011 return true; 1012 } 1013 1014 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1015 void (*f_tl)(TCGv, TCGv, TCGv), 1016 void (*f_32)(TCGv, TCGv, TCGv), 1017 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1018 { 1019 int olen = get_olen(ctx); 1020 if (olen != TARGET_LONG_BITS) { 1021 if (olen == 32) { 1022 f_tl = f_32; 1023 } else if (olen != 128) { 1024 g_assert_not_reached(); 1025 } 1026 } 1027 return gen_shift(ctx, a, ext, f_tl, f_128); 1028 } 1029 1030 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1031 void (*func)(TCGv, TCGv)) 1032 { 1033 TCGv dest = dest_gpr(ctx, a->rd); 1034 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1035 1036 func(dest, src1); 1037 1038 gen_set_gpr(ctx, a->rd, dest); 1039 return true; 1040 } 1041 1042 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1043 void (*f_tl)(TCGv, TCGv), 1044 void (*f_32)(TCGv, TCGv)) 1045 { 1046 int olen = get_olen(ctx); 1047 1048 if (olen != TARGET_LONG_BITS) { 1049 if (olen == 32) { 1050 f_tl = f_32; 1051 } else { 1052 g_assert_not_reached(); 1053 } 1054 } 1055 return gen_unary(ctx, a, ext, f_tl); 1056 } 1057 1058 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1059 { 1060 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1061 CPUState *cpu = ctx->cs; 1062 CPURISCVState *env = cpu->env_ptr; 1063 1064 return cpu_ldl_code(env, pc); 1065 } 1066 1067 /* Include insn module translation function */ 1068 #include "insn_trans/trans_rvi.c.inc" 1069 #include "insn_trans/trans_rvm.c.inc" 1070 #include "insn_trans/trans_rva.c.inc" 1071 #include "insn_trans/trans_rvf.c.inc" 1072 #include "insn_trans/trans_rvd.c.inc" 1073 #include "insn_trans/trans_rvh.c.inc" 1074 #include "insn_trans/trans_rvv.c.inc" 1075 #include "insn_trans/trans_rvb.c.inc" 1076 #include "insn_trans/trans_rvzicond.c.inc" 1077 #include "insn_trans/trans_rvzawrs.c.inc" 1078 #include "insn_trans/trans_rvzicbo.c.inc" 1079 #include "insn_trans/trans_rvzfh.c.inc" 1080 #include "insn_trans/trans_rvk.c.inc" 1081 #include "insn_trans/trans_privileged.c.inc" 1082 #include "insn_trans/trans_svinval.c.inc" 1083 #include "decode-xthead.c.inc" 1084 #include "insn_trans/trans_xthead.c.inc" 1085 #include "insn_trans/trans_xventanacondops.c.inc" 1086 1087 /* Include the auto-generated decoder for 16 bit insn */ 1088 #include "decode-insn16.c.inc" 1089 #include "insn_trans/trans_rvzce.c.inc" 1090 1091 /* Include decoders for factored-out extensions */ 1092 #include "decode-XVentanaCondOps.c.inc" 1093 1094 /* The specification allows for longer insns, but not supported by qemu. */ 1095 #define MAX_INSN_LEN 4 1096 1097 static inline int insn_len(uint16_t first_word) 1098 { 1099 return (first_word & 3) == 3 ? 4 : 2; 1100 } 1101 1102 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1103 { 1104 /* 1105 * A table with predicate (i.e., guard) functions and decoder functions 1106 * that are tested in-order until a decoder matches onto the opcode. 1107 */ 1108 static const struct { 1109 bool (*guard_func)(DisasContext *); 1110 bool (*decode_func)(DisasContext *, uint32_t); 1111 } decoders[] = { 1112 { always_true_p, decode_insn32 }, 1113 { has_xthead_p, decode_xthead }, 1114 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1115 }; 1116 1117 ctx->virt_inst_excp = false; 1118 /* Check for compressed insn */ 1119 if (insn_len(opcode) == 2) { 1120 ctx->opcode = opcode; 1121 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1122 /* 1123 * The Zca extension is added as way to refer to instructions in the C 1124 * extension that do not include the floating-point loads and stores 1125 */ 1126 if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) { 1127 return; 1128 } 1129 } else { 1130 uint32_t opcode32 = opcode; 1131 opcode32 = deposit32(opcode32, 16, 16, 1132 translator_lduw(env, &ctx->base, 1133 ctx->base.pc_next + 2)); 1134 ctx->opcode = opcode32; 1135 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1136 1137 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1138 if (decoders[i].guard_func(ctx) && 1139 decoders[i].decode_func(ctx, opcode32)) { 1140 return; 1141 } 1142 } 1143 } 1144 1145 gen_exception_illegal(ctx); 1146 } 1147 1148 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1149 { 1150 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1151 CPURISCVState *env = cs->env_ptr; 1152 RISCVCPU *cpu = RISCV_CPU(cs); 1153 uint32_t tb_flags = ctx->base.tb->flags; 1154 1155 ctx->pc_succ_insn = ctx->base.pc_first; 1156 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1157 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1158 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1159 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1160 ctx->priv_ver = env->priv_ver; 1161 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1162 ctx->misa_ext = env->misa_ext; 1163 ctx->frm = -1; /* unknown rounding mode */ 1164 ctx->cfg_ptr = &(cpu->cfg); 1165 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1166 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1167 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1168 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1169 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1170 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1171 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1172 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1173 ctx->misa_mxl_max = env->misa_mxl_max; 1174 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1175 ctx->cs = cs; 1176 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1177 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1178 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1179 ctx->zero = tcg_constant_tl(0); 1180 ctx->virt_inst_excp = false; 1181 } 1182 1183 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1184 { 1185 } 1186 1187 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1188 { 1189 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1190 1191 tcg_gen_insn_start(ctx->base.pc_next, 0); 1192 ctx->insn_start = tcg_last_op(); 1193 } 1194 1195 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1196 { 1197 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1198 CPURISCVState *env = cpu->env_ptr; 1199 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1200 1201 ctx->ol = ctx->xl; 1202 decode_opc(env, ctx, opcode16); 1203 ctx->base.pc_next = ctx->pc_succ_insn; 1204 1205 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1206 if (ctx->base.is_jmp == DISAS_NEXT) { 1207 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1208 ctx->base.is_jmp = DISAS_TOO_MANY; 1209 } else { 1210 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1211 1212 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1213 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1214 int len = insn_len(next_insn); 1215 1216 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1217 ctx->base.is_jmp = DISAS_TOO_MANY; 1218 } 1219 } 1220 } 1221 } 1222 } 1223 1224 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1225 { 1226 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1227 1228 switch (ctx->base.is_jmp) { 1229 case DISAS_TOO_MANY: 1230 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1231 break; 1232 case DISAS_NORETURN: 1233 break; 1234 default: 1235 g_assert_not_reached(); 1236 } 1237 } 1238 1239 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1240 CPUState *cpu, FILE *logfile) 1241 { 1242 #ifndef CONFIG_USER_ONLY 1243 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1244 CPURISCVState *env = &rvcpu->env; 1245 #endif 1246 1247 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1248 #ifndef CONFIG_USER_ONLY 1249 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n", 1250 env->priv, env->virt_enabled); 1251 #endif 1252 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1253 } 1254 1255 static const TranslatorOps riscv_tr_ops = { 1256 .init_disas_context = riscv_tr_init_disas_context, 1257 .tb_start = riscv_tr_tb_start, 1258 .insn_start = riscv_tr_insn_start, 1259 .translate_insn = riscv_tr_translate_insn, 1260 .tb_stop = riscv_tr_tb_stop, 1261 .disas_log = riscv_tr_disas_log, 1262 }; 1263 1264 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1265 target_ulong pc, void *host_pc) 1266 { 1267 DisasContext ctx; 1268 1269 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1270 } 1271 1272 void riscv_translate_init(void) 1273 { 1274 int i; 1275 1276 /* 1277 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1278 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1279 * unless you specifically block reads/writes to reg 0. 1280 */ 1281 cpu_gpr[0] = NULL; 1282 cpu_gprh[0] = NULL; 1283 1284 for (i = 1; i < 32; i++) { 1285 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1286 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1287 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1288 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1289 } 1290 1291 for (i = 0; i < 32; i++) { 1292 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1293 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1294 } 1295 1296 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1297 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1298 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1299 "vstart"); 1300 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1301 "load_res"); 1302 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1303 "load_val"); 1304 /* Assign PM CSRs to tcg globals */ 1305 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1306 "pmmask"); 1307 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1308 "pmbase"); 1309 } 1310