1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 bool ext_ifencei; 80 bool ext_zfh; 81 bool ext_zfhmin; 82 bool ext_zve32f; 83 bool ext_zve64f; 84 bool hlsx; 85 /* vector extension */ 86 bool vill; 87 /* 88 * Encode LMUL to lmul as follows: 89 * LMUL vlmul lmul 90 * 1 000 0 91 * 2 001 1 92 * 4 010 2 93 * 8 011 3 94 * - 100 - 95 * 1/8 101 -3 96 * 1/4 110 -2 97 * 1/2 111 -1 98 */ 99 int8_t lmul; 100 uint8_t sew; 101 uint16_t vlen; 102 uint16_t elen; 103 target_ulong vstart; 104 bool vl_eq_vlmax; 105 uint8_t ntemp; 106 CPUState *cs; 107 TCGv zero; 108 /* Space for 3 operands plus 1 extra for address computation. */ 109 TCGv temp[4]; 110 /* PointerMasking extension */ 111 bool pm_enabled; 112 } DisasContext; 113 114 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 115 { 116 return ctx->misa_ext & ext; 117 } 118 119 #ifdef TARGET_RISCV32 120 #define get_xl(ctx) MXL_RV32 121 #elif defined(CONFIG_USER_ONLY) 122 #define get_xl(ctx) MXL_RV64 123 #else 124 #define get_xl(ctx) ((ctx)->xl) 125 #endif 126 127 /* The word size for this machine mode. */ 128 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 129 { 130 return 16 << get_xl(ctx); 131 } 132 133 /* The operation length, as opposed to the xlen. */ 134 #ifdef TARGET_RISCV32 135 #define get_ol(ctx) MXL_RV32 136 #else 137 #define get_ol(ctx) ((ctx)->ol) 138 #endif 139 140 static inline int get_olen(DisasContext *ctx) 141 { 142 return 16 << get_ol(ctx); 143 } 144 145 /* The maximum register length */ 146 #ifdef TARGET_RISCV32 147 #define get_xl_max(ctx) MXL_RV32 148 #else 149 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 150 #endif 151 152 /* 153 * RISC-V requires NaN-boxing of narrower width floating point values. 154 * This applies when a 32-bit value is assigned to a 64-bit FP register. 155 * For consistency and simplicity, we nanbox results even when the RVD 156 * extension is not present. 157 */ 158 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 159 { 160 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 161 } 162 163 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 164 { 165 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 166 } 167 168 /* 169 * A narrow n-bit operation, where n < FLEN, checks that input operands 170 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 171 * If so, the least-significant bits of the input are used, otherwise the 172 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 173 * 174 * Here, the result is always nan-boxed, even the canonical nan. 175 */ 176 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 177 { 178 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 179 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 180 181 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 182 tcg_temp_free_i64(t_max); 183 tcg_temp_free_i64(t_nan); 184 } 185 186 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 187 { 188 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 189 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 190 191 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 192 } 193 194 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 195 { 196 if (get_xl(ctx) == MXL_RV32) { 197 dest = (int32_t)dest; 198 } 199 tcg_gen_movi_tl(cpu_pc, dest); 200 } 201 202 static void gen_set_pc(DisasContext *ctx, TCGv dest) 203 { 204 if (get_xl(ctx) == MXL_RV32) { 205 tcg_gen_ext32s_tl(cpu_pc, dest); 206 } else { 207 tcg_gen_mov_tl(cpu_pc, dest); 208 } 209 } 210 211 static void generate_exception(DisasContext *ctx, int excp) 212 { 213 gen_set_pc_imm(ctx, ctx->base.pc_next); 214 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 215 ctx->base.is_jmp = DISAS_NORETURN; 216 } 217 218 static void generate_exception_mtval(DisasContext *ctx, int excp) 219 { 220 gen_set_pc_imm(ctx, ctx->base.pc_next); 221 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 222 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 223 ctx->base.is_jmp = DISAS_NORETURN; 224 } 225 226 static void gen_exception_illegal(DisasContext *ctx) 227 { 228 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 229 offsetof(CPURISCVState, bins)); 230 231 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 232 } 233 234 static void gen_exception_inst_addr_mis(DisasContext *ctx) 235 { 236 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 237 } 238 239 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 240 { 241 if (translator_use_goto_tb(&ctx->base, dest)) { 242 tcg_gen_goto_tb(n); 243 gen_set_pc_imm(ctx, dest); 244 tcg_gen_exit_tb(ctx->base.tb, n); 245 } else { 246 gen_set_pc_imm(ctx, dest); 247 tcg_gen_lookup_and_goto_ptr(); 248 } 249 } 250 251 /* 252 * Wrappers for getting reg values. 253 * 254 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 255 * constant zero as a source, and an uninitialized sink as destination. 256 * 257 * Further, we may provide an extension for word operations. 258 */ 259 static TCGv temp_new(DisasContext *ctx) 260 { 261 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 262 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 263 } 264 265 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 266 { 267 TCGv t; 268 269 if (reg_num == 0) { 270 return ctx->zero; 271 } 272 273 switch (get_ol(ctx)) { 274 case MXL_RV32: 275 switch (ext) { 276 case EXT_NONE: 277 break; 278 case EXT_SIGN: 279 t = temp_new(ctx); 280 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 281 return t; 282 case EXT_ZERO: 283 t = temp_new(ctx); 284 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 285 return t; 286 default: 287 g_assert_not_reached(); 288 } 289 break; 290 case MXL_RV64: 291 case MXL_RV128: 292 break; 293 default: 294 g_assert_not_reached(); 295 } 296 return cpu_gpr[reg_num]; 297 } 298 299 static TCGv get_gprh(DisasContext *ctx, int reg_num) 300 { 301 assert(get_xl(ctx) == MXL_RV128); 302 if (reg_num == 0) { 303 return ctx->zero; 304 } 305 return cpu_gprh[reg_num]; 306 } 307 308 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 309 { 310 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 311 return temp_new(ctx); 312 } 313 return cpu_gpr[reg_num]; 314 } 315 316 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 317 { 318 if (reg_num == 0) { 319 return temp_new(ctx); 320 } 321 return cpu_gprh[reg_num]; 322 } 323 324 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 325 { 326 if (reg_num != 0) { 327 switch (get_ol(ctx)) { 328 case MXL_RV32: 329 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 330 break; 331 case MXL_RV64: 332 case MXL_RV128: 333 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 334 break; 335 default: 336 g_assert_not_reached(); 337 } 338 339 if (get_xl_max(ctx) == MXL_RV128) { 340 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 341 } 342 } 343 } 344 345 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 346 { 347 if (reg_num != 0) { 348 switch (get_ol(ctx)) { 349 case MXL_RV32: 350 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 351 break; 352 case MXL_RV64: 353 case MXL_RV128: 354 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 355 break; 356 default: 357 g_assert_not_reached(); 358 } 359 360 if (get_xl_max(ctx) == MXL_RV128) { 361 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 362 } 363 } 364 } 365 366 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 367 { 368 assert(get_ol(ctx) == MXL_RV128); 369 if (reg_num != 0) { 370 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 371 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 372 } 373 } 374 375 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 376 { 377 target_ulong next_pc; 378 379 /* check misaligned: */ 380 next_pc = ctx->base.pc_next + imm; 381 if (!has_ext(ctx, RVC)) { 382 if ((next_pc & 0x3) != 0) { 383 gen_exception_inst_addr_mis(ctx); 384 return; 385 } 386 } 387 388 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 389 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 390 ctx->base.is_jmp = DISAS_NORETURN; 391 } 392 393 /* 394 * Generates address adjustment for PointerMasking 395 */ 396 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) 397 { 398 TCGv temp; 399 if (!s->pm_enabled) { 400 /* Load unmodified address */ 401 return src; 402 } else { 403 temp = temp_new(s); 404 tcg_gen_andc_tl(temp, src, pm_mask); 405 tcg_gen_or_tl(temp, temp, pm_base); 406 return temp; 407 } 408 } 409 410 #ifndef CONFIG_USER_ONLY 411 /* The states of mstatus_fs are: 412 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 413 * We will have already diagnosed disabled state, 414 * and need to turn initial/clean into dirty. 415 */ 416 static void mark_fs_dirty(DisasContext *ctx) 417 { 418 TCGv tmp; 419 420 if (ctx->mstatus_fs != MSTATUS_FS) { 421 /* Remember the state change for the rest of the TB. */ 422 ctx->mstatus_fs = MSTATUS_FS; 423 424 tmp = tcg_temp_new(); 425 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 426 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 427 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 428 tcg_temp_free(tmp); 429 } 430 431 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 432 /* Remember the stage change for the rest of the TB. */ 433 ctx->mstatus_hs_fs = MSTATUS_FS; 434 435 tmp = tcg_temp_new(); 436 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 437 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 438 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 439 tcg_temp_free(tmp); 440 } 441 } 442 #else 443 static inline void mark_fs_dirty(DisasContext *ctx) { } 444 #endif 445 446 #ifndef CONFIG_USER_ONLY 447 /* The states of mstatus_vs are: 448 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 449 * We will have already diagnosed disabled state, 450 * and need to turn initial/clean into dirty. 451 */ 452 static void mark_vs_dirty(DisasContext *ctx) 453 { 454 TCGv tmp; 455 456 if (ctx->mstatus_vs != MSTATUS_VS) { 457 /* Remember the state change for the rest of the TB. */ 458 ctx->mstatus_vs = MSTATUS_VS; 459 460 tmp = tcg_temp_new(); 461 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 462 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 463 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 464 tcg_temp_free(tmp); 465 } 466 467 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 468 /* Remember the stage change for the rest of the TB. */ 469 ctx->mstatus_hs_vs = MSTATUS_VS; 470 471 tmp = tcg_temp_new(); 472 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 473 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 474 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 475 tcg_temp_free(tmp); 476 } 477 } 478 #else 479 static inline void mark_vs_dirty(DisasContext *ctx) { } 480 #endif 481 482 static void gen_set_rm(DisasContext *ctx, int rm) 483 { 484 if (ctx->frm == rm) { 485 return; 486 } 487 ctx->frm = rm; 488 489 if (rm == RISCV_FRM_ROD) { 490 gen_helper_set_rod_rounding_mode(cpu_env); 491 return; 492 } 493 494 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 495 } 496 497 static int ex_plus_1(DisasContext *ctx, int nf) 498 { 499 return nf + 1; 500 } 501 502 #define EX_SH(amount) \ 503 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 504 { \ 505 return imm << amount; \ 506 } 507 EX_SH(1) 508 EX_SH(2) 509 EX_SH(3) 510 EX_SH(4) 511 EX_SH(12) 512 513 #define REQUIRE_EXT(ctx, ext) do { \ 514 if (!has_ext(ctx, ext)) { \ 515 return false; \ 516 } \ 517 } while (0) 518 519 #define REQUIRE_32BIT(ctx) do { \ 520 if (get_xl(ctx) != MXL_RV32) { \ 521 return false; \ 522 } \ 523 } while (0) 524 525 #define REQUIRE_64BIT(ctx) do { \ 526 if (get_xl(ctx) != MXL_RV64) { \ 527 return false; \ 528 } \ 529 } while (0) 530 531 #define REQUIRE_128BIT(ctx) do { \ 532 if (get_xl(ctx) != MXL_RV128) { \ 533 return false; \ 534 } \ 535 } while (0) 536 537 #define REQUIRE_64_OR_128BIT(ctx) do { \ 538 if (get_xl(ctx) == MXL_RV32) { \ 539 return false; \ 540 } \ 541 } while (0) 542 543 static int ex_rvc_register(DisasContext *ctx, int reg) 544 { 545 return 8 + reg; 546 } 547 548 static int ex_rvc_shifti(DisasContext *ctx, int imm) 549 { 550 /* For RV128 a shamt of 0 means a shift by 64. */ 551 return imm ? imm : 64; 552 } 553 554 /* Include the auto-generated decoder for 32 bit insn */ 555 #include "decode-insn32.c.inc" 556 557 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 558 void (*func)(TCGv, TCGv, target_long)) 559 { 560 TCGv dest = dest_gpr(ctx, a->rd); 561 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 562 563 func(dest, src1, a->imm); 564 565 if (get_xl(ctx) == MXL_RV128) { 566 TCGv src1h = get_gprh(ctx, a->rs1); 567 TCGv desth = dest_gprh(ctx, a->rd); 568 569 func(desth, src1h, -(a->imm < 0)); 570 gen_set_gpr128(ctx, a->rd, dest, desth); 571 } else { 572 gen_set_gpr(ctx, a->rd, dest); 573 } 574 575 return true; 576 } 577 578 static bool gen_logic(DisasContext *ctx, arg_r *a, 579 void (*func)(TCGv, TCGv, TCGv)) 580 { 581 TCGv dest = dest_gpr(ctx, a->rd); 582 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 583 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 584 585 func(dest, src1, src2); 586 587 if (get_xl(ctx) == MXL_RV128) { 588 TCGv src1h = get_gprh(ctx, a->rs1); 589 TCGv src2h = get_gprh(ctx, a->rs2); 590 TCGv desth = dest_gprh(ctx, a->rd); 591 592 func(desth, src1h, src2h); 593 gen_set_gpr128(ctx, a->rd, dest, desth); 594 } else { 595 gen_set_gpr(ctx, a->rd, dest); 596 } 597 598 return true; 599 } 600 601 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 602 void (*func)(TCGv, TCGv, target_long), 603 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 604 { 605 TCGv dest = dest_gpr(ctx, a->rd); 606 TCGv src1 = get_gpr(ctx, a->rs1, ext); 607 608 if (get_ol(ctx) < MXL_RV128) { 609 func(dest, src1, a->imm); 610 gen_set_gpr(ctx, a->rd, dest); 611 } else { 612 if (f128 == NULL) { 613 return false; 614 } 615 616 TCGv src1h = get_gprh(ctx, a->rs1); 617 TCGv desth = dest_gprh(ctx, a->rd); 618 619 f128(dest, desth, src1, src1h, a->imm); 620 gen_set_gpr128(ctx, a->rd, dest, desth); 621 } 622 return true; 623 } 624 625 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 626 void (*func)(TCGv, TCGv, TCGv), 627 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 628 { 629 TCGv dest = dest_gpr(ctx, a->rd); 630 TCGv src1 = get_gpr(ctx, a->rs1, ext); 631 TCGv src2 = tcg_constant_tl(a->imm); 632 633 if (get_ol(ctx) < MXL_RV128) { 634 func(dest, src1, src2); 635 gen_set_gpr(ctx, a->rd, dest); 636 } else { 637 if (f128 == NULL) { 638 return false; 639 } 640 641 TCGv src1h = get_gprh(ctx, a->rs1); 642 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 643 TCGv desth = dest_gprh(ctx, a->rd); 644 645 f128(dest, desth, src1, src1h, src2, src2h); 646 gen_set_gpr128(ctx, a->rd, dest, desth); 647 } 648 return true; 649 } 650 651 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 652 void (*func)(TCGv, TCGv, TCGv), 653 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 654 { 655 TCGv dest = dest_gpr(ctx, a->rd); 656 TCGv src1 = get_gpr(ctx, a->rs1, ext); 657 TCGv src2 = get_gpr(ctx, a->rs2, ext); 658 659 if (get_ol(ctx) < MXL_RV128) { 660 func(dest, src1, src2); 661 gen_set_gpr(ctx, a->rd, dest); 662 } else { 663 if (f128 == NULL) { 664 return false; 665 } 666 667 TCGv src1h = get_gprh(ctx, a->rs1); 668 TCGv src2h = get_gprh(ctx, a->rs2); 669 TCGv desth = dest_gprh(ctx, a->rd); 670 671 f128(dest, desth, src1, src1h, src2, src2h); 672 gen_set_gpr128(ctx, a->rd, dest, desth); 673 } 674 return true; 675 } 676 677 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 678 void (*f_tl)(TCGv, TCGv, TCGv), 679 void (*f_32)(TCGv, TCGv, TCGv), 680 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 681 { 682 int olen = get_olen(ctx); 683 684 if (olen != TARGET_LONG_BITS) { 685 if (olen == 32) { 686 f_tl = f_32; 687 } else if (olen != 128) { 688 g_assert_not_reached(); 689 } 690 } 691 return gen_arith(ctx, a, ext, f_tl, f_128); 692 } 693 694 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 695 void (*func)(TCGv, TCGv, target_long), 696 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 697 { 698 TCGv dest, src1; 699 int max_len = get_olen(ctx); 700 701 if (a->shamt >= max_len) { 702 return false; 703 } 704 705 dest = dest_gpr(ctx, a->rd); 706 src1 = get_gpr(ctx, a->rs1, ext); 707 708 if (max_len < 128) { 709 func(dest, src1, a->shamt); 710 gen_set_gpr(ctx, a->rd, dest); 711 } else { 712 TCGv src1h = get_gprh(ctx, a->rs1); 713 TCGv desth = dest_gprh(ctx, a->rd); 714 715 if (f128 == NULL) { 716 return false; 717 } 718 f128(dest, desth, src1, src1h, a->shamt); 719 gen_set_gpr128(ctx, a->rd, dest, desth); 720 } 721 return true; 722 } 723 724 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 725 DisasExtend ext, 726 void (*f_tl)(TCGv, TCGv, target_long), 727 void (*f_32)(TCGv, TCGv, target_long), 728 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 729 target_long)) 730 { 731 int olen = get_olen(ctx); 732 if (olen != TARGET_LONG_BITS) { 733 if (olen == 32) { 734 f_tl = f_32; 735 } else if (olen != 128) { 736 g_assert_not_reached(); 737 } 738 } 739 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 740 } 741 742 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 743 void (*func)(TCGv, TCGv, TCGv)) 744 { 745 TCGv dest, src1, src2; 746 int max_len = get_olen(ctx); 747 748 if (a->shamt >= max_len) { 749 return false; 750 } 751 752 dest = dest_gpr(ctx, a->rd); 753 src1 = get_gpr(ctx, a->rs1, ext); 754 src2 = tcg_constant_tl(a->shamt); 755 756 func(dest, src1, src2); 757 758 gen_set_gpr(ctx, a->rd, dest); 759 return true; 760 } 761 762 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 763 void (*func)(TCGv, TCGv, TCGv), 764 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 765 { 766 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 767 TCGv ext2 = tcg_temp_new(); 768 int max_len = get_olen(ctx); 769 770 tcg_gen_andi_tl(ext2, src2, max_len - 1); 771 772 TCGv dest = dest_gpr(ctx, a->rd); 773 TCGv src1 = get_gpr(ctx, a->rs1, ext); 774 775 if (max_len < 128) { 776 func(dest, src1, ext2); 777 gen_set_gpr(ctx, a->rd, dest); 778 } else { 779 TCGv src1h = get_gprh(ctx, a->rs1); 780 TCGv desth = dest_gprh(ctx, a->rd); 781 782 if (f128 == NULL) { 783 return false; 784 } 785 f128(dest, desth, src1, src1h, ext2); 786 gen_set_gpr128(ctx, a->rd, dest, desth); 787 } 788 tcg_temp_free(ext2); 789 return true; 790 } 791 792 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 793 void (*f_tl)(TCGv, TCGv, TCGv), 794 void (*f_32)(TCGv, TCGv, TCGv), 795 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 796 { 797 int olen = get_olen(ctx); 798 if (olen != TARGET_LONG_BITS) { 799 if (olen == 32) { 800 f_tl = f_32; 801 } else if (olen != 128) { 802 g_assert_not_reached(); 803 } 804 } 805 return gen_shift(ctx, a, ext, f_tl, f_128); 806 } 807 808 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 809 void (*func)(TCGv, TCGv)) 810 { 811 TCGv dest = dest_gpr(ctx, a->rd); 812 TCGv src1 = get_gpr(ctx, a->rs1, ext); 813 814 func(dest, src1); 815 816 gen_set_gpr(ctx, a->rd, dest); 817 return true; 818 } 819 820 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 821 void (*f_tl)(TCGv, TCGv), 822 void (*f_32)(TCGv, TCGv)) 823 { 824 int olen = get_olen(ctx); 825 826 if (olen != TARGET_LONG_BITS) { 827 if (olen == 32) { 828 f_tl = f_32; 829 } else { 830 g_assert_not_reached(); 831 } 832 } 833 return gen_unary(ctx, a, ext, f_tl); 834 } 835 836 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 837 { 838 DisasContext *ctx = container_of(dcbase, DisasContext, base); 839 CPUState *cpu = ctx->cs; 840 CPURISCVState *env = cpu->env_ptr; 841 842 return cpu_ldl_code(env, pc); 843 } 844 845 /* Include insn module translation function */ 846 #include "insn_trans/trans_rvi.c.inc" 847 #include "insn_trans/trans_rvm.c.inc" 848 #include "insn_trans/trans_rva.c.inc" 849 #include "insn_trans/trans_rvf.c.inc" 850 #include "insn_trans/trans_rvd.c.inc" 851 #include "insn_trans/trans_rvh.c.inc" 852 #include "insn_trans/trans_rvv.c.inc" 853 #include "insn_trans/trans_rvb.c.inc" 854 #include "insn_trans/trans_rvzfh.c.inc" 855 #include "insn_trans/trans_privileged.c.inc" 856 857 /* Include the auto-generated decoder for 16 bit insn */ 858 #include "decode-insn16.c.inc" 859 860 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 861 { 862 /* check for compressed insn */ 863 if (extract16(opcode, 0, 2) != 3) { 864 if (!has_ext(ctx, RVC)) { 865 gen_exception_illegal(ctx); 866 } else { 867 ctx->opcode = opcode; 868 ctx->pc_succ_insn = ctx->base.pc_next + 2; 869 if (!decode_insn16(ctx, opcode)) { 870 gen_exception_illegal(ctx); 871 } 872 } 873 } else { 874 uint32_t opcode32 = opcode; 875 opcode32 = deposit32(opcode32, 16, 16, 876 translator_lduw(env, &ctx->base, 877 ctx->base.pc_next + 2)); 878 ctx->opcode = opcode32; 879 ctx->pc_succ_insn = ctx->base.pc_next + 4; 880 if (!decode_insn32(ctx, opcode32)) { 881 gen_exception_illegal(ctx); 882 } 883 } 884 } 885 886 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 887 { 888 DisasContext *ctx = container_of(dcbase, DisasContext, base); 889 CPURISCVState *env = cs->env_ptr; 890 RISCVCPU *cpu = RISCV_CPU(cs); 891 uint32_t tb_flags = ctx->base.tb->flags; 892 893 ctx->pc_succ_insn = ctx->base.pc_first; 894 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 895 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 896 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 897 ctx->priv_ver = env->priv_ver; 898 #if !defined(CONFIG_USER_ONLY) 899 if (riscv_has_ext(env, RVH)) { 900 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 901 } else { 902 ctx->virt_enabled = false; 903 } 904 #else 905 ctx->virt_enabled = false; 906 #endif 907 ctx->misa_ext = env->misa_ext; 908 ctx->frm = -1; /* unknown rounding mode */ 909 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 910 ctx->ext_zfh = cpu->cfg.ext_zfh; 911 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; 912 ctx->ext_zve32f = cpu->cfg.ext_zve32f; 913 ctx->ext_zve64f = cpu->cfg.ext_zve64f; 914 ctx->vlen = cpu->cfg.vlen; 915 ctx->elen = cpu->cfg.elen; 916 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 917 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 918 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 919 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 920 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 921 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 922 ctx->vstart = env->vstart; 923 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 924 ctx->misa_mxl_max = env->misa_mxl_max; 925 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 926 ctx->cs = cs; 927 ctx->ntemp = 0; 928 memset(ctx->temp, 0, sizeof(ctx->temp)); 929 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); 930 ctx->zero = tcg_constant_tl(0); 931 } 932 933 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 934 { 935 } 936 937 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 938 { 939 DisasContext *ctx = container_of(dcbase, DisasContext, base); 940 941 tcg_gen_insn_start(ctx->base.pc_next); 942 } 943 944 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 945 { 946 DisasContext *ctx = container_of(dcbase, DisasContext, base); 947 CPURISCVState *env = cpu->env_ptr; 948 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 949 950 ctx->ol = ctx->xl; 951 decode_opc(env, ctx, opcode16); 952 ctx->base.pc_next = ctx->pc_succ_insn; 953 954 for (int i = ctx->ntemp - 1; i >= 0; --i) { 955 tcg_temp_free(ctx->temp[i]); 956 ctx->temp[i] = NULL; 957 } 958 ctx->ntemp = 0; 959 960 if (ctx->base.is_jmp == DISAS_NEXT) { 961 target_ulong page_start; 962 963 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 964 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 965 ctx->base.is_jmp = DISAS_TOO_MANY; 966 } 967 } 968 } 969 970 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 971 { 972 DisasContext *ctx = container_of(dcbase, DisasContext, base); 973 974 switch (ctx->base.is_jmp) { 975 case DISAS_TOO_MANY: 976 gen_goto_tb(ctx, 0, ctx->base.pc_next); 977 break; 978 case DISAS_NORETURN: 979 break; 980 default: 981 g_assert_not_reached(); 982 } 983 } 984 985 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 986 { 987 #ifndef CONFIG_USER_ONLY 988 RISCVCPU *rvcpu = RISCV_CPU(cpu); 989 CPURISCVState *env = &rvcpu->env; 990 #endif 991 992 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 993 #ifndef CONFIG_USER_ONLY 994 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 995 #endif 996 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 997 } 998 999 static const TranslatorOps riscv_tr_ops = { 1000 .init_disas_context = riscv_tr_init_disas_context, 1001 .tb_start = riscv_tr_tb_start, 1002 .insn_start = riscv_tr_insn_start, 1003 .translate_insn = riscv_tr_translate_insn, 1004 .tb_stop = riscv_tr_tb_stop, 1005 .disas_log = riscv_tr_disas_log, 1006 }; 1007 1008 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1009 { 1010 DisasContext ctx; 1011 1012 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1013 } 1014 1015 void riscv_translate_init(void) 1016 { 1017 int i; 1018 1019 /* 1020 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1021 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1022 * unless you specifically block reads/writes to reg 0. 1023 */ 1024 cpu_gpr[0] = NULL; 1025 cpu_gprh[0] = NULL; 1026 1027 for (i = 1; i < 32; i++) { 1028 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1029 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1030 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1031 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1032 } 1033 1034 for (i = 0; i < 32; i++) { 1035 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1036 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1037 } 1038 1039 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1040 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1041 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1042 "vstart"); 1043 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1044 "load_res"); 1045 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1046 "load_val"); 1047 /* Assign PM CSRs to tcg globals */ 1048 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1049 "pmmask"); 1050 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1051 "pmbase"); 1052 } 1053