1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 34 /* global register indices */ 35 static TCGv cpu_gpr[32], cpu_pc, cpu_vl; 36 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 37 static TCGv load_res; 38 static TCGv load_val; 39 /* globals for PM CSRs */ 40 static TCGv pm_mask[4]; 41 static TCGv pm_base[4]; 42 43 #include "exec/gen-icount.h" 44 45 /* 46 * If an operation is being performed on less than TARGET_LONG_BITS, 47 * it may require the inputs to be sign- or zero-extended; which will 48 * depend on the exact operation being performed. 49 */ 50 typedef enum { 51 EXT_NONE, 52 EXT_SIGN, 53 EXT_ZERO, 54 } DisasExtend; 55 56 typedef struct DisasContext { 57 DisasContextBase base; 58 /* pc_succ_insn points to the instruction following base.pc_next */ 59 target_ulong pc_succ_insn; 60 target_ulong priv_ver; 61 RISCVMXL xl; 62 uint32_t misa_ext; 63 uint32_t opcode; 64 uint32_t mstatus_fs; 65 uint32_t mstatus_hs_fs; 66 uint32_t mem_idx; 67 /* Remember the rounding mode encoded in the previous fp instruction, 68 which we have already installed into env->fp_status. Or -1 for 69 no previous fp instruction. Note that we exit the TB when writing 70 to any system register, which includes CSR_FRM, so we do not have 71 to reset this known value. */ 72 int frm; 73 RISCVMXL ol; 74 bool virt_enabled; 75 bool ext_ifencei; 76 bool hlsx; 77 /* vector extension */ 78 bool vill; 79 uint8_t lmul; 80 uint8_t sew; 81 uint16_t vlen; 82 uint16_t mlen; 83 bool vl_eq_vlmax; 84 uint8_t ntemp; 85 CPUState *cs; 86 TCGv zero; 87 /* Space for 3 operands plus 1 extra for address computation. */ 88 TCGv temp[4]; 89 /* PointerMasking extension */ 90 bool pm_enabled; 91 TCGv pm_mask; 92 TCGv pm_base; 93 } DisasContext; 94 95 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 96 { 97 return ctx->misa_ext & ext; 98 } 99 100 #ifdef TARGET_RISCV32 101 #define get_xl(ctx) MXL_RV32 102 #elif defined(CONFIG_USER_ONLY) 103 #define get_xl(ctx) MXL_RV64 104 #else 105 #define get_xl(ctx) ((ctx)->xl) 106 #endif 107 108 /* The word size for this machine mode. */ 109 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 110 { 111 return 16 << get_xl(ctx); 112 } 113 114 /* The operation length, as opposed to the xlen. */ 115 #ifdef TARGET_RISCV32 116 #define get_ol(ctx) MXL_RV32 117 #else 118 #define get_ol(ctx) ((ctx)->ol) 119 #endif 120 121 static inline int get_olen(DisasContext *ctx) 122 { 123 return 16 << get_ol(ctx); 124 } 125 126 /* 127 * RISC-V requires NaN-boxing of narrower width floating point values. 128 * This applies when a 32-bit value is assigned to a 64-bit FP register. 129 * For consistency and simplicity, we nanbox results even when the RVD 130 * extension is not present. 131 */ 132 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 133 { 134 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 135 } 136 137 /* 138 * A narrow n-bit operation, where n < FLEN, checks that input operands 139 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 140 * If so, the least-significant bits of the input are used, otherwise the 141 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 142 * 143 * Here, the result is always nan-boxed, even the canonical nan. 144 */ 145 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 146 { 147 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 148 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 149 150 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 151 } 152 153 static void generate_exception(DisasContext *ctx, int excp) 154 { 155 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 156 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 157 ctx->base.is_jmp = DISAS_NORETURN; 158 } 159 160 static void generate_exception_mtval(DisasContext *ctx, int excp) 161 { 162 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 163 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 164 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 165 ctx->base.is_jmp = DISAS_NORETURN; 166 } 167 168 static void gen_exception_illegal(DisasContext *ctx) 169 { 170 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 171 } 172 173 static void gen_exception_inst_addr_mis(DisasContext *ctx) 174 { 175 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 176 } 177 178 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 179 { 180 if (translator_use_goto_tb(&ctx->base, dest)) { 181 tcg_gen_goto_tb(n); 182 tcg_gen_movi_tl(cpu_pc, dest); 183 tcg_gen_exit_tb(ctx->base.tb, n); 184 } else { 185 tcg_gen_movi_tl(cpu_pc, dest); 186 tcg_gen_lookup_and_goto_ptr(); 187 } 188 } 189 190 /* 191 * Wrappers for getting reg values. 192 * 193 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 194 * constant zero as a source, and an uninitialized sink as destination. 195 * 196 * Further, we may provide an extension for word operations. 197 */ 198 static TCGv temp_new(DisasContext *ctx) 199 { 200 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 201 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 202 } 203 204 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 205 { 206 TCGv t; 207 208 if (reg_num == 0) { 209 return ctx->zero; 210 } 211 212 switch (get_ol(ctx)) { 213 case MXL_RV32: 214 switch (ext) { 215 case EXT_NONE: 216 break; 217 case EXT_SIGN: 218 t = temp_new(ctx); 219 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 220 return t; 221 case EXT_ZERO: 222 t = temp_new(ctx); 223 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 224 return t; 225 default: 226 g_assert_not_reached(); 227 } 228 break; 229 case MXL_RV64: 230 break; 231 default: 232 g_assert_not_reached(); 233 } 234 return cpu_gpr[reg_num]; 235 } 236 237 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 238 { 239 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 240 return temp_new(ctx); 241 } 242 return cpu_gpr[reg_num]; 243 } 244 245 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 246 { 247 if (reg_num != 0) { 248 switch (get_ol(ctx)) { 249 case MXL_RV32: 250 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 251 break; 252 case MXL_RV64: 253 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 254 break; 255 default: 256 g_assert_not_reached(); 257 } 258 } 259 } 260 261 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 262 { 263 target_ulong next_pc; 264 265 /* check misaligned: */ 266 next_pc = ctx->base.pc_next + imm; 267 if (!has_ext(ctx, RVC)) { 268 if ((next_pc & 0x3) != 0) { 269 gen_exception_inst_addr_mis(ctx); 270 return; 271 } 272 } 273 if (rd != 0) { 274 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 275 } 276 277 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 278 ctx->base.is_jmp = DISAS_NORETURN; 279 } 280 281 /* 282 * Generates address adjustment for PointerMasking 283 */ 284 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) 285 { 286 TCGv temp; 287 if (!s->pm_enabled) { 288 /* Load unmodified address */ 289 return src; 290 } else { 291 temp = temp_new(s); 292 tcg_gen_andc_tl(temp, src, s->pm_mask); 293 tcg_gen_or_tl(temp, temp, s->pm_base); 294 return temp; 295 } 296 } 297 298 #ifndef CONFIG_USER_ONLY 299 /* The states of mstatus_fs are: 300 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 301 * We will have already diagnosed disabled state, 302 * and need to turn initial/clean into dirty. 303 */ 304 static void mark_fs_dirty(DisasContext *ctx) 305 { 306 TCGv tmp; 307 308 if (ctx->mstatus_fs != MSTATUS_FS) { 309 /* Remember the state change for the rest of the TB. */ 310 ctx->mstatus_fs = MSTATUS_FS; 311 312 tmp = tcg_temp_new(); 313 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 314 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 315 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 316 tcg_temp_free(tmp); 317 } 318 319 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 320 /* Remember the stage change for the rest of the TB. */ 321 ctx->mstatus_hs_fs = MSTATUS_FS; 322 323 tmp = tcg_temp_new(); 324 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 325 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 326 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 327 tcg_temp_free(tmp); 328 } 329 } 330 #else 331 static inline void mark_fs_dirty(DisasContext *ctx) { } 332 #endif 333 334 static void gen_set_rm(DisasContext *ctx, int rm) 335 { 336 if (ctx->frm == rm) { 337 return; 338 } 339 ctx->frm = rm; 340 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 341 } 342 343 static int ex_plus_1(DisasContext *ctx, int nf) 344 { 345 return nf + 1; 346 } 347 348 #define EX_SH(amount) \ 349 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 350 { \ 351 return imm << amount; \ 352 } 353 EX_SH(1) 354 EX_SH(2) 355 EX_SH(3) 356 EX_SH(4) 357 EX_SH(12) 358 359 #define REQUIRE_EXT(ctx, ext) do { \ 360 if (!has_ext(ctx, ext)) { \ 361 return false; \ 362 } \ 363 } while (0) 364 365 #define REQUIRE_32BIT(ctx) do { \ 366 if (get_xl(ctx) != MXL_RV32) { \ 367 return false; \ 368 } \ 369 } while (0) 370 371 #define REQUIRE_64BIT(ctx) do { \ 372 if (get_xl(ctx) < MXL_RV64) { \ 373 return false; \ 374 } \ 375 } while (0) 376 377 static int ex_rvc_register(DisasContext *ctx, int reg) 378 { 379 return 8 + reg; 380 } 381 382 static int ex_rvc_shifti(DisasContext *ctx, int imm) 383 { 384 /* For RV128 a shamt of 0 means a shift by 64. */ 385 return imm ? imm : 64; 386 } 387 388 /* Include the auto-generated decoder for 32 bit insn */ 389 #include "decode-insn32.c.inc" 390 391 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 392 void (*func)(TCGv, TCGv, target_long)) 393 { 394 TCGv dest = dest_gpr(ctx, a->rd); 395 TCGv src1 = get_gpr(ctx, a->rs1, ext); 396 397 func(dest, src1, a->imm); 398 399 gen_set_gpr(ctx, a->rd, dest); 400 return true; 401 } 402 403 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 404 void (*func)(TCGv, TCGv, TCGv)) 405 { 406 TCGv dest = dest_gpr(ctx, a->rd); 407 TCGv src1 = get_gpr(ctx, a->rs1, ext); 408 TCGv src2 = tcg_constant_tl(a->imm); 409 410 func(dest, src1, src2); 411 412 gen_set_gpr(ctx, a->rd, dest); 413 return true; 414 } 415 416 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 417 void (*func)(TCGv, TCGv, TCGv)) 418 { 419 TCGv dest = dest_gpr(ctx, a->rd); 420 TCGv src1 = get_gpr(ctx, a->rs1, ext); 421 TCGv src2 = get_gpr(ctx, a->rs2, ext); 422 423 func(dest, src1, src2); 424 425 gen_set_gpr(ctx, a->rd, dest); 426 return true; 427 } 428 429 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 430 void (*f_tl)(TCGv, TCGv, TCGv), 431 void (*f_32)(TCGv, TCGv, TCGv)) 432 { 433 int olen = get_olen(ctx); 434 435 if (olen != TARGET_LONG_BITS) { 436 if (olen == 32) { 437 f_tl = f_32; 438 } else { 439 g_assert_not_reached(); 440 } 441 } 442 return gen_arith(ctx, a, ext, f_tl); 443 } 444 445 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 446 void (*func)(TCGv, TCGv, target_long)) 447 { 448 TCGv dest, src1; 449 int max_len = get_olen(ctx); 450 451 if (a->shamt >= max_len) { 452 return false; 453 } 454 455 dest = dest_gpr(ctx, a->rd); 456 src1 = get_gpr(ctx, a->rs1, ext); 457 458 func(dest, src1, a->shamt); 459 460 gen_set_gpr(ctx, a->rd, dest); 461 return true; 462 } 463 464 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 465 DisasExtend ext, 466 void (*f_tl)(TCGv, TCGv, target_long), 467 void (*f_32)(TCGv, TCGv, target_long)) 468 { 469 int olen = get_olen(ctx); 470 if (olen != TARGET_LONG_BITS) { 471 if (olen == 32) { 472 f_tl = f_32; 473 } else { 474 g_assert_not_reached(); 475 } 476 } 477 return gen_shift_imm_fn(ctx, a, ext, f_tl); 478 } 479 480 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 481 void (*func)(TCGv, TCGv, TCGv)) 482 { 483 TCGv dest, src1, src2; 484 int max_len = get_olen(ctx); 485 486 if (a->shamt >= max_len) { 487 return false; 488 } 489 490 dest = dest_gpr(ctx, a->rd); 491 src1 = get_gpr(ctx, a->rs1, ext); 492 src2 = tcg_constant_tl(a->shamt); 493 494 func(dest, src1, src2); 495 496 gen_set_gpr(ctx, a->rd, dest); 497 return true; 498 } 499 500 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 501 void (*func)(TCGv, TCGv, TCGv)) 502 { 503 TCGv dest = dest_gpr(ctx, a->rd); 504 TCGv src1 = get_gpr(ctx, a->rs1, ext); 505 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 506 TCGv ext2 = tcg_temp_new(); 507 508 tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); 509 func(dest, src1, ext2); 510 511 gen_set_gpr(ctx, a->rd, dest); 512 tcg_temp_free(ext2); 513 return true; 514 } 515 516 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 517 void (*f_tl)(TCGv, TCGv, TCGv), 518 void (*f_32)(TCGv, TCGv, TCGv)) 519 { 520 int olen = get_olen(ctx); 521 if (olen != TARGET_LONG_BITS) { 522 if (olen == 32) { 523 f_tl = f_32; 524 } else { 525 g_assert_not_reached(); 526 } 527 } 528 return gen_shift(ctx, a, ext, f_tl); 529 } 530 531 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 532 void (*func)(TCGv, TCGv)) 533 { 534 TCGv dest = dest_gpr(ctx, a->rd); 535 TCGv src1 = get_gpr(ctx, a->rs1, ext); 536 537 func(dest, src1); 538 539 gen_set_gpr(ctx, a->rd, dest); 540 return true; 541 } 542 543 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 544 void (*f_tl)(TCGv, TCGv), 545 void (*f_32)(TCGv, TCGv)) 546 { 547 int olen = get_olen(ctx); 548 549 if (olen != TARGET_LONG_BITS) { 550 if (olen == 32) { 551 f_tl = f_32; 552 } else { 553 g_assert_not_reached(); 554 } 555 } 556 return gen_unary(ctx, a, ext, f_tl); 557 } 558 559 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 560 { 561 DisasContext *ctx = container_of(dcbase, DisasContext, base); 562 CPUState *cpu = ctx->cs; 563 CPURISCVState *env = cpu->env_ptr; 564 565 return cpu_ldl_code(env, pc); 566 } 567 568 /* Include insn module translation function */ 569 #include "insn_trans/trans_rvi.c.inc" 570 #include "insn_trans/trans_rvm.c.inc" 571 #include "insn_trans/trans_rva.c.inc" 572 #include "insn_trans/trans_rvf.c.inc" 573 #include "insn_trans/trans_rvd.c.inc" 574 #include "insn_trans/trans_rvh.c.inc" 575 #include "insn_trans/trans_rvv.c.inc" 576 #include "insn_trans/trans_rvb.c.inc" 577 #include "insn_trans/trans_privileged.c.inc" 578 579 /* Include the auto-generated decoder for 16 bit insn */ 580 #include "decode-insn16.c.inc" 581 582 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 583 { 584 /* check for compressed insn */ 585 if (extract16(opcode, 0, 2) != 3) { 586 if (!has_ext(ctx, RVC)) { 587 gen_exception_illegal(ctx); 588 } else { 589 ctx->pc_succ_insn = ctx->base.pc_next + 2; 590 if (!decode_insn16(ctx, opcode)) { 591 gen_exception_illegal(ctx); 592 } 593 } 594 } else { 595 uint32_t opcode32 = opcode; 596 opcode32 = deposit32(opcode32, 16, 16, 597 translator_lduw(env, &ctx->base, 598 ctx->base.pc_next + 2)); 599 ctx->pc_succ_insn = ctx->base.pc_next + 4; 600 if (!decode_insn32(ctx, opcode32)) { 601 gen_exception_illegal(ctx); 602 } 603 } 604 } 605 606 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 607 { 608 DisasContext *ctx = container_of(dcbase, DisasContext, base); 609 CPURISCVState *env = cs->env_ptr; 610 RISCVCPU *cpu = RISCV_CPU(cs); 611 uint32_t tb_flags = ctx->base.tb->flags; 612 613 ctx->pc_succ_insn = ctx->base.pc_first; 614 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 615 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 616 ctx->priv_ver = env->priv_ver; 617 #if !defined(CONFIG_USER_ONLY) 618 if (riscv_has_ext(env, RVH)) { 619 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 620 } else { 621 ctx->virt_enabled = false; 622 } 623 #else 624 ctx->virt_enabled = false; 625 #endif 626 ctx->misa_ext = env->misa_ext; 627 ctx->frm = -1; /* unknown rounding mode */ 628 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 629 ctx->vlen = cpu->cfg.vlen; 630 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 631 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 632 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 633 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 634 ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); 635 ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); 636 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 637 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 638 ctx->cs = cs; 639 ctx->ntemp = 0; 640 memset(ctx->temp, 0, sizeof(ctx->temp)); 641 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); 642 int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK; 643 ctx->pm_mask = pm_mask[priv]; 644 ctx->pm_base = pm_base[priv]; 645 646 ctx->zero = tcg_constant_tl(0); 647 } 648 649 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 650 { 651 } 652 653 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 654 { 655 DisasContext *ctx = container_of(dcbase, DisasContext, base); 656 657 tcg_gen_insn_start(ctx->base.pc_next); 658 } 659 660 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 661 { 662 DisasContext *ctx = container_of(dcbase, DisasContext, base); 663 CPURISCVState *env = cpu->env_ptr; 664 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 665 666 ctx->ol = ctx->xl; 667 decode_opc(env, ctx, opcode16); 668 ctx->base.pc_next = ctx->pc_succ_insn; 669 670 for (int i = ctx->ntemp - 1; i >= 0; --i) { 671 tcg_temp_free(ctx->temp[i]); 672 ctx->temp[i] = NULL; 673 } 674 ctx->ntemp = 0; 675 676 if (ctx->base.is_jmp == DISAS_NEXT) { 677 target_ulong page_start; 678 679 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 680 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 681 ctx->base.is_jmp = DISAS_TOO_MANY; 682 } 683 } 684 } 685 686 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 687 { 688 DisasContext *ctx = container_of(dcbase, DisasContext, base); 689 690 switch (ctx->base.is_jmp) { 691 case DISAS_TOO_MANY: 692 gen_goto_tb(ctx, 0, ctx->base.pc_next); 693 break; 694 case DISAS_NORETURN: 695 break; 696 default: 697 g_assert_not_reached(); 698 } 699 } 700 701 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 702 { 703 #ifndef CONFIG_USER_ONLY 704 RISCVCPU *rvcpu = RISCV_CPU(cpu); 705 CPURISCVState *env = &rvcpu->env; 706 #endif 707 708 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 709 #ifndef CONFIG_USER_ONLY 710 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 711 #endif 712 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 713 } 714 715 static const TranslatorOps riscv_tr_ops = { 716 .init_disas_context = riscv_tr_init_disas_context, 717 .tb_start = riscv_tr_tb_start, 718 .insn_start = riscv_tr_insn_start, 719 .translate_insn = riscv_tr_translate_insn, 720 .tb_stop = riscv_tr_tb_stop, 721 .disas_log = riscv_tr_disas_log, 722 }; 723 724 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 725 { 726 DisasContext ctx; 727 728 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 729 } 730 731 void riscv_translate_init(void) 732 { 733 int i; 734 735 /* 736 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 737 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 738 * unless you specifically block reads/writes to reg 0. 739 */ 740 cpu_gpr[0] = NULL; 741 742 for (i = 1; i < 32; i++) { 743 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 744 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 745 } 746 747 for (i = 0; i < 32; i++) { 748 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 749 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 750 } 751 752 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 753 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 754 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 755 "load_res"); 756 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 757 "load_val"); 758 #ifndef CONFIG_USER_ONLY 759 /* Assign PM CSRs to tcg globals */ 760 pm_mask[PRV_U] = 761 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); 762 pm_base[PRV_U] = 763 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); 764 pm_mask[PRV_S] = 765 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask"); 766 pm_base[PRV_S] = 767 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase"); 768 pm_mask[PRV_M] = 769 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask"); 770 pm_base[PRV_M] = 771 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase"); 772 #endif 773 } 774