1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "tcg-cpu.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "time_helper.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "qemu/accel.h" 29 #include "qemu/error-report.h" 30 #include "qemu/log.h" 31 #include "hw/core/accel-cpu.h" 32 #include "hw/core/tcg-cpu-ops.h" 33 #include "tcg/tcg.h" 34 35 /* Hash that stores user set extensions */ 36 static GHashTable *multi_ext_user_opts; 37 static GHashTable *misa_ext_user_opts; 38 39 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 40 { 41 return g_hash_table_contains(multi_ext_user_opts, 42 GUINT_TO_POINTER(ext_offset)); 43 } 44 45 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 46 { 47 return g_hash_table_contains(misa_ext_user_opts, 48 GUINT_TO_POINTER(misa_bit)); 49 } 50 51 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 52 { 53 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 54 (gpointer)value); 55 } 56 57 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 58 { 59 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 60 (gpointer)value); 61 } 62 63 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 64 bool enabled) 65 { 66 CPURISCVState *env = &cpu->env; 67 68 if (enabled) { 69 env->misa_ext |= bit; 70 env->misa_ext_mask |= bit; 71 } else { 72 env->misa_ext &= ~bit; 73 env->misa_ext_mask &= ~bit; 74 } 75 } 76 77 static const char *cpu_priv_ver_to_str(int priv_ver) 78 { 79 switch (priv_ver) { 80 case PRIV_VERSION_1_10_0: 81 return "v1.10.0"; 82 case PRIV_VERSION_1_11_0: 83 return "v1.11.0"; 84 case PRIV_VERSION_1_12_0: 85 return "v1.12.0"; 86 } 87 88 g_assert_not_reached(); 89 } 90 91 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 92 const TranslationBlock *tb) 93 { 94 if (!(tb_cflags(tb) & CF_PCREL)) { 95 RISCVCPU *cpu = RISCV_CPU(cs); 96 CPURISCVState *env = &cpu->env; 97 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 98 99 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 100 101 if (xl == MXL_RV32) { 102 env->pc = (int32_t) tb->pc; 103 } else { 104 env->pc = tb->pc; 105 } 106 } 107 } 108 109 static void riscv_restore_state_to_opc(CPUState *cs, 110 const TranslationBlock *tb, 111 const uint64_t *data) 112 { 113 RISCVCPU *cpu = RISCV_CPU(cs); 114 CPURISCVState *env = &cpu->env; 115 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 116 target_ulong pc; 117 118 if (tb_cflags(tb) & CF_PCREL) { 119 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 120 } else { 121 pc = data[0]; 122 } 123 124 if (xl == MXL_RV32) { 125 env->pc = (int32_t)pc; 126 } else { 127 env->pc = pc; 128 } 129 env->bins = data[1]; 130 } 131 132 static const TCGCPUOps riscv_tcg_ops = { 133 .initialize = riscv_translate_init, 134 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 135 .restore_state_to_opc = riscv_restore_state_to_opc, 136 137 #ifndef CONFIG_USER_ONLY 138 .tlb_fill = riscv_cpu_tlb_fill, 139 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 140 .do_interrupt = riscv_cpu_do_interrupt, 141 .do_transaction_failed = riscv_cpu_do_transaction_failed, 142 .do_unaligned_access = riscv_cpu_do_unaligned_access, 143 .debug_excp_handler = riscv_cpu_debug_excp_handler, 144 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 145 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 146 #endif /* !CONFIG_USER_ONLY */ 147 }; 148 149 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 150 { 151 const RISCVIsaExtData *edata; 152 153 for (edata = isa_edata_arr; edata && edata->name; edata++) { 154 if (edata->ext_enable_offset != ext_offset) { 155 continue; 156 } 157 158 return edata->min_version; 159 } 160 161 g_assert_not_reached(); 162 } 163 164 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 165 { 166 const RISCVCPUMultiExtConfig *feat; 167 const RISCVIsaExtData *edata; 168 169 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 170 if (edata->ext_enable_offset == ext_offset) { 171 return edata->name; 172 } 173 } 174 175 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 176 if (feat->offset == ext_offset) { 177 return feat->name; 178 } 179 } 180 181 g_assert_not_reached(); 182 } 183 184 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 185 { 186 const RISCVCPUMultiExtConfig *feat; 187 188 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 189 if (feat->offset == ext_offset) { 190 return true; 191 } 192 } 193 194 return false; 195 } 196 197 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 198 { 199 switch (feat_offset) { 200 case CPU_CFG_OFFSET(zic64b): 201 cpu->cfg.cbom_blocksize = 64; 202 cpu->cfg.cbop_blocksize = 64; 203 cpu->cfg.cboz_blocksize = 64; 204 break; 205 case CPU_CFG_OFFSET(svade): 206 cpu->cfg.ext_svadu = false; 207 break; 208 default: 209 g_assert_not_reached(); 210 } 211 } 212 213 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 214 uint32_t ext_offset) 215 { 216 int ext_priv_ver; 217 218 if (env->priv_ver == PRIV_VERSION_LATEST) { 219 return; 220 } 221 222 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 223 return; 224 } 225 226 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 227 228 if (env->priv_ver < ext_priv_ver) { 229 /* 230 * Note: the 'priv_spec' command line option, if present, 231 * will take precedence over this priv_ver bump. 232 */ 233 env->priv_ver = ext_priv_ver; 234 } 235 } 236 237 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 238 bool value) 239 { 240 CPURISCVState *env = &cpu->env; 241 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 242 int min_version; 243 244 if (prev_val == value) { 245 return; 246 } 247 248 if (cpu_cfg_ext_is_user_set(ext_offset)) { 249 return; 250 } 251 252 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 253 /* Do not enable it if priv_ver is older than min_version */ 254 min_version = cpu_cfg_ext_get_min_version(ext_offset); 255 if (env->priv_ver < min_version) { 256 return; 257 } 258 } 259 260 isa_ext_update_enabled(cpu, ext_offset, value); 261 } 262 263 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 264 { 265 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 266 error_setg(errp, "H extension requires priv spec 1.12.0"); 267 return; 268 } 269 } 270 271 static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) 272 { 273 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 274 CPUClass *cc = CPU_CLASS(mcc); 275 CPURISCVState *env = &cpu->env; 276 277 /* Validate that MISA_MXL is set properly. */ 278 switch (env->misa_mxl_max) { 279 #ifdef TARGET_RISCV64 280 case MXL_RV64: 281 case MXL_RV128: 282 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 283 break; 284 #endif 285 case MXL_RV32: 286 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 287 break; 288 default: 289 g_assert_not_reached(); 290 } 291 292 if (env->misa_mxl_max != env->misa_mxl) { 293 error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); 294 return; 295 } 296 } 297 298 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 299 Error **errp) 300 { 301 if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { 302 error_setg(errp, 303 "Vector extension implementation only supports VLEN " 304 "in the range [128, %d]", RV_VLEN_MAX); 305 return; 306 } 307 308 if (!is_power_of_2(cfg->elen)) { 309 error_setg(errp, "Vector extension ELEN must be power of 2"); 310 return; 311 } 312 313 if (cfg->elen > 64 || cfg->elen < 8) { 314 error_setg(errp, 315 "Vector extension implementation only supports ELEN " 316 "in the range [8, 64]"); 317 return; 318 } 319 } 320 321 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 322 { 323 CPURISCVState *env = &cpu->env; 324 const RISCVIsaExtData *edata; 325 326 /* Force disable extensions if priv spec version does not match */ 327 for (edata = isa_edata_arr; edata && edata->name; edata++) { 328 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 329 (env->priv_ver < edata->min_version)) { 330 /* 331 * These two extensions are always enabled as they were supported 332 * by QEMU before they were added as extensions in the ISA. 333 */ 334 if (!strcmp(edata->name, "zicntr") || 335 !strcmp(edata->name, "zihpm")) { 336 continue; 337 } 338 339 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 340 #ifndef CONFIG_USER_ONLY 341 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 342 " because privilege spec version does not match", 343 edata->name, env->mhartid); 344 #else 345 warn_report("disabling %s extension because " 346 "privilege spec version does not match", 347 edata->name); 348 #endif 349 } 350 } 351 } 352 353 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 354 { 355 cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 && 356 cpu->cfg.cbop_blocksize == 64 && 357 cpu->cfg.cboz_blocksize == 64; 358 359 cpu->cfg.svade = !cpu->cfg.ext_svadu; 360 } 361 362 static void riscv_cpu_validate_g(RISCVCPU *cpu) 363 { 364 const char *warn_msg = "RVG mandates disabled extension %s"; 365 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 366 bool send_warn = cpu_misa_ext_is_user_set(RVG); 367 368 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 369 uint32_t bit = g_misa_bits[i]; 370 371 if (riscv_has_ext(&cpu->env, bit)) { 372 continue; 373 } 374 375 if (!cpu_misa_ext_is_user_set(bit)) { 376 riscv_cpu_write_misa_bit(cpu, bit, true); 377 continue; 378 } 379 380 if (send_warn) { 381 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 382 } 383 } 384 385 if (!cpu->cfg.ext_zicsr) { 386 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 387 cpu->cfg.ext_zicsr = true; 388 } else if (send_warn) { 389 warn_report(warn_msg, "zicsr"); 390 } 391 } 392 393 if (!cpu->cfg.ext_zifencei) { 394 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 395 cpu->cfg.ext_zifencei = true; 396 } else if (send_warn) { 397 warn_report(warn_msg, "zifencei"); 398 } 399 } 400 } 401 402 static void riscv_cpu_validate_b(RISCVCPU *cpu) 403 { 404 const char *warn_msg = "RVB mandates disabled extension %s"; 405 406 if (!cpu->cfg.ext_zba) { 407 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 408 cpu->cfg.ext_zba = true; 409 } else { 410 warn_report(warn_msg, "zba"); 411 } 412 } 413 414 if (!cpu->cfg.ext_zbb) { 415 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 416 cpu->cfg.ext_zbb = true; 417 } else { 418 warn_report(warn_msg, "zbb"); 419 } 420 } 421 422 if (!cpu->cfg.ext_zbs) { 423 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 424 cpu->cfg.ext_zbs = true; 425 } else { 426 warn_report(warn_msg, "zbs"); 427 } 428 } 429 } 430 431 /* 432 * Check consistency between chosen extensions while setting 433 * cpu->cfg accordingly. 434 */ 435 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 436 { 437 CPURISCVState *env = &cpu->env; 438 Error *local_err = NULL; 439 440 if (riscv_has_ext(env, RVG)) { 441 riscv_cpu_validate_g(cpu); 442 } 443 444 if (riscv_has_ext(env, RVB)) { 445 riscv_cpu_validate_b(cpu); 446 } 447 448 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 449 error_setg(errp, 450 "I and E extensions are incompatible"); 451 return; 452 } 453 454 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 455 error_setg(errp, 456 "Either I or E extension must be set"); 457 return; 458 } 459 460 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 461 error_setg(errp, 462 "Setting S extension without U extension is illegal"); 463 return; 464 } 465 466 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 467 error_setg(errp, 468 "H depends on an I base integer ISA with 32 x registers"); 469 return; 470 } 471 472 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 473 error_setg(errp, "H extension implicitly requires S-mode"); 474 return; 475 } 476 477 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 478 error_setg(errp, "F extension requires Zicsr"); 479 return; 480 } 481 482 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 483 error_setg(errp, "Zacas extension requires A extension"); 484 return; 485 } 486 487 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 488 error_setg(errp, "Zawrs extension requires A extension"); 489 return; 490 } 491 492 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 493 error_setg(errp, "Zfa extension requires F extension"); 494 return; 495 } 496 497 if (cpu->cfg.ext_zfh) { 498 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); 499 } 500 501 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 502 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 503 return; 504 } 505 506 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 507 error_setg(errp, "Zfbfmin extension depends on F extension"); 508 return; 509 } 510 511 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 512 error_setg(errp, "D extension requires F extension"); 513 return; 514 } 515 516 if (riscv_has_ext(env, RVV)) { 517 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 518 if (local_err != NULL) { 519 error_propagate(errp, local_err); 520 return; 521 } 522 523 /* The V vector extension depends on the Zve64d extension */ 524 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); 525 } 526 527 /* The Zve64d extension depends on the Zve64f extension */ 528 if (cpu->cfg.ext_zve64d) { 529 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); 530 } 531 532 /* The Zve64f extension depends on the Zve32f extension */ 533 if (cpu->cfg.ext_zve64f) { 534 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); 535 } 536 537 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 538 error_setg(errp, "Zve64d/V extensions require D extension"); 539 return; 540 } 541 542 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 543 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 544 return; 545 } 546 547 if (cpu->cfg.ext_zvfh) { 548 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); 549 } 550 551 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 552 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 553 return; 554 } 555 556 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 557 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 558 return; 559 } 560 561 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { 562 error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"); 563 return; 564 } 565 566 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 567 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 568 return; 569 } 570 571 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 572 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 573 return; 574 } 575 576 /* Set the ISA extensions, checks should have happened above */ 577 if (cpu->cfg.ext_zhinx) { 578 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 579 } 580 581 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 582 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 583 return; 584 } 585 586 if (cpu->cfg.ext_zfinx) { 587 if (!cpu->cfg.ext_zicsr) { 588 error_setg(errp, "Zfinx extension requires Zicsr"); 589 return; 590 } 591 if (riscv_has_ext(env, RVF)) { 592 error_setg(errp, 593 "Zfinx cannot be supported together with F extension"); 594 return; 595 } 596 } 597 598 if (cpu->cfg.ext_zce) { 599 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 600 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 601 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 602 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 603 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 604 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 605 } 606 } 607 608 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ 609 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 610 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 611 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 612 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 613 } 614 if (riscv_has_ext(env, RVD)) { 615 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 616 } 617 } 618 619 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 620 error_setg(errp, "Zcf extension is only relevant to RV32"); 621 return; 622 } 623 624 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 625 error_setg(errp, "Zcf extension requires F extension"); 626 return; 627 } 628 629 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 630 error_setg(errp, "Zcd extension requires D extension"); 631 return; 632 } 633 634 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 635 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 636 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 637 "extension"); 638 return; 639 } 640 641 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 642 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 643 "Zcd extension"); 644 return; 645 } 646 647 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 648 error_setg(errp, "Zcmt extension requires Zicsr extension"); 649 return; 650 } 651 652 /* 653 * Shorthand vector crypto extensions 654 */ 655 if (cpu->cfg.ext_zvknc) { 656 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); 657 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 658 } 659 660 if (cpu->cfg.ext_zvkng) { 661 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); 662 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); 663 } 664 665 if (cpu->cfg.ext_zvkn) { 666 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true); 667 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true); 668 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); 669 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); 670 } 671 672 if (cpu->cfg.ext_zvksc) { 673 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); 674 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 675 } 676 677 if (cpu->cfg.ext_zvksg) { 678 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); 679 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); 680 } 681 682 if (cpu->cfg.ext_zvks) { 683 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true); 684 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true); 685 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); 686 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); 687 } 688 689 if (cpu->cfg.ext_zvkt) { 690 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); 691 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 692 } 693 694 /* 695 * In principle Zve*x would also suffice here, were they supported 696 * in qemu 697 */ 698 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 699 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 700 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { 701 error_setg(errp, 702 "Vector crypto extensions require V or Zve* extensions"); 703 return; 704 } 705 706 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) { 707 error_setg( 708 errp, 709 "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions"); 710 return; 711 } 712 713 if (cpu->cfg.ext_zk) { 714 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); 715 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); 716 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); 717 } 718 719 if (cpu->cfg.ext_zkn) { 720 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 721 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 722 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 723 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); 724 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); 725 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); 726 } 727 728 if (cpu->cfg.ext_zks) { 729 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 730 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 731 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 732 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); 733 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); 734 } 735 736 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 737 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 738 error_setg(errp, "zicntr requires zicsr"); 739 return; 740 } 741 cpu->cfg.ext_zicntr = false; 742 } 743 744 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 745 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 746 error_setg(errp, "zihpm requires zicsr"); 747 return; 748 } 749 cpu->cfg.ext_zihpm = false; 750 } 751 752 if (!cpu->cfg.ext_zihpm) { 753 cpu->cfg.pmu_mask = 0; 754 cpu->pmu_avail_ctrs = 0; 755 } 756 757 /* 758 * Disable isa extensions based on priv spec after we 759 * validated and set everything we need. 760 */ 761 riscv_cpu_disable_priv_spec_isa_exts(cpu); 762 } 763 764 #ifndef CONFIG_USER_ONLY 765 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 766 RISCVCPUProfile *profile, 767 bool send_warn) 768 { 769 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 770 771 if (profile->satp_mode > satp_max) { 772 if (send_warn) { 773 bool is_32bit = riscv_cpu_is_32bit(cpu); 774 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 775 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 776 777 warn_report("Profile %s requires satp mode %s, " 778 "but satp mode %s was set", profile->name, 779 req_satp, cur_satp); 780 } 781 782 return false; 783 } 784 785 return true; 786 } 787 #endif 788 789 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 790 RISCVCPUProfile *profile) 791 { 792 CPURISCVState *env = &cpu->env; 793 const char *warn_msg = "Profile %s mandates disabled extension %s"; 794 bool send_warn = profile->user_set && profile->enabled; 795 bool parent_enabled, profile_impl = true; 796 int i; 797 798 #ifndef CONFIG_USER_ONLY 799 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 800 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 801 send_warn); 802 } 803 #endif 804 805 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 806 profile->priv_spec != env->priv_ver) { 807 profile_impl = false; 808 809 if (send_warn) { 810 warn_report("Profile %s requires priv spec %s, " 811 "but priv ver %s was set", profile->name, 812 cpu_priv_ver_to_str(profile->priv_spec), 813 cpu_priv_ver_to_str(env->priv_ver)); 814 } 815 } 816 817 for (i = 0; misa_bits[i] != 0; i++) { 818 uint32_t bit = misa_bits[i]; 819 820 if (!(profile->misa_ext & bit)) { 821 continue; 822 } 823 824 if (!riscv_has_ext(&cpu->env, bit)) { 825 profile_impl = false; 826 827 if (send_warn) { 828 warn_report(warn_msg, profile->name, 829 riscv_get_misa_ext_name(bit)); 830 } 831 } 832 } 833 834 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 835 int ext_offset = profile->ext_offsets[i]; 836 837 if (!isa_ext_is_enabled(cpu, ext_offset)) { 838 profile_impl = false; 839 840 if (send_warn) { 841 warn_report(warn_msg, profile->name, 842 cpu_cfg_ext_get_name(ext_offset)); 843 } 844 } 845 } 846 847 profile->enabled = profile_impl; 848 849 if (profile->parent != NULL) { 850 parent_enabled = object_property_get_bool(OBJECT(cpu), 851 profile->parent->name, 852 NULL); 853 profile->enabled = profile->enabled && parent_enabled; 854 } 855 } 856 857 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 858 { 859 for (int i = 0; riscv_profiles[i] != NULL; i++) { 860 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 861 } 862 } 863 864 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 865 { 866 CPURISCVState *env = &cpu->env; 867 Error *local_err = NULL; 868 869 riscv_cpu_validate_misa_priv(env, &local_err); 870 if (local_err != NULL) { 871 error_propagate(errp, local_err); 872 return; 873 } 874 875 riscv_cpu_update_named_features(cpu); 876 riscv_cpu_validate_profiles(cpu); 877 878 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 879 /* 880 * Enhanced PMP should only be available 881 * on harts with PMP support 882 */ 883 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 884 return; 885 } 886 887 riscv_cpu_validate_set_extensions(cpu, &local_err); 888 if (local_err != NULL) { 889 error_propagate(errp, local_err); 890 return; 891 } 892 } 893 894 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 895 { 896 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 897 } 898 899 static bool riscv_cpu_is_generic(Object *cpu_obj) 900 { 901 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 902 } 903 904 /* 905 * We'll get here via the following path: 906 * 907 * riscv_cpu_realize() 908 * -> cpu_exec_realizefn() 909 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 910 */ 911 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 912 { 913 RISCVCPU *cpu = RISCV_CPU(cs); 914 Error *local_err = NULL; 915 916 if (!riscv_cpu_tcg_compatible(cpu)) { 917 g_autofree char *name = riscv_cpu_get_name(cpu); 918 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 919 name); 920 return false; 921 } 922 923 riscv_cpu_validate_misa_mxl(cpu, &local_err); 924 if (local_err != NULL) { 925 error_propagate(errp, local_err); 926 return false; 927 } 928 929 #ifndef CONFIG_USER_ONLY 930 CPURISCVState *env = &cpu->env; 931 932 CPU(cs)->tcg_cflags |= CF_PCREL; 933 934 if (cpu->cfg.ext_sstc) { 935 riscv_timer_init(cpu); 936 } 937 938 if (cpu->cfg.pmu_mask) { 939 riscv_pmu_init(cpu, &local_err); 940 if (local_err != NULL) { 941 error_propagate(errp, local_err); 942 return false; 943 } 944 945 if (cpu->cfg.ext_sscofpmf) { 946 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 947 riscv_pmu_timer_cb, cpu); 948 } 949 } 950 951 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 952 if (riscv_has_ext(env, RVH)) { 953 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 954 } 955 #endif 956 957 return true; 958 } 959 960 typedef struct RISCVCPUMisaExtConfig { 961 target_ulong misa_bit; 962 bool enabled; 963 } RISCVCPUMisaExtConfig; 964 965 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 966 void *opaque, Error **errp) 967 { 968 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 969 target_ulong misa_bit = misa_ext_cfg->misa_bit; 970 RISCVCPU *cpu = RISCV_CPU(obj); 971 CPURISCVState *env = &cpu->env; 972 bool vendor_cpu = riscv_cpu_is_vendor(obj); 973 bool prev_val, value; 974 975 if (!visit_type_bool(v, name, &value, errp)) { 976 return; 977 } 978 979 cpu_misa_ext_add_user_opt(misa_bit, value); 980 981 prev_val = env->misa_ext & misa_bit; 982 983 if (value == prev_val) { 984 return; 985 } 986 987 if (value) { 988 if (vendor_cpu) { 989 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 990 error_setg(errp, "'%s' CPU does not allow enabling extensions", 991 cpuname); 992 return; 993 } 994 995 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 996 /* 997 * Note: the 'priv_spec' command line option, if present, 998 * will take precedence over this priv_ver bump. 999 */ 1000 env->priv_ver = PRIV_VERSION_1_12_0; 1001 } 1002 } 1003 1004 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1005 } 1006 1007 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1008 void *opaque, Error **errp) 1009 { 1010 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1011 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1012 RISCVCPU *cpu = RISCV_CPU(obj); 1013 CPURISCVState *env = &cpu->env; 1014 bool value; 1015 1016 value = env->misa_ext & misa_bit; 1017 1018 visit_type_bool(v, name, &value, errp); 1019 } 1020 1021 #define MISA_CFG(_bit, _enabled) \ 1022 {.misa_bit = _bit, .enabled = _enabled} 1023 1024 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1025 MISA_CFG(RVA, true), 1026 MISA_CFG(RVC, true), 1027 MISA_CFG(RVD, true), 1028 MISA_CFG(RVF, true), 1029 MISA_CFG(RVI, true), 1030 MISA_CFG(RVE, false), 1031 MISA_CFG(RVM, true), 1032 MISA_CFG(RVS, true), 1033 MISA_CFG(RVU, true), 1034 MISA_CFG(RVH, true), 1035 MISA_CFG(RVJ, false), 1036 MISA_CFG(RVV, false), 1037 MISA_CFG(RVG, false), 1038 MISA_CFG(RVB, false), 1039 }; 1040 1041 /* 1042 * We do not support user choice tracking for MISA 1043 * extensions yet because, so far, we do not silently 1044 * change MISA bits during realize() (RVG enables MISA 1045 * bits but the user is warned about it). 1046 */ 1047 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1048 { 1049 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1050 int i; 1051 1052 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1053 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1054 int bit = misa_cfg->misa_bit; 1055 const char *name = riscv_get_misa_ext_name(bit); 1056 const char *desc = riscv_get_misa_ext_description(bit); 1057 1058 /* Check if KVM already created the property */ 1059 if (object_property_find(cpu_obj, name)) { 1060 continue; 1061 } 1062 1063 object_property_add(cpu_obj, name, "bool", 1064 cpu_get_misa_ext_cfg, 1065 cpu_set_misa_ext_cfg, 1066 NULL, (void *)misa_cfg); 1067 object_property_set_description(cpu_obj, name, desc); 1068 if (use_def_vals) { 1069 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1070 misa_cfg->enabled); 1071 } 1072 } 1073 } 1074 1075 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1076 void *opaque, Error **errp) 1077 { 1078 RISCVCPUProfile *profile = opaque; 1079 RISCVCPU *cpu = RISCV_CPU(obj); 1080 bool value; 1081 int i, ext_offset; 1082 1083 if (riscv_cpu_is_vendor(obj)) { 1084 error_setg(errp, "Profile %s is not available for vendor CPUs", 1085 profile->name); 1086 return; 1087 } 1088 1089 if (cpu->env.misa_mxl != MXL_RV64) { 1090 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1091 profile->name); 1092 return; 1093 } 1094 1095 if (!visit_type_bool(v, name, &value, errp)) { 1096 return; 1097 } 1098 1099 profile->user_set = true; 1100 profile->enabled = value; 1101 1102 if (profile->parent != NULL) { 1103 object_property_set_bool(obj, profile->parent->name, 1104 profile->enabled, NULL); 1105 } 1106 1107 if (profile->enabled) { 1108 cpu->env.priv_ver = profile->priv_spec; 1109 } 1110 1111 #ifndef CONFIG_USER_ONLY 1112 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1113 const char *satp_prop = satp_mode_str(profile->satp_mode, 1114 riscv_cpu_is_32bit(cpu)); 1115 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1116 } 1117 #endif 1118 1119 for (i = 0; misa_bits[i] != 0; i++) { 1120 uint32_t bit = misa_bits[i]; 1121 1122 if (!(profile->misa_ext & bit)) { 1123 continue; 1124 } 1125 1126 if (bit == RVI && !profile->enabled) { 1127 /* 1128 * Disabling profiles will not disable the base 1129 * ISA RV64I. 1130 */ 1131 continue; 1132 } 1133 1134 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1135 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1136 } 1137 1138 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1139 ext_offset = profile->ext_offsets[i]; 1140 1141 if (profile->enabled) { 1142 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1143 riscv_cpu_enable_named_feat(cpu, ext_offset); 1144 } 1145 1146 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1147 } 1148 1149 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1150 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1151 } 1152 } 1153 1154 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1155 void *opaque, Error **errp) 1156 { 1157 RISCVCPUProfile *profile = opaque; 1158 bool value = profile->enabled; 1159 1160 visit_type_bool(v, name, &value, errp); 1161 } 1162 1163 static void riscv_cpu_add_profiles(Object *cpu_obj) 1164 { 1165 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1166 const RISCVCPUProfile *profile = riscv_profiles[i]; 1167 1168 object_property_add(cpu_obj, profile->name, "bool", 1169 cpu_get_profile, cpu_set_profile, 1170 NULL, (void *)profile); 1171 1172 /* 1173 * CPUs might enable a profile right from the start. 1174 * Enable its mandatory extensions right away in this 1175 * case. 1176 */ 1177 if (profile->enabled) { 1178 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1179 } 1180 } 1181 } 1182 1183 static bool cpu_ext_is_deprecated(const char *ext_name) 1184 { 1185 return isupper(ext_name[0]); 1186 } 1187 1188 /* 1189 * String will be allocated in the heap. Caller is responsible 1190 * for freeing it. 1191 */ 1192 static char *cpu_ext_to_lower(const char *ext_name) 1193 { 1194 char *ret = g_malloc0(strlen(ext_name) + 1); 1195 1196 strcpy(ret, ext_name); 1197 ret[0] = tolower(ret[0]); 1198 1199 return ret; 1200 } 1201 1202 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1203 void *opaque, Error **errp) 1204 { 1205 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1206 RISCVCPU *cpu = RISCV_CPU(obj); 1207 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1208 bool prev_val, value; 1209 1210 if (!visit_type_bool(v, name, &value, errp)) { 1211 return; 1212 } 1213 1214 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1215 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1216 1217 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1218 multi_ext_cfg->name, lower); 1219 } 1220 1221 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1222 1223 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1224 1225 if (value == prev_val) { 1226 return; 1227 } 1228 1229 if (value && vendor_cpu) { 1230 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1231 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1232 cpuname); 1233 return; 1234 } 1235 1236 if (value) { 1237 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1238 } 1239 1240 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1241 } 1242 1243 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1244 void *opaque, Error **errp) 1245 { 1246 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1247 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1248 1249 visit_type_bool(v, name, &value, errp); 1250 } 1251 1252 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1253 const RISCVCPUMultiExtConfig *multi_cfg) 1254 { 1255 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1256 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1257 1258 object_property_add(cpu_obj, multi_cfg->name, "bool", 1259 cpu_get_multi_ext_cfg, 1260 cpu_set_multi_ext_cfg, 1261 NULL, (void *)multi_cfg); 1262 1263 if (!generic_cpu || deprecated_ext) { 1264 return; 1265 } 1266 1267 /* 1268 * Set def val directly instead of using 1269 * object_property_set_bool() to save the set() 1270 * callback hash for user inputs. 1271 */ 1272 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1273 multi_cfg->enabled); 1274 } 1275 1276 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1277 const RISCVCPUMultiExtConfig *array) 1278 { 1279 const RISCVCPUMultiExtConfig *prop; 1280 1281 g_assert(array); 1282 1283 for (prop = array; prop && prop->name; prop++) { 1284 cpu_add_multi_ext_prop(obj, prop); 1285 } 1286 } 1287 1288 /* 1289 * Add CPU properties with user-facing flags. 1290 * 1291 * This will overwrite existing env->misa_ext values with the 1292 * defaults set via riscv_cpu_add_misa_properties(). 1293 */ 1294 static void riscv_cpu_add_user_properties(Object *obj) 1295 { 1296 #ifndef CONFIG_USER_ONLY 1297 riscv_add_satp_mode_properties(obj); 1298 #endif 1299 1300 riscv_cpu_add_misa_properties(obj); 1301 1302 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1303 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1304 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1305 1306 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1307 1308 riscv_cpu_add_profiles(obj); 1309 1310 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1311 qdev_property_add_static(DEVICE(obj), prop); 1312 } 1313 } 1314 1315 /* 1316 * The 'max' type CPU will have all possible ratified 1317 * non-vendor extensions enabled. 1318 */ 1319 static void riscv_init_max_cpu_extensions(Object *obj) 1320 { 1321 RISCVCPU *cpu = RISCV_CPU(obj); 1322 CPURISCVState *env = &cpu->env; 1323 const RISCVCPUMultiExtConfig *prop; 1324 1325 /* Enable RVG, RVJ and RVV that are disabled by default */ 1326 riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); 1327 1328 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1329 isa_ext_update_enabled(cpu, prop->offset, true); 1330 } 1331 1332 /* set vector version */ 1333 env->vext_ver = VEXT_VERSION_1_00_0; 1334 1335 /* Zfinx is not compatible with F. Disable it */ 1336 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1337 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1338 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1339 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1340 1341 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1342 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1343 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1344 1345 if (env->misa_mxl != MXL_RV32) { 1346 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1347 } 1348 } 1349 1350 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1351 { 1352 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1353 } 1354 1355 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1356 { 1357 RISCVCPU *cpu = RISCV_CPU(cs); 1358 Object *obj = OBJECT(cpu); 1359 1360 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1361 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1362 riscv_cpu_add_user_properties(obj); 1363 1364 if (riscv_cpu_has_max_extensions(obj)) { 1365 riscv_init_max_cpu_extensions(obj); 1366 } 1367 } 1368 1369 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1370 { 1371 /* 1372 * All cpus use the same set of operations. 1373 */ 1374 cc->tcg_ops = &riscv_tcg_ops; 1375 } 1376 1377 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1378 { 1379 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1380 } 1381 1382 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1383 { 1384 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1385 1386 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1387 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1388 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1389 } 1390 1391 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1392 .name = ACCEL_CPU_NAME("tcg"), 1393 1394 .parent = TYPE_ACCEL_CPU, 1395 .class_init = riscv_tcg_cpu_accel_class_init, 1396 .abstract = true, 1397 }; 1398 1399 static void riscv_tcg_cpu_accel_register_types(void) 1400 { 1401 type_register_static(&riscv_tcg_cpu_accel_type_info); 1402 } 1403 type_init(riscv_tcg_cpu_accel_register_types); 1404