1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "tcg-cpu.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "time_helper.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "qemu/accel.h" 29 #include "qemu/error-report.h" 30 #include "qemu/log.h" 31 #include "hw/core/accel-cpu.h" 32 #include "hw/core/tcg-cpu-ops.h" 33 #include "tcg/tcg.h" 34 35 /* Hash that stores user set extensions */ 36 static GHashTable *multi_ext_user_opts; 37 38 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 39 { 40 return g_hash_table_contains(multi_ext_user_opts, 41 GUINT_TO_POINTER(ext_offset)); 42 } 43 44 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 45 const TranslationBlock *tb) 46 { 47 if (!(tb_cflags(tb) & CF_PCREL)) { 48 RISCVCPU *cpu = RISCV_CPU(cs); 49 CPURISCVState *env = &cpu->env; 50 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 51 52 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 53 54 if (xl == MXL_RV32) { 55 env->pc = (int32_t) tb->pc; 56 } else { 57 env->pc = tb->pc; 58 } 59 } 60 } 61 62 static void riscv_restore_state_to_opc(CPUState *cs, 63 const TranslationBlock *tb, 64 const uint64_t *data) 65 { 66 RISCVCPU *cpu = RISCV_CPU(cs); 67 CPURISCVState *env = &cpu->env; 68 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 69 target_ulong pc; 70 71 if (tb_cflags(tb) & CF_PCREL) { 72 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 73 } else { 74 pc = data[0]; 75 } 76 77 if (xl == MXL_RV32) { 78 env->pc = (int32_t)pc; 79 } else { 80 env->pc = pc; 81 } 82 env->bins = data[1]; 83 } 84 85 static const struct TCGCPUOps riscv_tcg_ops = { 86 .initialize = riscv_translate_init, 87 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 88 .restore_state_to_opc = riscv_restore_state_to_opc, 89 90 #ifndef CONFIG_USER_ONLY 91 .tlb_fill = riscv_cpu_tlb_fill, 92 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 93 .do_interrupt = riscv_cpu_do_interrupt, 94 .do_transaction_failed = riscv_cpu_do_transaction_failed, 95 .do_unaligned_access = riscv_cpu_do_unaligned_access, 96 .debug_excp_handler = riscv_cpu_debug_excp_handler, 97 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 98 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 99 #endif /* !CONFIG_USER_ONLY */ 100 }; 101 102 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 103 { 104 const RISCVIsaExtData *edata; 105 106 for (edata = isa_edata_arr; edata && edata->name; edata++) { 107 if (edata->ext_enable_offset != ext_offset) { 108 continue; 109 } 110 111 return edata->min_version; 112 } 113 114 g_assert_not_reached(); 115 } 116 117 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 118 bool value) 119 { 120 CPURISCVState *env = &cpu->env; 121 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 122 int min_version; 123 124 if (prev_val == value) { 125 return; 126 } 127 128 if (cpu_cfg_ext_is_user_set(ext_offset)) { 129 return; 130 } 131 132 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 133 /* Do not enable it if priv_ver is older than min_version */ 134 min_version = cpu_cfg_ext_get_min_version(ext_offset); 135 if (env->priv_ver < min_version) { 136 return; 137 } 138 } 139 140 isa_ext_update_enabled(cpu, ext_offset, value); 141 } 142 143 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 144 { 145 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 146 error_setg(errp, "H extension requires priv spec 1.12.0"); 147 return; 148 } 149 } 150 151 static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) 152 { 153 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 154 CPUClass *cc = CPU_CLASS(mcc); 155 CPURISCVState *env = &cpu->env; 156 157 /* Validate that MISA_MXL is set properly. */ 158 switch (env->misa_mxl_max) { 159 #ifdef TARGET_RISCV64 160 case MXL_RV64: 161 case MXL_RV128: 162 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 163 break; 164 #endif 165 case MXL_RV32: 166 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 167 break; 168 default: 169 g_assert_not_reached(); 170 } 171 172 if (env->misa_mxl_max != env->misa_mxl) { 173 error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); 174 return; 175 } 176 } 177 178 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) 179 { 180 CPURISCVState *env = &cpu->env; 181 int priv_version = -1; 182 183 if (cpu->cfg.priv_spec) { 184 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 185 priv_version = PRIV_VERSION_1_12_0; 186 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 187 priv_version = PRIV_VERSION_1_11_0; 188 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 189 priv_version = PRIV_VERSION_1_10_0; 190 } else { 191 error_setg(errp, 192 "Unsupported privilege spec version '%s'", 193 cpu->cfg.priv_spec); 194 return; 195 } 196 197 env->priv_ver = priv_version; 198 } 199 } 200 201 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 202 Error **errp) 203 { 204 if (!is_power_of_2(cfg->vlen)) { 205 error_setg(errp, "Vector extension VLEN must be power of 2"); 206 return; 207 } 208 209 if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { 210 error_setg(errp, 211 "Vector extension implementation only supports VLEN " 212 "in the range [128, %d]", RV_VLEN_MAX); 213 return; 214 } 215 216 if (!is_power_of_2(cfg->elen)) { 217 error_setg(errp, "Vector extension ELEN must be power of 2"); 218 return; 219 } 220 221 if (cfg->elen > 64 || cfg->elen < 8) { 222 error_setg(errp, 223 "Vector extension implementation only supports ELEN " 224 "in the range [8, 64]"); 225 return; 226 } 227 228 if (cfg->vext_spec) { 229 if (!g_strcmp0(cfg->vext_spec, "v1.0")) { 230 env->vext_ver = VEXT_VERSION_1_00_0; 231 } else { 232 error_setg(errp, "Unsupported vector spec version '%s'", 233 cfg->vext_spec); 234 return; 235 } 236 } else if (env->vext_ver == 0) { 237 qemu_log("vector version is not specified, " 238 "use the default value v1.0\n"); 239 240 env->vext_ver = VEXT_VERSION_1_00_0; 241 } 242 } 243 244 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 245 { 246 CPURISCVState *env = &cpu->env; 247 const RISCVIsaExtData *edata; 248 249 /* Force disable extensions if priv spec version does not match */ 250 for (edata = isa_edata_arr; edata && edata->name; edata++) { 251 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 252 (env->priv_ver < edata->min_version)) { 253 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 254 #ifndef CONFIG_USER_ONLY 255 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 256 " because privilege spec version does not match", 257 edata->name, env->mhartid); 258 #else 259 warn_report("disabling %s extension because " 260 "privilege spec version does not match", 261 edata->name); 262 #endif 263 } 264 } 265 } 266 267 /* 268 * Check consistency between chosen extensions while setting 269 * cpu->cfg accordingly. 270 */ 271 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 272 { 273 CPURISCVState *env = &cpu->env; 274 Error *local_err = NULL; 275 276 /* Do some ISA extension error checking */ 277 if (riscv_has_ext(env, RVG) && 278 !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && 279 riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && 280 riscv_has_ext(env, RVD) && 281 cpu->cfg.ext_zicsr && cpu->cfg.ext_zifencei)) { 282 283 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr)) && 284 !cpu->cfg.ext_zicsr) { 285 error_setg(errp, "RVG requires Zicsr but user set Zicsr to false"); 286 return; 287 } 288 289 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei)) && 290 !cpu->cfg.ext_zifencei) { 291 error_setg(errp, "RVG requires Zifencei but user set " 292 "Zifencei to false"); 293 return; 294 } 295 296 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zicsr), true); 297 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true); 298 299 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 300 env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; 301 } 302 303 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 304 error_setg(errp, 305 "I and E extensions are incompatible"); 306 return; 307 } 308 309 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 310 error_setg(errp, 311 "Either I or E extension must be set"); 312 return; 313 } 314 315 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 316 error_setg(errp, 317 "Setting S extension without U extension is illegal"); 318 return; 319 } 320 321 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 322 error_setg(errp, 323 "H depends on an I base integer ISA with 32 x registers"); 324 return; 325 } 326 327 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 328 error_setg(errp, "H extension implicitly requires S-mode"); 329 return; 330 } 331 332 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 333 error_setg(errp, "F extension requires Zicsr"); 334 return; 335 } 336 337 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 338 error_setg(errp, "Zawrs extension requires A extension"); 339 return; 340 } 341 342 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 343 error_setg(errp, "Zfa extension requires F extension"); 344 return; 345 } 346 347 if (cpu->cfg.ext_zfh) { 348 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); 349 } 350 351 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 352 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 353 return; 354 } 355 356 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 357 error_setg(errp, "Zfbfmin extension depends on F extension"); 358 return; 359 } 360 361 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 362 error_setg(errp, "D extension requires F extension"); 363 return; 364 } 365 366 if (riscv_has_ext(env, RVV)) { 367 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 368 if (local_err != NULL) { 369 error_propagate(errp, local_err); 370 return; 371 } 372 373 /* The V vector extension depends on the Zve64d extension */ 374 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); 375 } 376 377 /* The Zve64d extension depends on the Zve64f extension */ 378 if (cpu->cfg.ext_zve64d) { 379 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); 380 } 381 382 /* The Zve64f extension depends on the Zve32f extension */ 383 if (cpu->cfg.ext_zve64f) { 384 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); 385 } 386 387 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 388 error_setg(errp, "Zve64d/V extensions require D extension"); 389 return; 390 } 391 392 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 393 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 394 return; 395 } 396 397 if (cpu->cfg.ext_zvfh) { 398 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); 399 } 400 401 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 402 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 403 return; 404 } 405 406 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 407 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 408 return; 409 } 410 411 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { 412 error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"); 413 return; 414 } 415 416 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 417 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 418 return; 419 } 420 421 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 422 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 423 return; 424 } 425 426 /* Set the ISA extensions, checks should have happened above */ 427 if (cpu->cfg.ext_zhinx) { 428 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 429 } 430 431 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 432 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 433 return; 434 } 435 436 if (cpu->cfg.ext_zfinx) { 437 if (!cpu->cfg.ext_zicsr) { 438 error_setg(errp, "Zfinx extension requires Zicsr"); 439 return; 440 } 441 if (riscv_has_ext(env, RVF)) { 442 error_setg(errp, 443 "Zfinx cannot be supported together with F extension"); 444 return; 445 } 446 } 447 448 if (cpu->cfg.ext_zce) { 449 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 450 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 451 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 452 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 453 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 454 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 455 } 456 } 457 458 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ 459 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 460 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 461 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 462 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 463 } 464 if (riscv_has_ext(env, RVD)) { 465 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 466 } 467 } 468 469 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 470 error_setg(errp, "Zcf extension is only relevant to RV32"); 471 return; 472 } 473 474 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 475 error_setg(errp, "Zcf extension requires F extension"); 476 return; 477 } 478 479 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 480 error_setg(errp, "Zcd extension requires D extension"); 481 return; 482 } 483 484 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 485 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 486 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 487 "extension"); 488 return; 489 } 490 491 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 492 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 493 "Zcd extension"); 494 return; 495 } 496 497 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 498 error_setg(errp, "Zcmt extension requires Zicsr extension"); 499 return; 500 } 501 502 /* 503 * In principle Zve*x would also suffice here, were they supported 504 * in qemu 505 */ 506 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || 507 cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) && 508 !cpu->cfg.ext_zve32f) { 509 error_setg(errp, 510 "Vector crypto extensions require V or Zve* extensions"); 511 return; 512 } 513 514 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) { 515 error_setg( 516 errp, 517 "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions"); 518 return; 519 } 520 521 if (cpu->cfg.ext_zk) { 522 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); 523 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); 524 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); 525 } 526 527 if (cpu->cfg.ext_zkn) { 528 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 529 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 530 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 531 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); 532 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); 533 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); 534 } 535 536 if (cpu->cfg.ext_zks) { 537 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 538 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 539 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 540 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); 541 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); 542 } 543 544 /* 545 * Disable isa extensions based on priv spec after we 546 * validated and set everything we need. 547 */ 548 riscv_cpu_disable_priv_spec_isa_exts(cpu); 549 } 550 551 static bool riscv_cpu_is_generic(Object *cpu_obj) 552 { 553 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 554 } 555 556 /* 557 * We'll get here via the following path: 558 * 559 * riscv_cpu_realize() 560 * -> cpu_exec_realizefn() 561 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 562 */ 563 static bool tcg_cpu_realize(CPUState *cs, Error **errp) 564 { 565 RISCVCPU *cpu = RISCV_CPU(cs); 566 CPURISCVState *env = &cpu->env; 567 Error *local_err = NULL; 568 569 if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 570 g_autofree char *name = riscv_cpu_get_name(cpu); 571 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 572 name); 573 return false; 574 } 575 576 riscv_cpu_validate_misa_mxl(cpu, &local_err); 577 if (local_err != NULL) { 578 error_propagate(errp, local_err); 579 return false; 580 } 581 582 riscv_cpu_validate_priv_spec(cpu, &local_err); 583 if (local_err != NULL) { 584 error_propagate(errp, local_err); 585 return false; 586 } 587 588 riscv_cpu_validate_misa_priv(env, &local_err); 589 if (local_err != NULL) { 590 error_propagate(errp, local_err); 591 return false; 592 } 593 594 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 595 /* 596 * Enhanced PMP should only be available 597 * on harts with PMP support 598 */ 599 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 600 return false; 601 } 602 603 riscv_cpu_validate_set_extensions(cpu, &local_err); 604 if (local_err != NULL) { 605 error_propagate(errp, local_err); 606 return false; 607 } 608 609 #ifndef CONFIG_USER_ONLY 610 CPU(cs)->tcg_cflags |= CF_PCREL; 611 612 if (cpu->cfg.ext_sstc) { 613 riscv_timer_init(cpu); 614 } 615 616 if (cpu->cfg.pmu_num) { 617 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 618 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 619 riscv_pmu_timer_cb, cpu); 620 } 621 } 622 623 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 624 if (riscv_has_ext(env, RVH)) { 625 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 626 } 627 #endif 628 629 return true; 630 } 631 632 typedef struct RISCVCPUMisaExtConfig { 633 target_ulong misa_bit; 634 bool enabled; 635 } RISCVCPUMisaExtConfig; 636 637 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 638 void *opaque, Error **errp) 639 { 640 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 641 target_ulong misa_bit = misa_ext_cfg->misa_bit; 642 RISCVCPU *cpu = RISCV_CPU(obj); 643 CPURISCVState *env = &cpu->env; 644 bool generic_cpu = riscv_cpu_is_generic(obj); 645 bool prev_val, value; 646 647 if (!visit_type_bool(v, name, &value, errp)) { 648 return; 649 } 650 651 prev_val = env->misa_ext & misa_bit; 652 653 if (value == prev_val) { 654 return; 655 } 656 657 if (value) { 658 if (!generic_cpu) { 659 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 660 error_setg(errp, "'%s' CPU does not allow enabling extensions", 661 cpuname); 662 return; 663 } 664 665 env->misa_ext |= misa_bit; 666 env->misa_ext_mask |= misa_bit; 667 } else { 668 env->misa_ext &= ~misa_bit; 669 env->misa_ext_mask &= ~misa_bit; 670 } 671 } 672 673 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 674 void *opaque, Error **errp) 675 { 676 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 677 target_ulong misa_bit = misa_ext_cfg->misa_bit; 678 RISCVCPU *cpu = RISCV_CPU(obj); 679 CPURISCVState *env = &cpu->env; 680 bool value; 681 682 value = env->misa_ext & misa_bit; 683 684 visit_type_bool(v, name, &value, errp); 685 } 686 687 #define MISA_CFG(_bit, _enabled) \ 688 {.misa_bit = _bit, .enabled = _enabled} 689 690 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 691 MISA_CFG(RVA, true), 692 MISA_CFG(RVC, true), 693 MISA_CFG(RVD, true), 694 MISA_CFG(RVF, true), 695 MISA_CFG(RVI, true), 696 MISA_CFG(RVE, false), 697 MISA_CFG(RVM, true), 698 MISA_CFG(RVS, true), 699 MISA_CFG(RVU, true), 700 MISA_CFG(RVH, true), 701 MISA_CFG(RVJ, false), 702 MISA_CFG(RVV, false), 703 MISA_CFG(RVG, false), 704 }; 705 706 /* 707 * We do not support user choice tracking for MISA 708 * extensions yet because, so far, we do not silently 709 * change MISA bits during realize() (RVG enables MISA 710 * bits but the user is warned about it). 711 */ 712 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 713 { 714 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 715 int i; 716 717 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 718 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 719 int bit = misa_cfg->misa_bit; 720 const char *name = riscv_get_misa_ext_name(bit); 721 const char *desc = riscv_get_misa_ext_description(bit); 722 723 /* Check if KVM already created the property */ 724 if (object_property_find(cpu_obj, name)) { 725 continue; 726 } 727 728 object_property_add(cpu_obj, name, "bool", 729 cpu_get_misa_ext_cfg, 730 cpu_set_misa_ext_cfg, 731 NULL, (void *)misa_cfg); 732 object_property_set_description(cpu_obj, name, desc); 733 if (use_def_vals) { 734 object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); 735 } 736 } 737 } 738 739 static bool cpu_ext_is_deprecated(const char *ext_name) 740 { 741 return isupper(ext_name[0]); 742 } 743 744 /* 745 * String will be allocated in the heap. Caller is responsible 746 * for freeing it. 747 */ 748 static char *cpu_ext_to_lower(const char *ext_name) 749 { 750 char *ret = g_malloc0(strlen(ext_name) + 1); 751 752 strcpy(ret, ext_name); 753 ret[0] = tolower(ret[0]); 754 755 return ret; 756 } 757 758 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 759 void *opaque, Error **errp) 760 { 761 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 762 RISCVCPU *cpu = RISCV_CPU(obj); 763 bool generic_cpu = riscv_cpu_is_generic(obj); 764 bool prev_val, value; 765 766 if (!visit_type_bool(v, name, &value, errp)) { 767 return; 768 } 769 770 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 771 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 772 773 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 774 multi_ext_cfg->name, lower); 775 } 776 777 g_hash_table_insert(multi_ext_user_opts, 778 GUINT_TO_POINTER(multi_ext_cfg->offset), 779 (gpointer)value); 780 781 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 782 783 if (value == prev_val) { 784 return; 785 } 786 787 if (value && !generic_cpu) { 788 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 789 error_setg(errp, "'%s' CPU does not allow enabling extensions", 790 cpuname); 791 return; 792 } 793 794 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 795 } 796 797 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 798 void *opaque, Error **errp) 799 { 800 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 801 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 802 803 visit_type_bool(v, name, &value, errp); 804 } 805 806 static void cpu_add_multi_ext_prop(Object *cpu_obj, 807 const RISCVCPUMultiExtConfig *multi_cfg) 808 { 809 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 810 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 811 812 object_property_add(cpu_obj, multi_cfg->name, "bool", 813 cpu_get_multi_ext_cfg, 814 cpu_set_multi_ext_cfg, 815 NULL, (void *)multi_cfg); 816 817 if (!generic_cpu || deprecated_ext) { 818 return; 819 } 820 821 /* 822 * Set def val directly instead of using 823 * object_property_set_bool() to save the set() 824 * callback hash for user inputs. 825 */ 826 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 827 multi_cfg->enabled); 828 } 829 830 static void riscv_cpu_add_multiext_prop_array(Object *obj, 831 const RISCVCPUMultiExtConfig *array) 832 { 833 const RISCVCPUMultiExtConfig *prop; 834 835 g_assert(array); 836 837 for (prop = array; prop && prop->name; prop++) { 838 cpu_add_multi_ext_prop(obj, prop); 839 } 840 } 841 842 /* 843 * Add CPU properties with user-facing flags. 844 * 845 * This will overwrite existing env->misa_ext values with the 846 * defaults set via riscv_cpu_add_misa_properties(). 847 */ 848 static void riscv_cpu_add_user_properties(Object *obj) 849 { 850 #ifndef CONFIG_USER_ONLY 851 riscv_add_satp_mode_properties(obj); 852 #endif 853 854 riscv_cpu_add_misa_properties(obj); 855 856 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 857 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 858 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 859 860 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 861 862 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 863 qdev_property_add_static(DEVICE(obj), prop); 864 } 865 } 866 867 /* 868 * The 'max' type CPU will have all possible ratified 869 * non-vendor extensions enabled. 870 */ 871 static void riscv_init_max_cpu_extensions(Object *obj) 872 { 873 RISCVCPU *cpu = RISCV_CPU(obj); 874 CPURISCVState *env = &cpu->env; 875 const RISCVCPUMultiExtConfig *prop; 876 877 /* Enable RVG, RVJ and RVV that are disabled by default */ 878 riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); 879 880 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 881 isa_ext_update_enabled(cpu, prop->offset, true); 882 } 883 884 /* set vector version */ 885 env->vext_ver = VEXT_VERSION_1_00_0; 886 887 /* Zfinx is not compatible with F. Disable it */ 888 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 889 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 890 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 891 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 892 893 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 894 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 895 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 896 897 if (env->misa_mxl != MXL_RV32) { 898 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 899 } 900 } 901 902 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 903 { 904 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 905 } 906 907 static void tcg_cpu_instance_init(CPUState *cs) 908 { 909 RISCVCPU *cpu = RISCV_CPU(cs); 910 Object *obj = OBJECT(cpu); 911 912 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 913 riscv_cpu_add_user_properties(obj); 914 915 if (riscv_cpu_has_max_extensions(obj)) { 916 riscv_init_max_cpu_extensions(obj); 917 } 918 } 919 920 static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 921 { 922 /* 923 * All cpus use the same set of operations. 924 */ 925 cc->tcg_ops = &riscv_tcg_ops; 926 } 927 928 static void tcg_cpu_class_init(CPUClass *cc) 929 { 930 cc->init_accel_cpu = tcg_cpu_init_ops; 931 } 932 933 static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 934 { 935 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 936 937 acc->cpu_class_init = tcg_cpu_class_init; 938 acc->cpu_instance_init = tcg_cpu_instance_init; 939 acc->cpu_target_realize = tcg_cpu_realize; 940 } 941 942 static const TypeInfo tcg_cpu_accel_type_info = { 943 .name = ACCEL_CPU_NAME("tcg"), 944 945 .parent = TYPE_ACCEL_CPU, 946 .class_init = tcg_cpu_accel_class_init, 947 .abstract = true, 948 }; 949 950 static void tcg_cpu_accel_register_types(void) 951 { 952 type_register_static(&tcg_cpu_accel_type_info); 953 } 954 type_init(tcg_cpu_accel_register_types); 955