1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "tcg-cpu.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "time_helper.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "qemu/accel.h" 29 #include "qemu/error-report.h" 30 #include "qemu/log.h" 31 #include "hw/core/accel-cpu.h" 32 #include "hw/core/tcg-cpu-ops.h" 33 #include "tcg/tcg.h" 34 35 /* Hash that stores user set extensions */ 36 static GHashTable *multi_ext_user_opts; 37 static GHashTable *misa_ext_user_opts; 38 39 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 40 { 41 return g_hash_table_contains(multi_ext_user_opts, 42 GUINT_TO_POINTER(ext_offset)); 43 } 44 45 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 46 { 47 return g_hash_table_contains(misa_ext_user_opts, 48 GUINT_TO_POINTER(misa_bit)); 49 } 50 51 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 52 { 53 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 54 (gpointer)value); 55 } 56 57 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 58 { 59 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 60 (gpointer)value); 61 } 62 63 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 64 bool enabled) 65 { 66 CPURISCVState *env = &cpu->env; 67 68 if (enabled) { 69 env->misa_ext |= bit; 70 env->misa_ext_mask |= bit; 71 } else { 72 env->misa_ext &= ~bit; 73 env->misa_ext_mask &= ~bit; 74 } 75 } 76 77 static const char *cpu_priv_ver_to_str(int priv_ver) 78 { 79 switch (priv_ver) { 80 case PRIV_VERSION_1_10_0: 81 return "v1.10.0"; 82 case PRIV_VERSION_1_11_0: 83 return "v1.11.0"; 84 case PRIV_VERSION_1_12_0: 85 return "v1.12.0"; 86 } 87 88 g_assert_not_reached(); 89 } 90 91 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 92 const TranslationBlock *tb) 93 { 94 if (!(tb_cflags(tb) & CF_PCREL)) { 95 RISCVCPU *cpu = RISCV_CPU(cs); 96 CPURISCVState *env = &cpu->env; 97 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 98 99 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 100 101 if (xl == MXL_RV32) { 102 env->pc = (int32_t) tb->pc; 103 } else { 104 env->pc = tb->pc; 105 } 106 } 107 } 108 109 static void riscv_restore_state_to_opc(CPUState *cs, 110 const TranslationBlock *tb, 111 const uint64_t *data) 112 { 113 RISCVCPU *cpu = RISCV_CPU(cs); 114 CPURISCVState *env = &cpu->env; 115 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 116 target_ulong pc; 117 118 if (tb_cflags(tb) & CF_PCREL) { 119 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 120 } else { 121 pc = data[0]; 122 } 123 124 if (xl == MXL_RV32) { 125 env->pc = (int32_t)pc; 126 } else { 127 env->pc = pc; 128 } 129 env->bins = data[1]; 130 } 131 132 static const TCGCPUOps riscv_tcg_ops = { 133 .initialize = riscv_translate_init, 134 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 135 .restore_state_to_opc = riscv_restore_state_to_opc, 136 137 #ifndef CONFIG_USER_ONLY 138 .tlb_fill = riscv_cpu_tlb_fill, 139 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 140 .do_interrupt = riscv_cpu_do_interrupt, 141 .do_transaction_failed = riscv_cpu_do_transaction_failed, 142 .do_unaligned_access = riscv_cpu_do_unaligned_access, 143 .debug_excp_handler = riscv_cpu_debug_excp_handler, 144 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 145 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 146 #endif /* !CONFIG_USER_ONLY */ 147 }; 148 149 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 150 { 151 const RISCVIsaExtData *edata; 152 153 for (edata = isa_edata_arr; edata && edata->name; edata++) { 154 if (edata->ext_enable_offset != ext_offset) { 155 continue; 156 } 157 158 return edata->min_version; 159 } 160 161 g_assert_not_reached(); 162 } 163 164 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 165 { 166 const RISCVCPUMultiExtConfig *feat; 167 const RISCVIsaExtData *edata; 168 169 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 170 if (edata->ext_enable_offset == ext_offset) { 171 return edata->name; 172 } 173 } 174 175 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 176 if (feat->offset == ext_offset) { 177 return feat->name; 178 } 179 } 180 181 g_assert_not_reached(); 182 } 183 184 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 185 { 186 const RISCVCPUMultiExtConfig *feat; 187 188 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 189 if (feat->offset == ext_offset) { 190 return true; 191 } 192 } 193 194 return false; 195 } 196 197 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 198 { 199 /* 200 * All other named features are already enabled 201 * in riscv_tcg_cpu_instance_init(). 202 */ 203 if (feat_offset == CPU_CFG_OFFSET(ext_zic64b)) { 204 cpu->cfg.cbom_blocksize = 64; 205 cpu->cfg.cbop_blocksize = 64; 206 cpu->cfg.cboz_blocksize = 64; 207 } 208 } 209 210 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 211 uint32_t ext_offset) 212 { 213 int ext_priv_ver; 214 215 if (env->priv_ver == PRIV_VERSION_LATEST) { 216 return; 217 } 218 219 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 220 221 if (env->priv_ver < ext_priv_ver) { 222 /* 223 * Note: the 'priv_spec' command line option, if present, 224 * will take precedence over this priv_ver bump. 225 */ 226 env->priv_ver = ext_priv_ver; 227 } 228 } 229 230 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 231 bool value) 232 { 233 CPURISCVState *env = &cpu->env; 234 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 235 int min_version; 236 237 if (prev_val == value) { 238 return; 239 } 240 241 if (cpu_cfg_ext_is_user_set(ext_offset)) { 242 return; 243 } 244 245 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 246 /* Do not enable it if priv_ver is older than min_version */ 247 min_version = cpu_cfg_ext_get_min_version(ext_offset); 248 if (env->priv_ver < min_version) { 249 return; 250 } 251 } 252 253 isa_ext_update_enabled(cpu, ext_offset, value); 254 } 255 256 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 257 { 258 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 259 error_setg(errp, "H extension requires priv spec 1.12.0"); 260 return; 261 } 262 } 263 264 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 265 Error **errp) 266 { 267 uint32_t vlen = cfg->vlenb << 3; 268 269 if (vlen > RV_VLEN_MAX || vlen < 128) { 270 error_setg(errp, 271 "Vector extension implementation only supports VLEN " 272 "in the range [128, %d]", RV_VLEN_MAX); 273 return; 274 } 275 276 if (cfg->elen > 64 || cfg->elen < 8) { 277 error_setg(errp, 278 "Vector extension implementation only supports ELEN " 279 "in the range [8, 64]"); 280 return; 281 } 282 } 283 284 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 285 { 286 CPURISCVState *env = &cpu->env; 287 const RISCVIsaExtData *edata; 288 289 /* Force disable extensions if priv spec version does not match */ 290 for (edata = isa_edata_arr; edata && edata->name; edata++) { 291 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 292 (env->priv_ver < edata->min_version)) { 293 /* 294 * These two extensions are always enabled as they were supported 295 * by QEMU before they were added as extensions in the ISA. 296 */ 297 if (!strcmp(edata->name, "zicntr") || 298 !strcmp(edata->name, "zihpm")) { 299 continue; 300 } 301 302 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 303 #ifndef CONFIG_USER_ONLY 304 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 305 " because privilege spec version does not match", 306 edata->name, env->mhartid); 307 #else 308 warn_report("disabling %s extension because " 309 "privilege spec version does not match", 310 edata->name); 311 #endif 312 } 313 } 314 } 315 316 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 317 { 318 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && 319 cpu->cfg.cbop_blocksize == 64 && 320 cpu->cfg.cboz_blocksize == 64; 321 } 322 323 static void riscv_cpu_validate_g(RISCVCPU *cpu) 324 { 325 const char *warn_msg = "RVG mandates disabled extension %s"; 326 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 327 bool send_warn = cpu_misa_ext_is_user_set(RVG); 328 329 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 330 uint32_t bit = g_misa_bits[i]; 331 332 if (riscv_has_ext(&cpu->env, bit)) { 333 continue; 334 } 335 336 if (!cpu_misa_ext_is_user_set(bit)) { 337 riscv_cpu_write_misa_bit(cpu, bit, true); 338 continue; 339 } 340 341 if (send_warn) { 342 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 343 } 344 } 345 346 if (!cpu->cfg.ext_zicsr) { 347 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 348 cpu->cfg.ext_zicsr = true; 349 } else if (send_warn) { 350 warn_report(warn_msg, "zicsr"); 351 } 352 } 353 354 if (!cpu->cfg.ext_zifencei) { 355 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 356 cpu->cfg.ext_zifencei = true; 357 } else if (send_warn) { 358 warn_report(warn_msg, "zifencei"); 359 } 360 } 361 } 362 363 static void riscv_cpu_validate_b(RISCVCPU *cpu) 364 { 365 const char *warn_msg = "RVB mandates disabled extension %s"; 366 367 if (!cpu->cfg.ext_zba) { 368 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 369 cpu->cfg.ext_zba = true; 370 } else { 371 warn_report(warn_msg, "zba"); 372 } 373 } 374 375 if (!cpu->cfg.ext_zbb) { 376 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 377 cpu->cfg.ext_zbb = true; 378 } else { 379 warn_report(warn_msg, "zbb"); 380 } 381 } 382 383 if (!cpu->cfg.ext_zbs) { 384 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 385 cpu->cfg.ext_zbs = true; 386 } else { 387 warn_report(warn_msg, "zbs"); 388 } 389 } 390 } 391 392 /* 393 * Check consistency between chosen extensions while setting 394 * cpu->cfg accordingly. 395 */ 396 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 397 { 398 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 399 CPURISCVState *env = &cpu->env; 400 Error *local_err = NULL; 401 402 if (riscv_has_ext(env, RVG)) { 403 riscv_cpu_validate_g(cpu); 404 } 405 406 if (riscv_has_ext(env, RVB)) { 407 riscv_cpu_validate_b(cpu); 408 } 409 410 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 411 error_setg(errp, 412 "I and E extensions are incompatible"); 413 return; 414 } 415 416 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 417 error_setg(errp, 418 "Either I or E extension must be set"); 419 return; 420 } 421 422 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 423 error_setg(errp, 424 "Setting S extension without U extension is illegal"); 425 return; 426 } 427 428 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 429 error_setg(errp, 430 "H depends on an I base integer ISA with 32 x registers"); 431 return; 432 } 433 434 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 435 error_setg(errp, "H extension implicitly requires S-mode"); 436 return; 437 } 438 439 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 440 error_setg(errp, "F extension requires Zicsr"); 441 return; 442 } 443 444 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 445 error_setg(errp, "Zacas extension requires A extension"); 446 return; 447 } 448 449 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 450 error_setg(errp, "Zawrs extension requires A extension"); 451 return; 452 } 453 454 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 455 error_setg(errp, "Zfa extension requires F extension"); 456 return; 457 } 458 459 if (cpu->cfg.ext_zfh) { 460 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); 461 } 462 463 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 464 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 465 return; 466 } 467 468 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 469 error_setg(errp, "Zfbfmin extension depends on F extension"); 470 return; 471 } 472 473 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 474 error_setg(errp, "D extension requires F extension"); 475 return; 476 } 477 478 if (riscv_has_ext(env, RVV)) { 479 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 480 if (local_err != NULL) { 481 error_propagate(errp, local_err); 482 return; 483 } 484 485 /* The V vector extension depends on the Zve64d extension */ 486 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); 487 } 488 489 /* The Zve64d extension depends on the Zve64f extension */ 490 if (cpu->cfg.ext_zve64d) { 491 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); 492 } 493 494 /* The Zve64f extension depends on the Zve32f extension */ 495 if (cpu->cfg.ext_zve64f) { 496 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); 497 } 498 499 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 500 error_setg(errp, "Zve64d/V extensions require D extension"); 501 return; 502 } 503 504 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 505 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 506 return; 507 } 508 509 if (cpu->cfg.ext_zvfh) { 510 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); 511 } 512 513 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 514 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 515 return; 516 } 517 518 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 519 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 520 return; 521 } 522 523 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { 524 error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"); 525 return; 526 } 527 528 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 529 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 530 return; 531 } 532 533 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 534 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 535 return; 536 } 537 538 /* Set the ISA extensions, checks should have happened above */ 539 if (cpu->cfg.ext_zhinx) { 540 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 541 } 542 543 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 544 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 545 return; 546 } 547 548 if (cpu->cfg.ext_zfinx) { 549 if (!cpu->cfg.ext_zicsr) { 550 error_setg(errp, "Zfinx extension requires Zicsr"); 551 return; 552 } 553 if (riscv_has_ext(env, RVF)) { 554 error_setg(errp, 555 "Zfinx cannot be supported together with F extension"); 556 return; 557 } 558 } 559 560 if (cpu->cfg.ext_zce) { 561 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 562 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 563 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 564 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 565 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 566 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 567 } 568 } 569 570 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ 571 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 572 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 573 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 574 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 575 } 576 if (riscv_has_ext(env, RVD)) { 577 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 578 } 579 } 580 581 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 582 error_setg(errp, "Zcf extension is only relevant to RV32"); 583 return; 584 } 585 586 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 587 error_setg(errp, "Zcf extension requires F extension"); 588 return; 589 } 590 591 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 592 error_setg(errp, "Zcd extension requires D extension"); 593 return; 594 } 595 596 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 597 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 598 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 599 "extension"); 600 return; 601 } 602 603 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 604 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 605 "Zcd extension"); 606 return; 607 } 608 609 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 610 error_setg(errp, "Zcmt extension requires Zicsr extension"); 611 return; 612 } 613 614 /* 615 * Shorthand vector crypto extensions 616 */ 617 if (cpu->cfg.ext_zvknc) { 618 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); 619 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 620 } 621 622 if (cpu->cfg.ext_zvkng) { 623 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); 624 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); 625 } 626 627 if (cpu->cfg.ext_zvkn) { 628 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true); 629 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true); 630 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); 631 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); 632 } 633 634 if (cpu->cfg.ext_zvksc) { 635 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); 636 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 637 } 638 639 if (cpu->cfg.ext_zvksg) { 640 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); 641 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); 642 } 643 644 if (cpu->cfg.ext_zvks) { 645 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true); 646 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true); 647 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); 648 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); 649 } 650 651 if (cpu->cfg.ext_zvkt) { 652 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); 653 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 654 } 655 656 /* 657 * In principle Zve*x would also suffice here, were they supported 658 * in qemu 659 */ 660 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 661 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 662 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { 663 error_setg(errp, 664 "Vector crypto extensions require V or Zve* extensions"); 665 return; 666 } 667 668 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) { 669 error_setg( 670 errp, 671 "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions"); 672 return; 673 } 674 675 if (cpu->cfg.ext_zk) { 676 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); 677 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); 678 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); 679 } 680 681 if (cpu->cfg.ext_zkn) { 682 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 683 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 684 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 685 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); 686 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); 687 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); 688 } 689 690 if (cpu->cfg.ext_zks) { 691 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 692 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 693 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 694 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); 695 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); 696 } 697 698 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 699 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 700 error_setg(errp, "zicntr requires zicsr"); 701 return; 702 } 703 cpu->cfg.ext_zicntr = false; 704 } 705 706 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 707 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 708 error_setg(errp, "zihpm requires zicsr"); 709 return; 710 } 711 cpu->cfg.ext_zihpm = false; 712 } 713 714 if (!cpu->cfg.ext_zihpm) { 715 cpu->cfg.pmu_mask = 0; 716 cpu->pmu_avail_ctrs = 0; 717 } 718 719 /* 720 * Disable isa extensions based on priv spec after we 721 * validated and set everything we need. 722 */ 723 riscv_cpu_disable_priv_spec_isa_exts(cpu); 724 } 725 726 #ifndef CONFIG_USER_ONLY 727 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 728 RISCVCPUProfile *profile, 729 bool send_warn) 730 { 731 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 732 733 if (profile->satp_mode > satp_max) { 734 if (send_warn) { 735 bool is_32bit = riscv_cpu_is_32bit(cpu); 736 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 737 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 738 739 warn_report("Profile %s requires satp mode %s, " 740 "but satp mode %s was set", profile->name, 741 req_satp, cur_satp); 742 } 743 744 return false; 745 } 746 747 return true; 748 } 749 #endif 750 751 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 752 RISCVCPUProfile *profile) 753 { 754 CPURISCVState *env = &cpu->env; 755 const char *warn_msg = "Profile %s mandates disabled extension %s"; 756 bool send_warn = profile->user_set && profile->enabled; 757 bool parent_enabled, profile_impl = true; 758 int i; 759 760 #ifndef CONFIG_USER_ONLY 761 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 762 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 763 send_warn); 764 } 765 #endif 766 767 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 768 profile->priv_spec != env->priv_ver) { 769 profile_impl = false; 770 771 if (send_warn) { 772 warn_report("Profile %s requires priv spec %s, " 773 "but priv ver %s was set", profile->name, 774 cpu_priv_ver_to_str(profile->priv_spec), 775 cpu_priv_ver_to_str(env->priv_ver)); 776 } 777 } 778 779 for (i = 0; misa_bits[i] != 0; i++) { 780 uint32_t bit = misa_bits[i]; 781 782 if (!(profile->misa_ext & bit)) { 783 continue; 784 } 785 786 if (!riscv_has_ext(&cpu->env, bit)) { 787 profile_impl = false; 788 789 if (send_warn) { 790 warn_report(warn_msg, profile->name, 791 riscv_get_misa_ext_name(bit)); 792 } 793 } 794 } 795 796 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 797 int ext_offset = profile->ext_offsets[i]; 798 799 if (!isa_ext_is_enabled(cpu, ext_offset)) { 800 profile_impl = false; 801 802 if (send_warn) { 803 warn_report(warn_msg, profile->name, 804 cpu_cfg_ext_get_name(ext_offset)); 805 } 806 } 807 } 808 809 profile->enabled = profile_impl; 810 811 if (profile->parent != NULL) { 812 parent_enabled = object_property_get_bool(OBJECT(cpu), 813 profile->parent->name, 814 NULL); 815 profile->enabled = profile->enabled && parent_enabled; 816 } 817 } 818 819 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 820 { 821 for (int i = 0; riscv_profiles[i] != NULL; i++) { 822 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 823 } 824 } 825 826 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 827 { 828 CPURISCVState *env = &cpu->env; 829 Error *local_err = NULL; 830 831 riscv_cpu_validate_misa_priv(env, &local_err); 832 if (local_err != NULL) { 833 error_propagate(errp, local_err); 834 return; 835 } 836 837 riscv_cpu_update_named_features(cpu); 838 riscv_cpu_validate_profiles(cpu); 839 840 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 841 /* 842 * Enhanced PMP should only be available 843 * on harts with PMP support 844 */ 845 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 846 return; 847 } 848 849 riscv_cpu_validate_set_extensions(cpu, &local_err); 850 if (local_err != NULL) { 851 error_propagate(errp, local_err); 852 return; 853 } 854 } 855 856 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 857 { 858 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 859 } 860 861 static bool riscv_cpu_is_generic(Object *cpu_obj) 862 { 863 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 864 } 865 866 /* 867 * We'll get here via the following path: 868 * 869 * riscv_cpu_realize() 870 * -> cpu_exec_realizefn() 871 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 872 */ 873 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 874 { 875 RISCVCPU *cpu = RISCV_CPU(cs); 876 877 if (!riscv_cpu_tcg_compatible(cpu)) { 878 g_autofree char *name = riscv_cpu_get_name(cpu); 879 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 880 name); 881 return false; 882 } 883 884 #ifndef CONFIG_USER_ONLY 885 CPURISCVState *env = &cpu->env; 886 Error *local_err = NULL; 887 888 CPU(cs)->tcg_cflags |= CF_PCREL; 889 890 if (cpu->cfg.ext_sstc) { 891 riscv_timer_init(cpu); 892 } 893 894 if (cpu->cfg.pmu_mask) { 895 riscv_pmu_init(cpu, &local_err); 896 if (local_err != NULL) { 897 error_propagate(errp, local_err); 898 return false; 899 } 900 901 if (cpu->cfg.ext_sscofpmf) { 902 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 903 riscv_pmu_timer_cb, cpu); 904 } 905 } 906 907 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 908 if (riscv_has_ext(env, RVH)) { 909 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 910 } 911 #endif 912 913 return true; 914 } 915 916 typedef struct RISCVCPUMisaExtConfig { 917 target_ulong misa_bit; 918 bool enabled; 919 } RISCVCPUMisaExtConfig; 920 921 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 922 void *opaque, Error **errp) 923 { 924 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 925 target_ulong misa_bit = misa_ext_cfg->misa_bit; 926 RISCVCPU *cpu = RISCV_CPU(obj); 927 CPURISCVState *env = &cpu->env; 928 bool vendor_cpu = riscv_cpu_is_vendor(obj); 929 bool prev_val, value; 930 931 if (!visit_type_bool(v, name, &value, errp)) { 932 return; 933 } 934 935 cpu_misa_ext_add_user_opt(misa_bit, value); 936 937 prev_val = env->misa_ext & misa_bit; 938 939 if (value == prev_val) { 940 return; 941 } 942 943 if (value) { 944 if (vendor_cpu) { 945 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 946 error_setg(errp, "'%s' CPU does not allow enabling extensions", 947 cpuname); 948 return; 949 } 950 951 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 952 /* 953 * Note: the 'priv_spec' command line option, if present, 954 * will take precedence over this priv_ver bump. 955 */ 956 env->priv_ver = PRIV_VERSION_1_12_0; 957 } 958 } 959 960 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 961 } 962 963 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 964 void *opaque, Error **errp) 965 { 966 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 967 target_ulong misa_bit = misa_ext_cfg->misa_bit; 968 RISCVCPU *cpu = RISCV_CPU(obj); 969 CPURISCVState *env = &cpu->env; 970 bool value; 971 972 value = env->misa_ext & misa_bit; 973 974 visit_type_bool(v, name, &value, errp); 975 } 976 977 #define MISA_CFG(_bit, _enabled) \ 978 {.misa_bit = _bit, .enabled = _enabled} 979 980 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 981 MISA_CFG(RVA, true), 982 MISA_CFG(RVC, true), 983 MISA_CFG(RVD, true), 984 MISA_CFG(RVF, true), 985 MISA_CFG(RVI, true), 986 MISA_CFG(RVE, false), 987 MISA_CFG(RVM, true), 988 MISA_CFG(RVS, true), 989 MISA_CFG(RVU, true), 990 MISA_CFG(RVH, true), 991 MISA_CFG(RVJ, false), 992 MISA_CFG(RVV, false), 993 MISA_CFG(RVG, false), 994 MISA_CFG(RVB, false), 995 }; 996 997 /* 998 * We do not support user choice tracking for MISA 999 * extensions yet because, so far, we do not silently 1000 * change MISA bits during realize() (RVG enables MISA 1001 * bits but the user is warned about it). 1002 */ 1003 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1004 { 1005 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1006 int i; 1007 1008 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1009 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1010 int bit = misa_cfg->misa_bit; 1011 const char *name = riscv_get_misa_ext_name(bit); 1012 const char *desc = riscv_get_misa_ext_description(bit); 1013 1014 /* Check if KVM already created the property */ 1015 if (object_property_find(cpu_obj, name)) { 1016 continue; 1017 } 1018 1019 object_property_add(cpu_obj, name, "bool", 1020 cpu_get_misa_ext_cfg, 1021 cpu_set_misa_ext_cfg, 1022 NULL, (void *)misa_cfg); 1023 object_property_set_description(cpu_obj, name, desc); 1024 if (use_def_vals) { 1025 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1026 misa_cfg->enabled); 1027 } 1028 } 1029 } 1030 1031 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1032 void *opaque, Error **errp) 1033 { 1034 RISCVCPUProfile *profile = opaque; 1035 RISCVCPU *cpu = RISCV_CPU(obj); 1036 bool value; 1037 int i, ext_offset; 1038 1039 if (riscv_cpu_is_vendor(obj)) { 1040 error_setg(errp, "Profile %s is not available for vendor CPUs", 1041 profile->name); 1042 return; 1043 } 1044 1045 if (cpu->env.misa_mxl != MXL_RV64) { 1046 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1047 profile->name); 1048 return; 1049 } 1050 1051 if (!visit_type_bool(v, name, &value, errp)) { 1052 return; 1053 } 1054 1055 profile->user_set = true; 1056 profile->enabled = value; 1057 1058 if (profile->parent != NULL) { 1059 object_property_set_bool(obj, profile->parent->name, 1060 profile->enabled, NULL); 1061 } 1062 1063 if (profile->enabled) { 1064 cpu->env.priv_ver = profile->priv_spec; 1065 } 1066 1067 #ifndef CONFIG_USER_ONLY 1068 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1069 object_property_set_bool(obj, "mmu", true, NULL); 1070 const char *satp_prop = satp_mode_str(profile->satp_mode, 1071 riscv_cpu_is_32bit(cpu)); 1072 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1073 } 1074 #endif 1075 1076 for (i = 0; misa_bits[i] != 0; i++) { 1077 uint32_t bit = misa_bits[i]; 1078 1079 if (!(profile->misa_ext & bit)) { 1080 continue; 1081 } 1082 1083 if (bit == RVI && !profile->enabled) { 1084 /* 1085 * Disabling profiles will not disable the base 1086 * ISA RV64I. 1087 */ 1088 continue; 1089 } 1090 1091 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1092 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1093 } 1094 1095 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1096 ext_offset = profile->ext_offsets[i]; 1097 1098 if (profile->enabled) { 1099 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1100 riscv_cpu_enable_named_feat(cpu, ext_offset); 1101 } 1102 1103 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1104 } 1105 1106 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1107 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1108 } 1109 } 1110 1111 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1112 void *opaque, Error **errp) 1113 { 1114 RISCVCPUProfile *profile = opaque; 1115 bool value = profile->enabled; 1116 1117 visit_type_bool(v, name, &value, errp); 1118 } 1119 1120 static void riscv_cpu_add_profiles(Object *cpu_obj) 1121 { 1122 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1123 const RISCVCPUProfile *profile = riscv_profiles[i]; 1124 1125 object_property_add(cpu_obj, profile->name, "bool", 1126 cpu_get_profile, cpu_set_profile, 1127 NULL, (void *)profile); 1128 1129 /* 1130 * CPUs might enable a profile right from the start. 1131 * Enable its mandatory extensions right away in this 1132 * case. 1133 */ 1134 if (profile->enabled) { 1135 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1136 } 1137 } 1138 } 1139 1140 static bool cpu_ext_is_deprecated(const char *ext_name) 1141 { 1142 return isupper(ext_name[0]); 1143 } 1144 1145 /* 1146 * String will be allocated in the heap. Caller is responsible 1147 * for freeing it. 1148 */ 1149 static char *cpu_ext_to_lower(const char *ext_name) 1150 { 1151 char *ret = g_malloc0(strlen(ext_name) + 1); 1152 1153 strcpy(ret, ext_name); 1154 ret[0] = tolower(ret[0]); 1155 1156 return ret; 1157 } 1158 1159 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1160 void *opaque, Error **errp) 1161 { 1162 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1163 RISCVCPU *cpu = RISCV_CPU(obj); 1164 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1165 bool prev_val, value; 1166 1167 if (!visit_type_bool(v, name, &value, errp)) { 1168 return; 1169 } 1170 1171 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1172 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1173 1174 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1175 multi_ext_cfg->name, lower); 1176 } 1177 1178 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1179 1180 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1181 1182 if (value == prev_val) { 1183 return; 1184 } 1185 1186 if (value && vendor_cpu) { 1187 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1188 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1189 cpuname); 1190 return; 1191 } 1192 1193 if (value) { 1194 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1195 } 1196 1197 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1198 } 1199 1200 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1201 void *opaque, Error **errp) 1202 { 1203 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1204 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1205 1206 visit_type_bool(v, name, &value, errp); 1207 } 1208 1209 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1210 const RISCVCPUMultiExtConfig *multi_cfg) 1211 { 1212 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1213 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1214 1215 object_property_add(cpu_obj, multi_cfg->name, "bool", 1216 cpu_get_multi_ext_cfg, 1217 cpu_set_multi_ext_cfg, 1218 NULL, (void *)multi_cfg); 1219 1220 if (!generic_cpu || deprecated_ext) { 1221 return; 1222 } 1223 1224 /* 1225 * Set def val directly instead of using 1226 * object_property_set_bool() to save the set() 1227 * callback hash for user inputs. 1228 */ 1229 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1230 multi_cfg->enabled); 1231 } 1232 1233 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1234 const RISCVCPUMultiExtConfig *array) 1235 { 1236 const RISCVCPUMultiExtConfig *prop; 1237 1238 g_assert(array); 1239 1240 for (prop = array; prop && prop->name; prop++) { 1241 cpu_add_multi_ext_prop(obj, prop); 1242 } 1243 } 1244 1245 /* 1246 * Add CPU properties with user-facing flags. 1247 * 1248 * This will overwrite existing env->misa_ext values with the 1249 * defaults set via riscv_cpu_add_misa_properties(). 1250 */ 1251 static void riscv_cpu_add_user_properties(Object *obj) 1252 { 1253 #ifndef CONFIG_USER_ONLY 1254 riscv_add_satp_mode_properties(obj); 1255 #endif 1256 1257 riscv_cpu_add_misa_properties(obj); 1258 1259 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1260 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1261 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1262 1263 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1264 1265 riscv_cpu_add_profiles(obj); 1266 } 1267 1268 /* 1269 * The 'max' type CPU will have all possible ratified 1270 * non-vendor extensions enabled. 1271 */ 1272 static void riscv_init_max_cpu_extensions(Object *obj) 1273 { 1274 RISCVCPU *cpu = RISCV_CPU(obj); 1275 CPURISCVState *env = &cpu->env; 1276 const RISCVCPUMultiExtConfig *prop; 1277 1278 /* Enable RVG, RVJ and RVV that are disabled by default */ 1279 riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV); 1280 1281 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1282 isa_ext_update_enabled(cpu, prop->offset, true); 1283 } 1284 1285 /* 1286 * Some extensions can't be added without backward compatibilty concerns. 1287 * Disable those, the user can still opt in to them on the command line. 1288 */ 1289 cpu->cfg.ext_svade = false; 1290 1291 /* set vector version */ 1292 env->vext_ver = VEXT_VERSION_1_00_0; 1293 1294 /* Zfinx is not compatible with F. Disable it */ 1295 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1296 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1297 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1298 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1299 1300 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1301 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1302 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1303 1304 if (env->misa_mxl != MXL_RV32) { 1305 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1306 } 1307 } 1308 1309 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1310 { 1311 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1312 } 1313 1314 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1315 { 1316 RISCVCPU *cpu = RISCV_CPU(cs); 1317 Object *obj = OBJECT(cpu); 1318 1319 cpu->cfg.ext_always_enabled = true; 1320 1321 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1322 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1323 riscv_cpu_add_user_properties(obj); 1324 1325 if (riscv_cpu_has_max_extensions(obj)) { 1326 riscv_init_max_cpu_extensions(obj); 1327 } 1328 } 1329 1330 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1331 { 1332 /* 1333 * All cpus use the same set of operations. 1334 */ 1335 cc->tcg_ops = &riscv_tcg_ops; 1336 } 1337 1338 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1339 { 1340 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1341 } 1342 1343 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1344 { 1345 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1346 1347 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1348 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1349 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1350 } 1351 1352 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1353 .name = ACCEL_CPU_NAME("tcg"), 1354 1355 .parent = TYPE_ACCEL_CPU, 1356 .class_init = riscv_tcg_cpu_accel_class_init, 1357 .abstract = true, 1358 }; 1359 1360 static void riscv_tcg_cpu_accel_register_types(void) 1361 { 1362 type_register_static(&riscv_tcg_cpu_accel_type_info); 1363 } 1364 type_init(riscv_tcg_cpu_accel_register_types); 1365