1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "exec/translation-block.h" 23 #include "tcg-cpu.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "pmu.h" 27 #include "time_helper.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "qemu/accel.h" 31 #include "qemu/error-report.h" 32 #include "qemu/log.h" 33 #include "hw/core/accel-cpu.h" 34 #include "hw/core/tcg-cpu-ops.h" 35 #include "tcg/tcg.h" 36 #ifndef CONFIG_USER_ONLY 37 #include "hw/boards.h" 38 #endif 39 40 /* Hash that stores user set extensions */ 41 static GHashTable *multi_ext_user_opts; 42 static GHashTable *misa_ext_user_opts; 43 44 static GHashTable *multi_ext_implied_rules; 45 static GHashTable *misa_ext_implied_rules; 46 47 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 48 { 49 return g_hash_table_contains(multi_ext_user_opts, 50 GUINT_TO_POINTER(ext_offset)); 51 } 52 53 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 54 { 55 return g_hash_table_contains(misa_ext_user_opts, 56 GUINT_TO_POINTER(misa_bit)); 57 } 58 59 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 60 { 61 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 62 (gpointer)value); 63 } 64 65 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 66 { 67 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 68 (gpointer)value); 69 } 70 71 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 72 bool enabled) 73 { 74 CPURISCVState *env = &cpu->env; 75 76 if (enabled) { 77 env->misa_ext |= bit; 78 env->misa_ext_mask |= bit; 79 } else { 80 env->misa_ext &= ~bit; 81 env->misa_ext_mask &= ~bit; 82 } 83 } 84 85 static const char *cpu_priv_ver_to_str(int priv_ver) 86 { 87 const char *priv_spec_str = priv_spec_to_str(priv_ver); 88 89 g_assert(priv_spec_str); 90 91 return priv_spec_str; 92 } 93 94 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 95 const TranslationBlock *tb) 96 { 97 if (!(tb_cflags(tb) & CF_PCREL)) { 98 RISCVCPU *cpu = RISCV_CPU(cs); 99 CPURISCVState *env = &cpu->env; 100 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 101 102 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 103 104 if (xl == MXL_RV32) { 105 env->pc = (int32_t) tb->pc; 106 } else { 107 env->pc = tb->pc; 108 } 109 } 110 } 111 112 static void riscv_restore_state_to_opc(CPUState *cs, 113 const TranslationBlock *tb, 114 const uint64_t *data) 115 { 116 RISCVCPU *cpu = RISCV_CPU(cs); 117 CPURISCVState *env = &cpu->env; 118 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 119 target_ulong pc; 120 121 if (tb_cflags(tb) & CF_PCREL) { 122 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 123 } else { 124 pc = data[0]; 125 } 126 127 if (xl == MXL_RV32) { 128 env->pc = (int32_t)pc; 129 } else { 130 env->pc = pc; 131 } 132 env->bins = data[1]; 133 env->excp_uw2 = data[2]; 134 } 135 136 static const TCGCPUOps riscv_tcg_ops = { 137 .initialize = riscv_translate_init, 138 .translate_code = riscv_translate_code, 139 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 140 .restore_state_to_opc = riscv_restore_state_to_opc, 141 142 #ifndef CONFIG_USER_ONLY 143 .tlb_fill = riscv_cpu_tlb_fill, 144 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 145 .cpu_exec_halt = riscv_cpu_has_work, 146 .do_interrupt = riscv_cpu_do_interrupt, 147 .do_transaction_failed = riscv_cpu_do_transaction_failed, 148 .do_unaligned_access = riscv_cpu_do_unaligned_access, 149 .debug_excp_handler = riscv_cpu_debug_excp_handler, 150 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 151 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 152 #endif /* !CONFIG_USER_ONLY */ 153 }; 154 155 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 156 { 157 const RISCVIsaExtData *edata; 158 159 for (edata = isa_edata_arr; edata && edata->name; edata++) { 160 if (edata->ext_enable_offset != ext_offset) { 161 continue; 162 } 163 164 return edata->min_version; 165 } 166 167 g_assert_not_reached(); 168 } 169 170 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 171 { 172 const RISCVCPUMultiExtConfig *feat; 173 const RISCVIsaExtData *edata; 174 175 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 176 if (edata->ext_enable_offset == ext_offset) { 177 return edata->name; 178 } 179 } 180 181 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 182 if (feat->offset == ext_offset) { 183 return feat->name; 184 } 185 } 186 187 g_assert_not_reached(); 188 } 189 190 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 191 { 192 const RISCVCPUMultiExtConfig *feat; 193 194 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 195 if (feat->offset == ext_offset) { 196 return true; 197 } 198 } 199 200 return false; 201 } 202 203 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 204 { 205 /* 206 * All other named features are already enabled 207 * in riscv_tcg_cpu_instance_init(). 208 */ 209 switch (feat_offset) { 210 case CPU_CFG_OFFSET(ext_zic64b): 211 cpu->cfg.cbom_blocksize = 64; 212 cpu->cfg.cbop_blocksize = 64; 213 cpu->cfg.cboz_blocksize = 64; 214 break; 215 case CPU_CFG_OFFSET(ext_sha): 216 if (!cpu_misa_ext_is_user_set(RVH)) { 217 riscv_cpu_write_misa_bit(cpu, RVH, true); 218 } 219 /* fallthrough */ 220 case CPU_CFG_OFFSET(ext_ssstateen): 221 cpu->cfg.ext_smstateen = true; 222 break; 223 } 224 } 225 226 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 227 uint32_t ext_offset) 228 { 229 int ext_priv_ver; 230 231 if (env->priv_ver == PRIV_VERSION_LATEST) { 232 return; 233 } 234 235 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 236 237 if (env->priv_ver < ext_priv_ver) { 238 /* 239 * Note: the 'priv_spec' command line option, if present, 240 * will take precedence over this priv_ver bump. 241 */ 242 env->priv_ver = ext_priv_ver; 243 } 244 } 245 246 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 247 bool value) 248 { 249 CPURISCVState *env = &cpu->env; 250 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 251 int min_version; 252 253 if (prev_val == value) { 254 return; 255 } 256 257 if (cpu_cfg_ext_is_user_set(ext_offset)) { 258 return; 259 } 260 261 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 262 /* Do not enable it if priv_ver is older than min_version */ 263 min_version = cpu_cfg_ext_get_min_version(ext_offset); 264 if (env->priv_ver < min_version) { 265 return; 266 } 267 } 268 269 isa_ext_update_enabled(cpu, ext_offset, value); 270 } 271 272 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 273 { 274 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 275 error_setg(errp, "H extension requires priv spec 1.12.0"); 276 return; 277 } 278 } 279 280 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 281 Error **errp) 282 { 283 uint32_t vlen = cfg->vlenb << 3; 284 285 if (vlen > RV_VLEN_MAX || vlen < 128) { 286 error_setg(errp, 287 "Vector extension implementation only supports VLEN " 288 "in the range [128, %d]", RV_VLEN_MAX); 289 return; 290 } 291 292 if (cfg->elen > 64 || cfg->elen < 8) { 293 error_setg(errp, 294 "Vector extension implementation only supports ELEN " 295 "in the range [8, 64]"); 296 return; 297 } 298 } 299 300 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 301 { 302 CPURISCVState *env = &cpu->env; 303 const RISCVIsaExtData *edata; 304 305 /* Force disable extensions if priv spec version does not match */ 306 for (edata = isa_edata_arr; edata && edata->name; edata++) { 307 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 308 (env->priv_ver < edata->min_version)) { 309 /* 310 * These two extensions are always enabled as they were supported 311 * by QEMU before they were added as extensions in the ISA. 312 */ 313 if (!strcmp(edata->name, "zicntr") || 314 !strcmp(edata->name, "zihpm")) { 315 continue; 316 } 317 318 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 319 320 /* 321 * Do not show user warnings for named features that users 322 * can't enable/disable in the command line. See commit 323 * 68c9e54bea for more info. 324 */ 325 if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) { 326 continue; 327 } 328 #ifndef CONFIG_USER_ONLY 329 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 330 " because privilege spec version does not match", 331 edata->name, env->mhartid); 332 #else 333 warn_report("disabling %s extension because " 334 "privilege spec version does not match", 335 edata->name); 336 #endif 337 } 338 } 339 } 340 341 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 342 { 343 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { 344 cpu->cfg.has_priv_1_11 = true; 345 } 346 347 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { 348 cpu->cfg.has_priv_1_12 = true; 349 } 350 351 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { 352 cpu->cfg.has_priv_1_13 = true; 353 } 354 355 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && 356 cpu->cfg.cbop_blocksize == 64 && 357 cpu->cfg.cboz_blocksize == 64; 358 359 cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; 360 361 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && 362 cpu->cfg.ext_ssstateen; 363 } 364 365 static void riscv_cpu_validate_g(RISCVCPU *cpu) 366 { 367 const char *warn_msg = "RVG mandates disabled extension %s"; 368 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 369 bool send_warn = cpu_misa_ext_is_user_set(RVG); 370 371 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 372 uint32_t bit = g_misa_bits[i]; 373 374 if (riscv_has_ext(&cpu->env, bit)) { 375 continue; 376 } 377 378 if (!cpu_misa_ext_is_user_set(bit)) { 379 riscv_cpu_write_misa_bit(cpu, bit, true); 380 continue; 381 } 382 383 if (send_warn) { 384 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 385 } 386 } 387 388 if (!cpu->cfg.ext_zicsr) { 389 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 390 cpu->cfg.ext_zicsr = true; 391 } else if (send_warn) { 392 warn_report(warn_msg, "zicsr"); 393 } 394 } 395 396 if (!cpu->cfg.ext_zifencei) { 397 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 398 cpu->cfg.ext_zifencei = true; 399 } else if (send_warn) { 400 warn_report(warn_msg, "zifencei"); 401 } 402 } 403 } 404 405 static void riscv_cpu_validate_b(RISCVCPU *cpu) 406 { 407 const char *warn_msg = "RVB mandates disabled extension %s"; 408 409 if (!cpu->cfg.ext_zba) { 410 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 411 cpu->cfg.ext_zba = true; 412 } else { 413 warn_report(warn_msg, "zba"); 414 } 415 } 416 417 if (!cpu->cfg.ext_zbb) { 418 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 419 cpu->cfg.ext_zbb = true; 420 } else { 421 warn_report(warn_msg, "zbb"); 422 } 423 } 424 425 if (!cpu->cfg.ext_zbs) { 426 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 427 cpu->cfg.ext_zbs = true; 428 } else { 429 warn_report(warn_msg, "zbs"); 430 } 431 } 432 } 433 434 /* 435 * Check consistency between chosen extensions while setting 436 * cpu->cfg accordingly. 437 */ 438 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 439 { 440 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 441 CPURISCVState *env = &cpu->env; 442 Error *local_err = NULL; 443 444 if (riscv_has_ext(env, RVG)) { 445 riscv_cpu_validate_g(cpu); 446 } 447 448 if (riscv_has_ext(env, RVB)) { 449 riscv_cpu_validate_b(cpu); 450 } 451 452 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 453 error_setg(errp, 454 "I and E extensions are incompatible"); 455 return; 456 } 457 458 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 459 error_setg(errp, 460 "Either I or E extension must be set"); 461 return; 462 } 463 464 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 465 error_setg(errp, 466 "Setting S extension without U extension is illegal"); 467 return; 468 } 469 470 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 471 error_setg(errp, 472 "H depends on an I base integer ISA with 32 x registers"); 473 return; 474 } 475 476 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 477 error_setg(errp, "H extension implicitly requires S-mode"); 478 return; 479 } 480 481 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 482 error_setg(errp, "F extension requires Zicsr"); 483 return; 484 } 485 486 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 487 error_setg(errp, "Zacas extension requires A extension"); 488 return; 489 } 490 491 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 492 error_setg(errp, "Zawrs extension requires A extension"); 493 return; 494 } 495 496 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 497 error_setg(errp, "Zfa extension requires F extension"); 498 return; 499 } 500 501 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 502 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 503 return; 504 } 505 506 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 507 error_setg(errp, "Zfbfmin extension depends on F extension"); 508 return; 509 } 510 511 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 512 error_setg(errp, "D extension requires F extension"); 513 return; 514 } 515 516 if (riscv_has_ext(env, RVV)) { 517 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 518 if (local_err != NULL) { 519 error_propagate(errp, local_err); 520 return; 521 } 522 } 523 524 /* The Zve64d extension depends on the Zve64f extension */ 525 if (cpu->cfg.ext_zve64d) { 526 if (!riscv_has_ext(env, RVD)) { 527 error_setg(errp, "Zve64d/V extensions require D extension"); 528 return; 529 } 530 } 531 532 /* The Zve32f extension depends on the Zve32x extension */ 533 if (cpu->cfg.ext_zve32f) { 534 if (!riscv_has_ext(env, RVF)) { 535 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 536 return; 537 } 538 } 539 540 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 541 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 542 return; 543 } 544 545 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 546 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 547 return; 548 } 549 550 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 551 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 552 return; 553 } 554 555 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 556 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 557 return; 558 } 559 560 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 561 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 562 return; 563 } 564 565 if (cpu->cfg.ext_zfinx) { 566 if (!cpu->cfg.ext_zicsr) { 567 error_setg(errp, "Zfinx extension requires Zicsr"); 568 return; 569 } 570 if (riscv_has_ext(env, RVF)) { 571 error_setg(errp, 572 "Zfinx cannot be supported together with F extension"); 573 return; 574 } 575 } 576 577 if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { 578 error_setg(errp, "Zcmop extensions require Zca"); 579 return; 580 } 581 582 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 583 error_setg(errp, "Zcf extension is only relevant to RV32"); 584 return; 585 } 586 587 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 588 error_setg(errp, "Zcf extension requires F extension"); 589 return; 590 } 591 592 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 593 error_setg(errp, "Zcd extension requires D extension"); 594 return; 595 } 596 597 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 598 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 599 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 600 "extension"); 601 return; 602 } 603 604 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 605 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 606 "Zcd extension"); 607 return; 608 } 609 610 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 611 error_setg(errp, "Zcmt extension requires Zicsr extension"); 612 return; 613 } 614 615 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 616 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 617 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { 618 error_setg(errp, 619 "Vector crypto extensions require V or Zve* extensions"); 620 return; 621 } 622 623 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { 624 error_setg( 625 errp, 626 "Zvbc and Zvknhb extensions require V or Zve64x extensions"); 627 return; 628 } 629 630 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 631 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 632 error_setg(errp, "zicntr requires zicsr"); 633 return; 634 } 635 cpu->cfg.ext_zicntr = false; 636 } 637 638 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 639 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 640 error_setg(errp, "zihpm requires zicsr"); 641 return; 642 } 643 cpu->cfg.ext_zihpm = false; 644 } 645 646 if (cpu->cfg.ext_zicfiss) { 647 if (!cpu->cfg.ext_zicsr) { 648 error_setg(errp, "zicfiss extension requires zicsr extension"); 649 return; 650 } 651 if (!riscv_has_ext(env, RVA)) { 652 error_setg(errp, "zicfiss extension requires A extension"); 653 return; 654 } 655 if (!riscv_has_ext(env, RVS)) { 656 error_setg(errp, "zicfiss extension requires S"); 657 return; 658 } 659 if (!cpu->cfg.ext_zimop) { 660 error_setg(errp, "zicfiss extension requires zimop extension"); 661 return; 662 } 663 if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { 664 error_setg(errp, "zicfiss with zca requires zcmop extension"); 665 return; 666 } 667 } 668 669 if (!cpu->cfg.ext_zihpm) { 670 cpu->cfg.pmu_mask = 0; 671 cpu->pmu_avail_ctrs = 0; 672 } 673 674 if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { 675 error_setg(errp, "zicfilp extension requires zicsr extension"); 676 return; 677 } 678 679 if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { 680 error_setg(errp, "svukte is not supported for RV32"); 681 return; 682 } 683 684 /* 685 * Disable isa extensions based on priv spec after we 686 * validated and set everything we need. 687 */ 688 riscv_cpu_disable_priv_spec_isa_exts(cpu); 689 } 690 691 #ifndef CONFIG_USER_ONLY 692 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 693 RISCVCPUProfile *profile, 694 bool send_warn) 695 { 696 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 697 698 if (profile->satp_mode > satp_max) { 699 if (send_warn) { 700 bool is_32bit = riscv_cpu_is_32bit(cpu); 701 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 702 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 703 704 warn_report("Profile %s requires satp mode %s, " 705 "but satp mode %s was set", profile->name, 706 req_satp, cur_satp); 707 } 708 709 return false; 710 } 711 712 return true; 713 } 714 #endif 715 716 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 717 RISCVCPUProfile *profile) 718 { 719 CPURISCVState *env = &cpu->env; 720 const char *warn_msg = "Profile %s mandates disabled extension %s"; 721 bool send_warn = profile->user_set && profile->enabled; 722 bool parent_enabled, profile_impl = true; 723 int i; 724 725 #ifndef CONFIG_USER_ONLY 726 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 727 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 728 send_warn); 729 } 730 #endif 731 732 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 733 profile->priv_spec != env->priv_ver) { 734 profile_impl = false; 735 736 if (send_warn) { 737 warn_report("Profile %s requires priv spec %s, " 738 "but priv ver %s was set", profile->name, 739 cpu_priv_ver_to_str(profile->priv_spec), 740 cpu_priv_ver_to_str(env->priv_ver)); 741 } 742 } 743 744 for (i = 0; misa_bits[i] != 0; i++) { 745 uint32_t bit = misa_bits[i]; 746 747 if (!(profile->misa_ext & bit)) { 748 continue; 749 } 750 751 if (!riscv_has_ext(&cpu->env, bit)) { 752 profile_impl = false; 753 754 if (send_warn) { 755 warn_report(warn_msg, profile->name, 756 riscv_get_misa_ext_name(bit)); 757 } 758 } 759 } 760 761 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 762 int ext_offset = profile->ext_offsets[i]; 763 764 if (!isa_ext_is_enabled(cpu, ext_offset)) { 765 profile_impl = false; 766 767 if (send_warn) { 768 warn_report(warn_msg, profile->name, 769 cpu_cfg_ext_get_name(ext_offset)); 770 } 771 } 772 } 773 774 profile->enabled = profile_impl; 775 776 if (profile->parent != NULL) { 777 parent_enabled = object_property_get_bool(OBJECT(cpu), 778 profile->parent->name, 779 NULL); 780 profile->enabled = profile->enabled && parent_enabled; 781 } 782 } 783 784 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 785 { 786 for (int i = 0; riscv_profiles[i] != NULL; i++) { 787 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 788 } 789 } 790 791 static void riscv_cpu_init_implied_exts_rules(void) 792 { 793 RISCVCPUImpliedExtsRule *rule; 794 #ifndef CONFIG_USER_ONLY 795 MachineState *ms = MACHINE(qdev_get_machine()); 796 #endif 797 static bool initialized; 798 int i; 799 800 /* Implied rules only need to be initialized once. */ 801 if (initialized) { 802 return; 803 } 804 805 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 806 #ifndef CONFIG_USER_ONLY 807 rule->enabled = bitmap_new(ms->smp.cpus); 808 #endif 809 g_hash_table_insert(misa_ext_implied_rules, 810 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 811 } 812 813 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 814 #ifndef CONFIG_USER_ONLY 815 rule->enabled = bitmap_new(ms->smp.cpus); 816 #endif 817 g_hash_table_insert(multi_ext_implied_rules, 818 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 819 } 820 821 initialized = true; 822 } 823 824 static void cpu_enable_implied_rule(RISCVCPU *cpu, 825 RISCVCPUImpliedExtsRule *rule) 826 { 827 CPURISCVState *env = &cpu->env; 828 RISCVCPUImpliedExtsRule *ir; 829 bool enabled = false; 830 int i; 831 832 #ifndef CONFIG_USER_ONLY 833 enabled = test_bit(cpu->env.mhartid, rule->enabled); 834 #endif 835 836 if (!enabled) { 837 /* Enable the implied MISAs. */ 838 if (rule->implied_misa_exts) { 839 for (i = 0; misa_bits[i] != 0; i++) { 840 if (rule->implied_misa_exts & misa_bits[i]) { 841 /* 842 * If the user disabled the misa_bit do not re-enable it 843 * and do not apply any implied rules related to it. 844 */ 845 if (cpu_misa_ext_is_user_set(misa_bits[i]) && 846 !(env->misa_ext & misa_bits[i])) { 847 continue; 848 } 849 850 riscv_cpu_set_misa_ext(env, env->misa_ext | misa_bits[i]); 851 ir = g_hash_table_lookup(misa_ext_implied_rules, 852 GUINT_TO_POINTER(misa_bits[i])); 853 854 if (ir) { 855 cpu_enable_implied_rule(cpu, ir); 856 } 857 } 858 } 859 } 860 861 /* Enable the implied extensions. */ 862 for (i = 0; 863 rule->implied_multi_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) { 864 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); 865 866 ir = g_hash_table_lookup(multi_ext_implied_rules, 867 GUINT_TO_POINTER( 868 rule->implied_multi_exts[i])); 869 870 if (ir) { 871 cpu_enable_implied_rule(cpu, ir); 872 } 873 } 874 875 #ifndef CONFIG_USER_ONLY 876 bitmap_set(rule->enabled, cpu->env.mhartid, 1); 877 #endif 878 } 879 } 880 881 /* Zc extension has special implied rules that need to be handled separately. */ 882 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) 883 { 884 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 885 CPURISCVState *env = &cpu->env; 886 887 if (cpu->cfg.ext_zce) { 888 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 889 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 890 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 891 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 892 893 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 894 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 895 } 896 } 897 898 /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ 899 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 900 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 901 902 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 903 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 904 } 905 906 if (riscv_has_ext(env, RVD)) { 907 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 908 } 909 } 910 } 911 912 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) 913 { 914 RISCVCPUImpliedExtsRule *rule; 915 int i; 916 917 /* Enable the implied extensions for Zc. */ 918 cpu_enable_zc_implied_rules(cpu); 919 920 /* Enable the implied MISAs. */ 921 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 922 if (riscv_has_ext(&cpu->env, rule->ext)) { 923 cpu_enable_implied_rule(cpu, rule); 924 } 925 } 926 927 /* Enable the implied extensions. */ 928 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 929 if (isa_ext_is_enabled(cpu, rule->ext)) { 930 cpu_enable_implied_rule(cpu, rule); 931 } 932 } 933 } 934 935 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 936 { 937 CPURISCVState *env = &cpu->env; 938 Error *local_err = NULL; 939 940 riscv_cpu_init_implied_exts_rules(); 941 riscv_cpu_enable_implied_rules(cpu); 942 943 riscv_cpu_validate_misa_priv(env, &local_err); 944 if (local_err != NULL) { 945 error_propagate(errp, local_err); 946 return; 947 } 948 949 riscv_cpu_update_named_features(cpu); 950 riscv_cpu_validate_profiles(cpu); 951 952 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 953 /* 954 * Enhanced PMP should only be available 955 * on harts with PMP support 956 */ 957 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 958 return; 959 } 960 961 riscv_cpu_validate_set_extensions(cpu, &local_err); 962 if (local_err != NULL) { 963 error_propagate(errp, local_err); 964 return; 965 } 966 #ifndef CONFIG_USER_ONLY 967 if (cpu->cfg.pmu_mask) { 968 riscv_pmu_init(cpu, &local_err); 969 if (local_err != NULL) { 970 error_propagate(errp, local_err); 971 return; 972 } 973 974 if (cpu->cfg.ext_sscofpmf) { 975 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 976 riscv_pmu_timer_cb, cpu); 977 } 978 } 979 #endif 980 } 981 982 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) 983 { 984 GPtrArray *dynamic_decoders; 985 dynamic_decoders = g_ptr_array_sized_new(decoder_table_size); 986 for (size_t i = 0; i < decoder_table_size; ++i) { 987 if (decoder_table[i].guard_func && 988 decoder_table[i].guard_func(&cpu->cfg)) { 989 g_ptr_array_add(dynamic_decoders, 990 (gpointer)decoder_table[i].riscv_cpu_decode_fn); 991 } 992 } 993 994 cpu->decoders = dynamic_decoders; 995 } 996 997 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 998 { 999 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 1000 } 1001 1002 static bool riscv_cpu_is_generic(Object *cpu_obj) 1003 { 1004 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 1005 } 1006 1007 /* 1008 * We'll get here via the following path: 1009 * 1010 * riscv_cpu_realize() 1011 * -> cpu_exec_realizefn() 1012 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 1013 */ 1014 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 1015 { 1016 RISCVCPU *cpu = RISCV_CPU(cs); 1017 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 1018 1019 if (!riscv_cpu_tcg_compatible(cpu)) { 1020 g_autofree char *name = riscv_cpu_get_name(cpu); 1021 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 1022 name); 1023 return false; 1024 } 1025 1026 if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) { 1027 /* Missing 128-bit aligned atomics */ 1028 error_setg(errp, 1029 "128-bit RISC-V currently does not work with Multi " 1030 "Threaded TCG. Please use: -accel tcg,thread=single"); 1031 return false; 1032 } 1033 1034 #ifndef CONFIG_USER_ONLY 1035 CPURISCVState *env = &cpu->env; 1036 1037 tcg_cflags_set(CPU(cs), CF_PCREL); 1038 1039 if (cpu->cfg.ext_sstc) { 1040 riscv_timer_init(cpu); 1041 } 1042 1043 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 1044 if (riscv_has_ext(env, RVH)) { 1045 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 1046 } 1047 #endif 1048 1049 return true; 1050 } 1051 1052 typedef struct RISCVCPUMisaExtConfig { 1053 target_ulong misa_bit; 1054 bool enabled; 1055 } RISCVCPUMisaExtConfig; 1056 1057 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1058 void *opaque, Error **errp) 1059 { 1060 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1061 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1062 RISCVCPU *cpu = RISCV_CPU(obj); 1063 CPURISCVState *env = &cpu->env; 1064 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1065 bool prev_val, value; 1066 1067 if (!visit_type_bool(v, name, &value, errp)) { 1068 return; 1069 } 1070 1071 cpu_misa_ext_add_user_opt(misa_bit, value); 1072 1073 prev_val = env->misa_ext & misa_bit; 1074 1075 if (value == prev_val) { 1076 return; 1077 } 1078 1079 if (value) { 1080 if (vendor_cpu) { 1081 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1082 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1083 cpuname); 1084 return; 1085 } 1086 1087 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 1088 /* 1089 * Note: the 'priv_spec' command line option, if present, 1090 * will take precedence over this priv_ver bump. 1091 */ 1092 env->priv_ver = PRIV_VERSION_1_12_0; 1093 } 1094 } 1095 1096 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1097 } 1098 1099 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1100 void *opaque, Error **errp) 1101 { 1102 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1103 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1104 RISCVCPU *cpu = RISCV_CPU(obj); 1105 CPURISCVState *env = &cpu->env; 1106 bool value; 1107 1108 value = env->misa_ext & misa_bit; 1109 1110 visit_type_bool(v, name, &value, errp); 1111 } 1112 1113 #define MISA_CFG(_bit, _enabled) \ 1114 {.misa_bit = _bit, .enabled = _enabled} 1115 1116 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1117 MISA_CFG(RVA, true), 1118 MISA_CFG(RVC, true), 1119 MISA_CFG(RVD, true), 1120 MISA_CFG(RVF, true), 1121 MISA_CFG(RVI, true), 1122 MISA_CFG(RVE, false), 1123 MISA_CFG(RVM, true), 1124 MISA_CFG(RVS, true), 1125 MISA_CFG(RVU, true), 1126 MISA_CFG(RVH, true), 1127 MISA_CFG(RVV, false), 1128 MISA_CFG(RVG, false), 1129 MISA_CFG(RVB, false), 1130 }; 1131 1132 /* 1133 * We do not support user choice tracking for MISA 1134 * extensions yet because, so far, we do not silently 1135 * change MISA bits during realize() (RVG enables MISA 1136 * bits but the user is warned about it). 1137 */ 1138 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1139 { 1140 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1141 int i; 1142 1143 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1144 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1145 int bit = misa_cfg->misa_bit; 1146 const char *name = riscv_get_misa_ext_name(bit); 1147 const char *desc = riscv_get_misa_ext_description(bit); 1148 1149 /* Check if KVM already created the property */ 1150 if (object_property_find(cpu_obj, name)) { 1151 continue; 1152 } 1153 1154 object_property_add(cpu_obj, name, "bool", 1155 cpu_get_misa_ext_cfg, 1156 cpu_set_misa_ext_cfg, 1157 NULL, (void *)misa_cfg); 1158 object_property_set_description(cpu_obj, name, desc); 1159 if (use_def_vals) { 1160 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1161 misa_cfg->enabled); 1162 } 1163 } 1164 } 1165 1166 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1167 void *opaque, Error **errp) 1168 { 1169 RISCVCPUProfile *profile = opaque; 1170 RISCVCPU *cpu = RISCV_CPU(obj); 1171 bool value; 1172 int i, ext_offset; 1173 1174 if (riscv_cpu_is_vendor(obj)) { 1175 error_setg(errp, "Profile %s is not available for vendor CPUs", 1176 profile->name); 1177 return; 1178 } 1179 1180 if (cpu->env.misa_mxl != MXL_RV64) { 1181 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1182 profile->name); 1183 return; 1184 } 1185 1186 if (!visit_type_bool(v, name, &value, errp)) { 1187 return; 1188 } 1189 1190 profile->user_set = true; 1191 profile->enabled = value; 1192 1193 if (profile->parent != NULL) { 1194 object_property_set_bool(obj, profile->parent->name, 1195 profile->enabled, NULL); 1196 } 1197 1198 if (profile->enabled) { 1199 cpu->env.priv_ver = profile->priv_spec; 1200 } 1201 1202 #ifndef CONFIG_USER_ONLY 1203 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1204 object_property_set_bool(obj, "mmu", true, NULL); 1205 const char *satp_prop = satp_mode_str(profile->satp_mode, 1206 riscv_cpu_is_32bit(cpu)); 1207 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1208 } 1209 #endif 1210 1211 for (i = 0; misa_bits[i] != 0; i++) { 1212 uint32_t bit = misa_bits[i]; 1213 1214 if (!(profile->misa_ext & bit)) { 1215 continue; 1216 } 1217 1218 if (bit == RVI && !profile->enabled) { 1219 /* 1220 * Disabling profiles will not disable the base 1221 * ISA RV64I. 1222 */ 1223 continue; 1224 } 1225 1226 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1227 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1228 } 1229 1230 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1231 ext_offset = profile->ext_offsets[i]; 1232 1233 if (profile->enabled) { 1234 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1235 riscv_cpu_enable_named_feat(cpu, ext_offset); 1236 } 1237 1238 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1239 } 1240 1241 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1242 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1243 } 1244 } 1245 1246 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1247 void *opaque, Error **errp) 1248 { 1249 RISCVCPUProfile *profile = opaque; 1250 bool value = profile->enabled; 1251 1252 visit_type_bool(v, name, &value, errp); 1253 } 1254 1255 static void riscv_cpu_add_profiles(Object *cpu_obj) 1256 { 1257 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1258 const RISCVCPUProfile *profile = riscv_profiles[i]; 1259 1260 object_property_add(cpu_obj, profile->name, "bool", 1261 cpu_get_profile, cpu_set_profile, 1262 NULL, (void *)profile); 1263 1264 /* 1265 * CPUs might enable a profile right from the start. 1266 * Enable its mandatory extensions right away in this 1267 * case. 1268 */ 1269 if (profile->enabled) { 1270 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1271 } 1272 } 1273 } 1274 1275 static bool cpu_ext_is_deprecated(const char *ext_name) 1276 { 1277 return isupper(ext_name[0]); 1278 } 1279 1280 /* 1281 * String will be allocated in the heap. Caller is responsible 1282 * for freeing it. 1283 */ 1284 static char *cpu_ext_to_lower(const char *ext_name) 1285 { 1286 char *ret = g_malloc0(strlen(ext_name) + 1); 1287 1288 strcpy(ret, ext_name); 1289 ret[0] = tolower(ret[0]); 1290 1291 return ret; 1292 } 1293 1294 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1295 void *opaque, Error **errp) 1296 { 1297 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1298 RISCVCPU *cpu = RISCV_CPU(obj); 1299 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1300 bool prev_val, value; 1301 1302 if (!visit_type_bool(v, name, &value, errp)) { 1303 return; 1304 } 1305 1306 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1307 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1308 1309 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1310 multi_ext_cfg->name, lower); 1311 } 1312 1313 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1314 1315 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1316 1317 if (value == prev_val) { 1318 return; 1319 } 1320 1321 if (value && vendor_cpu) { 1322 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1323 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1324 cpuname); 1325 return; 1326 } 1327 1328 if (value) { 1329 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1330 } 1331 1332 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1333 } 1334 1335 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1336 void *opaque, Error **errp) 1337 { 1338 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1339 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1340 1341 visit_type_bool(v, name, &value, errp); 1342 } 1343 1344 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1345 const RISCVCPUMultiExtConfig *multi_cfg) 1346 { 1347 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1348 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1349 1350 object_property_add(cpu_obj, multi_cfg->name, "bool", 1351 cpu_get_multi_ext_cfg, 1352 cpu_set_multi_ext_cfg, 1353 NULL, (void *)multi_cfg); 1354 1355 if (!generic_cpu || deprecated_ext) { 1356 return; 1357 } 1358 1359 /* 1360 * Set def val directly instead of using 1361 * object_property_set_bool() to save the set() 1362 * callback hash for user inputs. 1363 */ 1364 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1365 multi_cfg->enabled); 1366 } 1367 1368 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1369 const RISCVCPUMultiExtConfig *array) 1370 { 1371 const RISCVCPUMultiExtConfig *prop; 1372 1373 g_assert(array); 1374 1375 for (prop = array; prop && prop->name; prop++) { 1376 cpu_add_multi_ext_prop(obj, prop); 1377 } 1378 } 1379 1380 /* 1381 * Add CPU properties with user-facing flags. 1382 * 1383 * This will overwrite existing env->misa_ext values with the 1384 * defaults set via riscv_cpu_add_misa_properties(). 1385 */ 1386 static void riscv_cpu_add_user_properties(Object *obj) 1387 { 1388 #ifndef CONFIG_USER_ONLY 1389 riscv_add_satp_mode_properties(obj); 1390 #endif 1391 1392 riscv_cpu_add_misa_properties(obj); 1393 1394 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1395 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1396 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1397 1398 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1399 1400 riscv_cpu_add_profiles(obj); 1401 } 1402 1403 /* 1404 * The 'max' type CPU will have all possible ratified 1405 * non-vendor extensions enabled. 1406 */ 1407 static void riscv_init_max_cpu_extensions(Object *obj) 1408 { 1409 RISCVCPU *cpu = RISCV_CPU(obj); 1410 CPURISCVState *env = &cpu->env; 1411 const RISCVCPUMultiExtConfig *prop; 1412 1413 /* Enable RVG and RVV that are disabled by default */ 1414 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); 1415 1416 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1417 isa_ext_update_enabled(cpu, prop->offset, true); 1418 } 1419 1420 /* 1421 * Some extensions can't be added without backward compatibilty concerns. 1422 * Disable those, the user can still opt in to them on the command line. 1423 */ 1424 cpu->cfg.ext_svade = false; 1425 1426 /* set vector version */ 1427 env->vext_ver = VEXT_VERSION_1_00_0; 1428 1429 /* Zfinx is not compatible with F. Disable it */ 1430 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1431 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1432 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1433 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1434 1435 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1436 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1437 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1438 1439 if (env->misa_mxl != MXL_RV32) { 1440 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1441 } 1442 1443 /* 1444 * ext_smrnmi requires OpenSBI changes that our current 1445 * image does not have. Disable it for now. 1446 */ 1447 if (cpu->cfg.ext_smrnmi) { 1448 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); 1449 qemu_log("Smrnmi is disabled in the 'max' type CPU\n"); 1450 } 1451 1452 /* 1453 * ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup to 1454 * avoid generating a double trap. OpenSBI does not currently support it, 1455 * disable it for now. 1456 */ 1457 if (cpu->cfg.ext_smdbltrp) { 1458 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); 1459 qemu_log("Smdbltrp is disabled in the 'max' type CPU\n"); 1460 } 1461 } 1462 1463 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1464 { 1465 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1466 } 1467 1468 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1469 { 1470 RISCVCPU *cpu = RISCV_CPU(cs); 1471 Object *obj = OBJECT(cpu); 1472 1473 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1474 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1475 1476 if (!misa_ext_implied_rules) { 1477 misa_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1478 } 1479 1480 if (!multi_ext_implied_rules) { 1481 multi_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1482 } 1483 1484 riscv_cpu_add_user_properties(obj); 1485 1486 if (riscv_cpu_has_max_extensions(obj)) { 1487 riscv_init_max_cpu_extensions(obj); 1488 } 1489 } 1490 1491 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1492 { 1493 /* 1494 * All cpus use the same set of operations. 1495 */ 1496 cc->tcg_ops = &riscv_tcg_ops; 1497 } 1498 1499 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1500 { 1501 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1502 } 1503 1504 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1505 { 1506 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1507 1508 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1509 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1510 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1511 } 1512 1513 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1514 .name = ACCEL_CPU_NAME("tcg"), 1515 1516 .parent = TYPE_ACCEL_CPU, 1517 .class_init = riscv_tcg_cpu_accel_class_init, 1518 .abstract = true, 1519 }; 1520 1521 static void riscv_tcg_cpu_accel_register_types(void) 1522 { 1523 type_register_static(&riscv_tcg_cpu_accel_type_info); 1524 } 1525 type_init(riscv_tcg_cpu_accel_register_types); 1526