1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "tcg-cpu.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "time_helper.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "qemu/accel.h" 29 #include "qemu/error-report.h" 30 #include "qemu/log.h" 31 #include "hw/core/accel-cpu.h" 32 #include "hw/core/tcg-cpu-ops.h" 33 #include "tcg/tcg.h" 34 35 /* Hash that stores user set extensions */ 36 static GHashTable *multi_ext_user_opts; 37 static GHashTable *misa_ext_user_opts; 38 39 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 40 { 41 return g_hash_table_contains(multi_ext_user_opts, 42 GUINT_TO_POINTER(ext_offset)); 43 } 44 45 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 46 { 47 return g_hash_table_contains(misa_ext_user_opts, 48 GUINT_TO_POINTER(misa_bit)); 49 } 50 51 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 52 { 53 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 54 (gpointer)value); 55 } 56 57 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 58 { 59 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 60 (gpointer)value); 61 } 62 63 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 64 bool enabled) 65 { 66 CPURISCVState *env = &cpu->env; 67 68 if (enabled) { 69 env->misa_ext |= bit; 70 env->misa_ext_mask |= bit; 71 } else { 72 env->misa_ext &= ~bit; 73 env->misa_ext_mask &= ~bit; 74 } 75 } 76 77 static const char *cpu_priv_ver_to_str(int priv_ver) 78 { 79 switch (priv_ver) { 80 case PRIV_VERSION_1_10_0: 81 return "v1.10.0"; 82 case PRIV_VERSION_1_11_0: 83 return "v1.11.0"; 84 case PRIV_VERSION_1_12_0: 85 return "v1.12.0"; 86 } 87 88 g_assert_not_reached(); 89 } 90 91 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 92 const TranslationBlock *tb) 93 { 94 if (!(tb_cflags(tb) & CF_PCREL)) { 95 RISCVCPU *cpu = RISCV_CPU(cs); 96 CPURISCVState *env = &cpu->env; 97 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 98 99 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 100 101 if (xl == MXL_RV32) { 102 env->pc = (int32_t) tb->pc; 103 } else { 104 env->pc = tb->pc; 105 } 106 } 107 } 108 109 static void riscv_restore_state_to_opc(CPUState *cs, 110 const TranslationBlock *tb, 111 const uint64_t *data) 112 { 113 RISCVCPU *cpu = RISCV_CPU(cs); 114 CPURISCVState *env = &cpu->env; 115 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 116 target_ulong pc; 117 118 if (tb_cflags(tb) & CF_PCREL) { 119 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 120 } else { 121 pc = data[0]; 122 } 123 124 if (xl == MXL_RV32) { 125 env->pc = (int32_t)pc; 126 } else { 127 env->pc = pc; 128 } 129 env->bins = data[1]; 130 } 131 132 static const TCGCPUOps riscv_tcg_ops = { 133 .initialize = riscv_translate_init, 134 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 135 .restore_state_to_opc = riscv_restore_state_to_opc, 136 137 #ifndef CONFIG_USER_ONLY 138 .tlb_fill = riscv_cpu_tlb_fill, 139 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 140 .do_interrupt = riscv_cpu_do_interrupt, 141 .do_transaction_failed = riscv_cpu_do_transaction_failed, 142 .do_unaligned_access = riscv_cpu_do_unaligned_access, 143 .debug_excp_handler = riscv_cpu_debug_excp_handler, 144 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 145 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 146 #endif /* !CONFIG_USER_ONLY */ 147 }; 148 149 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 150 { 151 const RISCVIsaExtData *edata; 152 153 for (edata = isa_edata_arr; edata && edata->name; edata++) { 154 if (edata->ext_enable_offset != ext_offset) { 155 continue; 156 } 157 158 return edata->min_version; 159 } 160 161 g_assert_not_reached(); 162 } 163 164 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 165 { 166 const RISCVCPUMultiExtConfig *feat; 167 const RISCVIsaExtData *edata; 168 169 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 170 if (edata->ext_enable_offset == ext_offset) { 171 return edata->name; 172 } 173 } 174 175 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 176 if (feat->offset == ext_offset) { 177 return feat->name; 178 } 179 } 180 181 g_assert_not_reached(); 182 } 183 184 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 185 { 186 const RISCVCPUMultiExtConfig *feat; 187 188 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 189 if (feat->offset == ext_offset) { 190 return true; 191 } 192 } 193 194 return false; 195 } 196 197 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 198 { 199 switch (feat_offset) { 200 case CPU_CFG_OFFSET(zic64b): 201 cpu->cfg.cbom_blocksize = 64; 202 cpu->cfg.cbop_blocksize = 64; 203 cpu->cfg.cboz_blocksize = 64; 204 break; 205 case CPU_CFG_OFFSET(svade): 206 cpu->cfg.ext_svadu = false; 207 break; 208 default: 209 g_assert_not_reached(); 210 } 211 } 212 213 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 214 uint32_t ext_offset) 215 { 216 int ext_priv_ver; 217 218 if (env->priv_ver == PRIV_VERSION_LATEST) { 219 return; 220 } 221 222 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 223 return; 224 } 225 226 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 227 228 if (env->priv_ver < ext_priv_ver) { 229 /* 230 * Note: the 'priv_spec' command line option, if present, 231 * will take precedence over this priv_ver bump. 232 */ 233 env->priv_ver = ext_priv_ver; 234 } 235 } 236 237 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 238 bool value) 239 { 240 CPURISCVState *env = &cpu->env; 241 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 242 int min_version; 243 244 if (prev_val == value) { 245 return; 246 } 247 248 if (cpu_cfg_ext_is_user_set(ext_offset)) { 249 return; 250 } 251 252 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 253 /* Do not enable it if priv_ver is older than min_version */ 254 min_version = cpu_cfg_ext_get_min_version(ext_offset); 255 if (env->priv_ver < min_version) { 256 return; 257 } 258 } 259 260 isa_ext_update_enabled(cpu, ext_offset, value); 261 } 262 263 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 264 { 265 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 266 error_setg(errp, "H extension requires priv spec 1.12.0"); 267 return; 268 } 269 } 270 271 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 272 Error **errp) 273 { 274 uint32_t vlen = cfg->vlenb << 3; 275 276 if (vlen > RV_VLEN_MAX || vlen < 128) { 277 error_setg(errp, 278 "Vector extension implementation only supports VLEN " 279 "in the range [128, %d]", RV_VLEN_MAX); 280 return; 281 } 282 283 if (cfg->elen > 64 || cfg->elen < 8) { 284 error_setg(errp, 285 "Vector extension implementation only supports ELEN " 286 "in the range [8, 64]"); 287 return; 288 } 289 } 290 291 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 292 { 293 CPURISCVState *env = &cpu->env; 294 const RISCVIsaExtData *edata; 295 296 /* Force disable extensions if priv spec version does not match */ 297 for (edata = isa_edata_arr; edata && edata->name; edata++) { 298 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 299 (env->priv_ver < edata->min_version)) { 300 /* 301 * These two extensions are always enabled as they were supported 302 * by QEMU before they were added as extensions in the ISA. 303 */ 304 if (!strcmp(edata->name, "zicntr") || 305 !strcmp(edata->name, "zihpm")) { 306 continue; 307 } 308 309 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 310 #ifndef CONFIG_USER_ONLY 311 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 312 " because privilege spec version does not match", 313 edata->name, env->mhartid); 314 #else 315 warn_report("disabling %s extension because " 316 "privilege spec version does not match", 317 edata->name); 318 #endif 319 } 320 } 321 } 322 323 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 324 { 325 cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 && 326 cpu->cfg.cbop_blocksize == 64 && 327 cpu->cfg.cboz_blocksize == 64; 328 329 cpu->cfg.svade = !cpu->cfg.ext_svadu; 330 } 331 332 static void riscv_cpu_validate_g(RISCVCPU *cpu) 333 { 334 const char *warn_msg = "RVG mandates disabled extension %s"; 335 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 336 bool send_warn = cpu_misa_ext_is_user_set(RVG); 337 338 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 339 uint32_t bit = g_misa_bits[i]; 340 341 if (riscv_has_ext(&cpu->env, bit)) { 342 continue; 343 } 344 345 if (!cpu_misa_ext_is_user_set(bit)) { 346 riscv_cpu_write_misa_bit(cpu, bit, true); 347 continue; 348 } 349 350 if (send_warn) { 351 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 352 } 353 } 354 355 if (!cpu->cfg.ext_zicsr) { 356 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 357 cpu->cfg.ext_zicsr = true; 358 } else if (send_warn) { 359 warn_report(warn_msg, "zicsr"); 360 } 361 } 362 363 if (!cpu->cfg.ext_zifencei) { 364 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 365 cpu->cfg.ext_zifencei = true; 366 } else if (send_warn) { 367 warn_report(warn_msg, "zifencei"); 368 } 369 } 370 } 371 372 static void riscv_cpu_validate_b(RISCVCPU *cpu) 373 { 374 const char *warn_msg = "RVB mandates disabled extension %s"; 375 376 if (!cpu->cfg.ext_zba) { 377 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 378 cpu->cfg.ext_zba = true; 379 } else { 380 warn_report(warn_msg, "zba"); 381 } 382 } 383 384 if (!cpu->cfg.ext_zbb) { 385 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 386 cpu->cfg.ext_zbb = true; 387 } else { 388 warn_report(warn_msg, "zbb"); 389 } 390 } 391 392 if (!cpu->cfg.ext_zbs) { 393 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 394 cpu->cfg.ext_zbs = true; 395 } else { 396 warn_report(warn_msg, "zbs"); 397 } 398 } 399 } 400 401 /* 402 * Check consistency between chosen extensions while setting 403 * cpu->cfg accordingly. 404 */ 405 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 406 { 407 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 408 CPURISCVState *env = &cpu->env; 409 Error *local_err = NULL; 410 411 if (riscv_has_ext(env, RVG)) { 412 riscv_cpu_validate_g(cpu); 413 } 414 415 if (riscv_has_ext(env, RVB)) { 416 riscv_cpu_validate_b(cpu); 417 } 418 419 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 420 error_setg(errp, 421 "I and E extensions are incompatible"); 422 return; 423 } 424 425 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 426 error_setg(errp, 427 "Either I or E extension must be set"); 428 return; 429 } 430 431 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 432 error_setg(errp, 433 "Setting S extension without U extension is illegal"); 434 return; 435 } 436 437 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 438 error_setg(errp, 439 "H depends on an I base integer ISA with 32 x registers"); 440 return; 441 } 442 443 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 444 error_setg(errp, "H extension implicitly requires S-mode"); 445 return; 446 } 447 448 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 449 error_setg(errp, "F extension requires Zicsr"); 450 return; 451 } 452 453 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 454 error_setg(errp, "Zacas extension requires A extension"); 455 return; 456 } 457 458 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 459 error_setg(errp, "Zawrs extension requires A extension"); 460 return; 461 } 462 463 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 464 error_setg(errp, "Zfa extension requires F extension"); 465 return; 466 } 467 468 if (cpu->cfg.ext_zfh) { 469 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); 470 } 471 472 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 473 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 474 return; 475 } 476 477 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 478 error_setg(errp, "Zfbfmin extension depends on F extension"); 479 return; 480 } 481 482 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 483 error_setg(errp, "D extension requires F extension"); 484 return; 485 } 486 487 if (riscv_has_ext(env, RVV)) { 488 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 489 if (local_err != NULL) { 490 error_propagate(errp, local_err); 491 return; 492 } 493 494 /* The V vector extension depends on the Zve64d extension */ 495 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); 496 } 497 498 /* The Zve64d extension depends on the Zve64f extension */ 499 if (cpu->cfg.ext_zve64d) { 500 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); 501 } 502 503 /* The Zve64f extension depends on the Zve32f extension */ 504 if (cpu->cfg.ext_zve64f) { 505 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); 506 } 507 508 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 509 error_setg(errp, "Zve64d/V extensions require D extension"); 510 return; 511 } 512 513 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 514 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 515 return; 516 } 517 518 if (cpu->cfg.ext_zvfh) { 519 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); 520 } 521 522 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 523 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 524 return; 525 } 526 527 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 528 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 529 return; 530 } 531 532 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { 533 error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"); 534 return; 535 } 536 537 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 538 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 539 return; 540 } 541 542 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 543 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 544 return; 545 } 546 547 /* Set the ISA extensions, checks should have happened above */ 548 if (cpu->cfg.ext_zhinx) { 549 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 550 } 551 552 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 553 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 554 return; 555 } 556 557 if (cpu->cfg.ext_zfinx) { 558 if (!cpu->cfg.ext_zicsr) { 559 error_setg(errp, "Zfinx extension requires Zicsr"); 560 return; 561 } 562 if (riscv_has_ext(env, RVF)) { 563 error_setg(errp, 564 "Zfinx cannot be supported together with F extension"); 565 return; 566 } 567 } 568 569 if (cpu->cfg.ext_zce) { 570 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 571 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 572 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 573 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 574 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 575 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 576 } 577 } 578 579 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ 580 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 581 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 582 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 583 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 584 } 585 if (riscv_has_ext(env, RVD)) { 586 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 587 } 588 } 589 590 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 591 error_setg(errp, "Zcf extension is only relevant to RV32"); 592 return; 593 } 594 595 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 596 error_setg(errp, "Zcf extension requires F extension"); 597 return; 598 } 599 600 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 601 error_setg(errp, "Zcd extension requires D extension"); 602 return; 603 } 604 605 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 606 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 607 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 608 "extension"); 609 return; 610 } 611 612 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 613 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 614 "Zcd extension"); 615 return; 616 } 617 618 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 619 error_setg(errp, "Zcmt extension requires Zicsr extension"); 620 return; 621 } 622 623 /* 624 * Shorthand vector crypto extensions 625 */ 626 if (cpu->cfg.ext_zvknc) { 627 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); 628 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 629 } 630 631 if (cpu->cfg.ext_zvkng) { 632 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); 633 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); 634 } 635 636 if (cpu->cfg.ext_zvkn) { 637 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true); 638 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true); 639 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); 640 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); 641 } 642 643 if (cpu->cfg.ext_zvksc) { 644 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); 645 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 646 } 647 648 if (cpu->cfg.ext_zvksg) { 649 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); 650 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); 651 } 652 653 if (cpu->cfg.ext_zvks) { 654 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true); 655 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true); 656 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); 657 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); 658 } 659 660 if (cpu->cfg.ext_zvkt) { 661 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); 662 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 663 } 664 665 /* 666 * In principle Zve*x would also suffice here, were they supported 667 * in qemu 668 */ 669 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 670 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 671 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { 672 error_setg(errp, 673 "Vector crypto extensions require V or Zve* extensions"); 674 return; 675 } 676 677 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) { 678 error_setg( 679 errp, 680 "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions"); 681 return; 682 } 683 684 if (cpu->cfg.ext_zk) { 685 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); 686 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); 687 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); 688 } 689 690 if (cpu->cfg.ext_zkn) { 691 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 692 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 693 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 694 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); 695 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); 696 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); 697 } 698 699 if (cpu->cfg.ext_zks) { 700 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 701 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 702 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 703 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); 704 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); 705 } 706 707 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 708 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 709 error_setg(errp, "zicntr requires zicsr"); 710 return; 711 } 712 cpu->cfg.ext_zicntr = false; 713 } 714 715 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 716 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 717 error_setg(errp, "zihpm requires zicsr"); 718 return; 719 } 720 cpu->cfg.ext_zihpm = false; 721 } 722 723 if (!cpu->cfg.ext_zihpm) { 724 cpu->cfg.pmu_mask = 0; 725 cpu->pmu_avail_ctrs = 0; 726 } 727 728 /* 729 * Disable isa extensions based on priv spec after we 730 * validated and set everything we need. 731 */ 732 riscv_cpu_disable_priv_spec_isa_exts(cpu); 733 } 734 735 #ifndef CONFIG_USER_ONLY 736 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 737 RISCVCPUProfile *profile, 738 bool send_warn) 739 { 740 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 741 742 if (profile->satp_mode > satp_max) { 743 if (send_warn) { 744 bool is_32bit = riscv_cpu_is_32bit(cpu); 745 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 746 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 747 748 warn_report("Profile %s requires satp mode %s, " 749 "but satp mode %s was set", profile->name, 750 req_satp, cur_satp); 751 } 752 753 return false; 754 } 755 756 return true; 757 } 758 #endif 759 760 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 761 RISCVCPUProfile *profile) 762 { 763 CPURISCVState *env = &cpu->env; 764 const char *warn_msg = "Profile %s mandates disabled extension %s"; 765 bool send_warn = profile->user_set && profile->enabled; 766 bool parent_enabled, profile_impl = true; 767 int i; 768 769 #ifndef CONFIG_USER_ONLY 770 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 771 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 772 send_warn); 773 } 774 #endif 775 776 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 777 profile->priv_spec != env->priv_ver) { 778 profile_impl = false; 779 780 if (send_warn) { 781 warn_report("Profile %s requires priv spec %s, " 782 "but priv ver %s was set", profile->name, 783 cpu_priv_ver_to_str(profile->priv_spec), 784 cpu_priv_ver_to_str(env->priv_ver)); 785 } 786 } 787 788 for (i = 0; misa_bits[i] != 0; i++) { 789 uint32_t bit = misa_bits[i]; 790 791 if (!(profile->misa_ext & bit)) { 792 continue; 793 } 794 795 if (!riscv_has_ext(&cpu->env, bit)) { 796 profile_impl = false; 797 798 if (send_warn) { 799 warn_report(warn_msg, profile->name, 800 riscv_get_misa_ext_name(bit)); 801 } 802 } 803 } 804 805 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 806 int ext_offset = profile->ext_offsets[i]; 807 808 if (!isa_ext_is_enabled(cpu, ext_offset)) { 809 profile_impl = false; 810 811 if (send_warn) { 812 warn_report(warn_msg, profile->name, 813 cpu_cfg_ext_get_name(ext_offset)); 814 } 815 } 816 } 817 818 profile->enabled = profile_impl; 819 820 if (profile->parent != NULL) { 821 parent_enabled = object_property_get_bool(OBJECT(cpu), 822 profile->parent->name, 823 NULL); 824 profile->enabled = profile->enabled && parent_enabled; 825 } 826 } 827 828 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 829 { 830 for (int i = 0; riscv_profiles[i] != NULL; i++) { 831 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 832 } 833 } 834 835 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 836 { 837 CPURISCVState *env = &cpu->env; 838 Error *local_err = NULL; 839 840 riscv_cpu_validate_misa_priv(env, &local_err); 841 if (local_err != NULL) { 842 error_propagate(errp, local_err); 843 return; 844 } 845 846 riscv_cpu_update_named_features(cpu); 847 riscv_cpu_validate_profiles(cpu); 848 849 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 850 /* 851 * Enhanced PMP should only be available 852 * on harts with PMP support 853 */ 854 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 855 return; 856 } 857 858 riscv_cpu_validate_set_extensions(cpu, &local_err); 859 if (local_err != NULL) { 860 error_propagate(errp, local_err); 861 return; 862 } 863 } 864 865 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 866 { 867 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 868 } 869 870 static bool riscv_cpu_is_generic(Object *cpu_obj) 871 { 872 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 873 } 874 875 /* 876 * We'll get here via the following path: 877 * 878 * riscv_cpu_realize() 879 * -> cpu_exec_realizefn() 880 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 881 */ 882 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 883 { 884 RISCVCPU *cpu = RISCV_CPU(cs); 885 886 if (!riscv_cpu_tcg_compatible(cpu)) { 887 g_autofree char *name = riscv_cpu_get_name(cpu); 888 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 889 name); 890 return false; 891 } 892 893 #ifndef CONFIG_USER_ONLY 894 CPURISCVState *env = &cpu->env; 895 Error *local_err = NULL; 896 897 CPU(cs)->tcg_cflags |= CF_PCREL; 898 899 if (cpu->cfg.ext_sstc) { 900 riscv_timer_init(cpu); 901 } 902 903 if (cpu->cfg.pmu_mask) { 904 riscv_pmu_init(cpu, &local_err); 905 if (local_err != NULL) { 906 error_propagate(errp, local_err); 907 return false; 908 } 909 910 if (cpu->cfg.ext_sscofpmf) { 911 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 912 riscv_pmu_timer_cb, cpu); 913 } 914 } 915 916 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 917 if (riscv_has_ext(env, RVH)) { 918 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 919 } 920 #endif 921 922 return true; 923 } 924 925 typedef struct RISCVCPUMisaExtConfig { 926 target_ulong misa_bit; 927 bool enabled; 928 } RISCVCPUMisaExtConfig; 929 930 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 931 void *opaque, Error **errp) 932 { 933 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 934 target_ulong misa_bit = misa_ext_cfg->misa_bit; 935 RISCVCPU *cpu = RISCV_CPU(obj); 936 CPURISCVState *env = &cpu->env; 937 bool vendor_cpu = riscv_cpu_is_vendor(obj); 938 bool prev_val, value; 939 940 if (!visit_type_bool(v, name, &value, errp)) { 941 return; 942 } 943 944 cpu_misa_ext_add_user_opt(misa_bit, value); 945 946 prev_val = env->misa_ext & misa_bit; 947 948 if (value == prev_val) { 949 return; 950 } 951 952 if (value) { 953 if (vendor_cpu) { 954 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 955 error_setg(errp, "'%s' CPU does not allow enabling extensions", 956 cpuname); 957 return; 958 } 959 960 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 961 /* 962 * Note: the 'priv_spec' command line option, if present, 963 * will take precedence over this priv_ver bump. 964 */ 965 env->priv_ver = PRIV_VERSION_1_12_0; 966 } 967 } 968 969 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 970 } 971 972 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 973 void *opaque, Error **errp) 974 { 975 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 976 target_ulong misa_bit = misa_ext_cfg->misa_bit; 977 RISCVCPU *cpu = RISCV_CPU(obj); 978 CPURISCVState *env = &cpu->env; 979 bool value; 980 981 value = env->misa_ext & misa_bit; 982 983 visit_type_bool(v, name, &value, errp); 984 } 985 986 #define MISA_CFG(_bit, _enabled) \ 987 {.misa_bit = _bit, .enabled = _enabled} 988 989 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 990 MISA_CFG(RVA, true), 991 MISA_CFG(RVC, true), 992 MISA_CFG(RVD, true), 993 MISA_CFG(RVF, true), 994 MISA_CFG(RVI, true), 995 MISA_CFG(RVE, false), 996 MISA_CFG(RVM, true), 997 MISA_CFG(RVS, true), 998 MISA_CFG(RVU, true), 999 MISA_CFG(RVH, true), 1000 MISA_CFG(RVJ, false), 1001 MISA_CFG(RVV, false), 1002 MISA_CFG(RVG, false), 1003 MISA_CFG(RVB, false), 1004 }; 1005 1006 /* 1007 * We do not support user choice tracking for MISA 1008 * extensions yet because, so far, we do not silently 1009 * change MISA bits during realize() (RVG enables MISA 1010 * bits but the user is warned about it). 1011 */ 1012 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1013 { 1014 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1015 int i; 1016 1017 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1018 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1019 int bit = misa_cfg->misa_bit; 1020 const char *name = riscv_get_misa_ext_name(bit); 1021 const char *desc = riscv_get_misa_ext_description(bit); 1022 1023 /* Check if KVM already created the property */ 1024 if (object_property_find(cpu_obj, name)) { 1025 continue; 1026 } 1027 1028 object_property_add(cpu_obj, name, "bool", 1029 cpu_get_misa_ext_cfg, 1030 cpu_set_misa_ext_cfg, 1031 NULL, (void *)misa_cfg); 1032 object_property_set_description(cpu_obj, name, desc); 1033 if (use_def_vals) { 1034 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1035 misa_cfg->enabled); 1036 } 1037 } 1038 } 1039 1040 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1041 void *opaque, Error **errp) 1042 { 1043 RISCVCPUProfile *profile = opaque; 1044 RISCVCPU *cpu = RISCV_CPU(obj); 1045 bool value; 1046 int i, ext_offset; 1047 1048 if (riscv_cpu_is_vendor(obj)) { 1049 error_setg(errp, "Profile %s is not available for vendor CPUs", 1050 profile->name); 1051 return; 1052 } 1053 1054 if (cpu->env.misa_mxl != MXL_RV64) { 1055 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1056 profile->name); 1057 return; 1058 } 1059 1060 if (!visit_type_bool(v, name, &value, errp)) { 1061 return; 1062 } 1063 1064 profile->user_set = true; 1065 profile->enabled = value; 1066 1067 if (profile->parent != NULL) { 1068 object_property_set_bool(obj, profile->parent->name, 1069 profile->enabled, NULL); 1070 } 1071 1072 if (profile->enabled) { 1073 cpu->env.priv_ver = profile->priv_spec; 1074 } 1075 1076 #ifndef CONFIG_USER_ONLY 1077 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1078 const char *satp_prop = satp_mode_str(profile->satp_mode, 1079 riscv_cpu_is_32bit(cpu)); 1080 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1081 } 1082 #endif 1083 1084 for (i = 0; misa_bits[i] != 0; i++) { 1085 uint32_t bit = misa_bits[i]; 1086 1087 if (!(profile->misa_ext & bit)) { 1088 continue; 1089 } 1090 1091 if (bit == RVI && !profile->enabled) { 1092 /* 1093 * Disabling profiles will not disable the base 1094 * ISA RV64I. 1095 */ 1096 continue; 1097 } 1098 1099 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1100 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1101 } 1102 1103 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1104 ext_offset = profile->ext_offsets[i]; 1105 1106 if (profile->enabled) { 1107 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1108 riscv_cpu_enable_named_feat(cpu, ext_offset); 1109 } 1110 1111 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1112 } 1113 1114 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1115 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1116 } 1117 } 1118 1119 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1120 void *opaque, Error **errp) 1121 { 1122 RISCVCPUProfile *profile = opaque; 1123 bool value = profile->enabled; 1124 1125 visit_type_bool(v, name, &value, errp); 1126 } 1127 1128 static void riscv_cpu_add_profiles(Object *cpu_obj) 1129 { 1130 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1131 const RISCVCPUProfile *profile = riscv_profiles[i]; 1132 1133 object_property_add(cpu_obj, profile->name, "bool", 1134 cpu_get_profile, cpu_set_profile, 1135 NULL, (void *)profile); 1136 1137 /* 1138 * CPUs might enable a profile right from the start. 1139 * Enable its mandatory extensions right away in this 1140 * case. 1141 */ 1142 if (profile->enabled) { 1143 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1144 } 1145 } 1146 } 1147 1148 static bool cpu_ext_is_deprecated(const char *ext_name) 1149 { 1150 return isupper(ext_name[0]); 1151 } 1152 1153 /* 1154 * String will be allocated in the heap. Caller is responsible 1155 * for freeing it. 1156 */ 1157 static char *cpu_ext_to_lower(const char *ext_name) 1158 { 1159 char *ret = g_malloc0(strlen(ext_name) + 1); 1160 1161 strcpy(ret, ext_name); 1162 ret[0] = tolower(ret[0]); 1163 1164 return ret; 1165 } 1166 1167 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1168 void *opaque, Error **errp) 1169 { 1170 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1171 RISCVCPU *cpu = RISCV_CPU(obj); 1172 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1173 bool prev_val, value; 1174 1175 if (!visit_type_bool(v, name, &value, errp)) { 1176 return; 1177 } 1178 1179 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1180 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1181 1182 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1183 multi_ext_cfg->name, lower); 1184 } 1185 1186 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1187 1188 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1189 1190 if (value == prev_val) { 1191 return; 1192 } 1193 1194 if (value && vendor_cpu) { 1195 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1196 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1197 cpuname); 1198 return; 1199 } 1200 1201 if (value) { 1202 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1203 } 1204 1205 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1206 } 1207 1208 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1209 void *opaque, Error **errp) 1210 { 1211 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1212 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1213 1214 visit_type_bool(v, name, &value, errp); 1215 } 1216 1217 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1218 const RISCVCPUMultiExtConfig *multi_cfg) 1219 { 1220 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1221 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1222 1223 object_property_add(cpu_obj, multi_cfg->name, "bool", 1224 cpu_get_multi_ext_cfg, 1225 cpu_set_multi_ext_cfg, 1226 NULL, (void *)multi_cfg); 1227 1228 if (!generic_cpu || deprecated_ext) { 1229 return; 1230 } 1231 1232 /* 1233 * Set def val directly instead of using 1234 * object_property_set_bool() to save the set() 1235 * callback hash for user inputs. 1236 */ 1237 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1238 multi_cfg->enabled); 1239 } 1240 1241 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1242 const RISCVCPUMultiExtConfig *array) 1243 { 1244 const RISCVCPUMultiExtConfig *prop; 1245 1246 g_assert(array); 1247 1248 for (prop = array; prop && prop->name; prop++) { 1249 cpu_add_multi_ext_prop(obj, prop); 1250 } 1251 } 1252 1253 /* 1254 * Add CPU properties with user-facing flags. 1255 * 1256 * This will overwrite existing env->misa_ext values with the 1257 * defaults set via riscv_cpu_add_misa_properties(). 1258 */ 1259 static void riscv_cpu_add_user_properties(Object *obj) 1260 { 1261 #ifndef CONFIG_USER_ONLY 1262 riscv_add_satp_mode_properties(obj); 1263 #endif 1264 1265 riscv_cpu_add_misa_properties(obj); 1266 1267 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1268 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1269 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1270 1271 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1272 1273 riscv_cpu_add_profiles(obj); 1274 } 1275 1276 /* 1277 * The 'max' type CPU will have all possible ratified 1278 * non-vendor extensions enabled. 1279 */ 1280 static void riscv_init_max_cpu_extensions(Object *obj) 1281 { 1282 RISCVCPU *cpu = RISCV_CPU(obj); 1283 CPURISCVState *env = &cpu->env; 1284 const RISCVCPUMultiExtConfig *prop; 1285 1286 /* Enable RVG, RVJ and RVV that are disabled by default */ 1287 riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV); 1288 1289 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1290 isa_ext_update_enabled(cpu, prop->offset, true); 1291 } 1292 1293 /* set vector version */ 1294 env->vext_ver = VEXT_VERSION_1_00_0; 1295 1296 /* Zfinx is not compatible with F. Disable it */ 1297 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1298 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1299 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1300 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1301 1302 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1303 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1304 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1305 1306 if (env->misa_mxl != MXL_RV32) { 1307 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1308 } 1309 } 1310 1311 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1312 { 1313 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1314 } 1315 1316 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1317 { 1318 RISCVCPU *cpu = RISCV_CPU(cs); 1319 Object *obj = OBJECT(cpu); 1320 1321 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1322 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1323 riscv_cpu_add_user_properties(obj); 1324 1325 if (riscv_cpu_has_max_extensions(obj)) { 1326 riscv_init_max_cpu_extensions(obj); 1327 } 1328 } 1329 1330 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1331 { 1332 /* 1333 * All cpus use the same set of operations. 1334 */ 1335 cc->tcg_ops = &riscv_tcg_ops; 1336 } 1337 1338 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1339 { 1340 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1341 } 1342 1343 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1344 { 1345 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1346 1347 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1348 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1349 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1350 } 1351 1352 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1353 .name = ACCEL_CPU_NAME("tcg"), 1354 1355 .parent = TYPE_ACCEL_CPU, 1356 .class_init = riscv_tcg_cpu_accel_class_init, 1357 .abstract = true, 1358 }; 1359 1360 static void riscv_tcg_cpu_accel_register_types(void) 1361 { 1362 type_register_static(&riscv_tcg_cpu_accel_type_info); 1363 } 1364 type_init(riscv_tcg_cpu_accel_register_types); 1365