1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "tcg-cpu.h" 23 #include "cpu.h" 24 #include "internals.h" 25 #include "pmu.h" 26 #include "time_helper.h" 27 #include "qapi/error.h" 28 #include "qapi/visitor.h" 29 #include "qemu/accel.h" 30 #include "qemu/error-report.h" 31 #include "qemu/log.h" 32 #include "hw/core/accel-cpu.h" 33 #include "hw/core/tcg-cpu-ops.h" 34 #include "tcg/tcg.h" 35 #ifndef CONFIG_USER_ONLY 36 #include "hw/boards.h" 37 #endif 38 39 /* Hash that stores user set extensions */ 40 static GHashTable *multi_ext_user_opts; 41 static GHashTable *misa_ext_user_opts; 42 43 static GHashTable *multi_ext_implied_rules; 44 static GHashTable *misa_ext_implied_rules; 45 46 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 47 { 48 return g_hash_table_contains(multi_ext_user_opts, 49 GUINT_TO_POINTER(ext_offset)); 50 } 51 52 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 53 { 54 return g_hash_table_contains(misa_ext_user_opts, 55 GUINT_TO_POINTER(misa_bit)); 56 } 57 58 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 59 { 60 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 61 (gpointer)value); 62 } 63 64 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 65 { 66 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 67 (gpointer)value); 68 } 69 70 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 71 bool enabled) 72 { 73 CPURISCVState *env = &cpu->env; 74 75 if (enabled) { 76 env->misa_ext |= bit; 77 env->misa_ext_mask |= bit; 78 } else { 79 env->misa_ext &= ~bit; 80 env->misa_ext_mask &= ~bit; 81 } 82 } 83 84 static const char *cpu_priv_ver_to_str(int priv_ver) 85 { 86 const char *priv_spec_str = priv_spec_to_str(priv_ver); 87 88 g_assert(priv_spec_str); 89 90 return priv_spec_str; 91 } 92 93 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 94 const TranslationBlock *tb) 95 { 96 if (!(tb_cflags(tb) & CF_PCREL)) { 97 RISCVCPU *cpu = RISCV_CPU(cs); 98 CPURISCVState *env = &cpu->env; 99 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 100 101 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 102 103 if (xl == MXL_RV32) { 104 env->pc = (int32_t) tb->pc; 105 } else { 106 env->pc = tb->pc; 107 } 108 } 109 } 110 111 static void riscv_restore_state_to_opc(CPUState *cs, 112 const TranslationBlock *tb, 113 const uint64_t *data) 114 { 115 RISCVCPU *cpu = RISCV_CPU(cs); 116 CPURISCVState *env = &cpu->env; 117 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 118 target_ulong pc; 119 120 if (tb_cflags(tb) & CF_PCREL) { 121 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 122 } else { 123 pc = data[0]; 124 } 125 126 if (xl == MXL_RV32) { 127 env->pc = (int32_t)pc; 128 } else { 129 env->pc = pc; 130 } 131 env->bins = data[1]; 132 } 133 134 static const TCGCPUOps riscv_tcg_ops = { 135 .initialize = riscv_translate_init, 136 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 137 .restore_state_to_opc = riscv_restore_state_to_opc, 138 139 #ifndef CONFIG_USER_ONLY 140 .tlb_fill = riscv_cpu_tlb_fill, 141 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 142 .cpu_exec_halt = riscv_cpu_has_work, 143 .do_interrupt = riscv_cpu_do_interrupt, 144 .do_transaction_failed = riscv_cpu_do_transaction_failed, 145 .do_unaligned_access = riscv_cpu_do_unaligned_access, 146 .debug_excp_handler = riscv_cpu_debug_excp_handler, 147 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 148 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 149 #endif /* !CONFIG_USER_ONLY */ 150 }; 151 152 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 153 { 154 const RISCVIsaExtData *edata; 155 156 for (edata = isa_edata_arr; edata && edata->name; edata++) { 157 if (edata->ext_enable_offset != ext_offset) { 158 continue; 159 } 160 161 return edata->min_version; 162 } 163 164 g_assert_not_reached(); 165 } 166 167 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 168 { 169 const RISCVCPUMultiExtConfig *feat; 170 const RISCVIsaExtData *edata; 171 172 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 173 if (edata->ext_enable_offset == ext_offset) { 174 return edata->name; 175 } 176 } 177 178 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 179 if (feat->offset == ext_offset) { 180 return feat->name; 181 } 182 } 183 184 g_assert_not_reached(); 185 } 186 187 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 188 { 189 const RISCVCPUMultiExtConfig *feat; 190 191 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 192 if (feat->offset == ext_offset) { 193 return true; 194 } 195 } 196 197 return false; 198 } 199 200 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 201 { 202 /* 203 * All other named features are already enabled 204 * in riscv_tcg_cpu_instance_init(). 205 */ 206 if (feat_offset == CPU_CFG_OFFSET(ext_zic64b)) { 207 cpu->cfg.cbom_blocksize = 64; 208 cpu->cfg.cbop_blocksize = 64; 209 cpu->cfg.cboz_blocksize = 64; 210 } 211 } 212 213 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 214 uint32_t ext_offset) 215 { 216 int ext_priv_ver; 217 218 if (env->priv_ver == PRIV_VERSION_LATEST) { 219 return; 220 } 221 222 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 223 224 if (env->priv_ver < ext_priv_ver) { 225 /* 226 * Note: the 'priv_spec' command line option, if present, 227 * will take precedence over this priv_ver bump. 228 */ 229 env->priv_ver = ext_priv_ver; 230 } 231 } 232 233 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 234 bool value) 235 { 236 CPURISCVState *env = &cpu->env; 237 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 238 int min_version; 239 240 if (prev_val == value) { 241 return; 242 } 243 244 if (cpu_cfg_ext_is_user_set(ext_offset)) { 245 return; 246 } 247 248 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 249 /* Do not enable it if priv_ver is older than min_version */ 250 min_version = cpu_cfg_ext_get_min_version(ext_offset); 251 if (env->priv_ver < min_version) { 252 return; 253 } 254 } 255 256 isa_ext_update_enabled(cpu, ext_offset, value); 257 } 258 259 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 260 { 261 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 262 error_setg(errp, "H extension requires priv spec 1.12.0"); 263 return; 264 } 265 } 266 267 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 268 Error **errp) 269 { 270 uint32_t vlen = cfg->vlenb << 3; 271 272 if (vlen > RV_VLEN_MAX || vlen < 128) { 273 error_setg(errp, 274 "Vector extension implementation only supports VLEN " 275 "in the range [128, %d]", RV_VLEN_MAX); 276 return; 277 } 278 279 if (cfg->elen > 64 || cfg->elen < 8) { 280 error_setg(errp, 281 "Vector extension implementation only supports ELEN " 282 "in the range [8, 64]"); 283 return; 284 } 285 } 286 287 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 288 { 289 CPURISCVState *env = &cpu->env; 290 const RISCVIsaExtData *edata; 291 292 /* Force disable extensions if priv spec version does not match */ 293 for (edata = isa_edata_arr; edata && edata->name; edata++) { 294 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 295 (env->priv_ver < edata->min_version)) { 296 /* 297 * These two extensions are always enabled as they were supported 298 * by QEMU before they were added as extensions in the ISA. 299 */ 300 if (!strcmp(edata->name, "zicntr") || 301 !strcmp(edata->name, "zihpm")) { 302 continue; 303 } 304 305 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 306 #ifndef CONFIG_USER_ONLY 307 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 308 " because privilege spec version does not match", 309 edata->name, env->mhartid); 310 #else 311 warn_report("disabling %s extension because " 312 "privilege spec version does not match", 313 edata->name); 314 #endif 315 } 316 } 317 } 318 319 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 320 { 321 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { 322 cpu->cfg.has_priv_1_11 = true; 323 } 324 325 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { 326 cpu->cfg.has_priv_1_12 = true; 327 } 328 329 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { 330 cpu->cfg.has_priv_1_13 = true; 331 } 332 333 /* zic64b is 1.12 or later */ 334 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && 335 cpu->cfg.cbop_blocksize == 64 && 336 cpu->cfg.cboz_blocksize == 64 && 337 cpu->cfg.has_priv_1_12; 338 } 339 340 static void riscv_cpu_validate_g(RISCVCPU *cpu) 341 { 342 const char *warn_msg = "RVG mandates disabled extension %s"; 343 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 344 bool send_warn = cpu_misa_ext_is_user_set(RVG); 345 346 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 347 uint32_t bit = g_misa_bits[i]; 348 349 if (riscv_has_ext(&cpu->env, bit)) { 350 continue; 351 } 352 353 if (!cpu_misa_ext_is_user_set(bit)) { 354 riscv_cpu_write_misa_bit(cpu, bit, true); 355 continue; 356 } 357 358 if (send_warn) { 359 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 360 } 361 } 362 363 if (!cpu->cfg.ext_zicsr) { 364 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 365 cpu->cfg.ext_zicsr = true; 366 } else if (send_warn) { 367 warn_report(warn_msg, "zicsr"); 368 } 369 } 370 371 if (!cpu->cfg.ext_zifencei) { 372 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 373 cpu->cfg.ext_zifencei = true; 374 } else if (send_warn) { 375 warn_report(warn_msg, "zifencei"); 376 } 377 } 378 } 379 380 static void riscv_cpu_validate_b(RISCVCPU *cpu) 381 { 382 const char *warn_msg = "RVB mandates disabled extension %s"; 383 384 if (!cpu->cfg.ext_zba) { 385 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 386 cpu->cfg.ext_zba = true; 387 } else { 388 warn_report(warn_msg, "zba"); 389 } 390 } 391 392 if (!cpu->cfg.ext_zbb) { 393 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 394 cpu->cfg.ext_zbb = true; 395 } else { 396 warn_report(warn_msg, "zbb"); 397 } 398 } 399 400 if (!cpu->cfg.ext_zbs) { 401 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 402 cpu->cfg.ext_zbs = true; 403 } else { 404 warn_report(warn_msg, "zbs"); 405 } 406 } 407 } 408 409 /* 410 * Check consistency between chosen extensions while setting 411 * cpu->cfg accordingly. 412 */ 413 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 414 { 415 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 416 CPURISCVState *env = &cpu->env; 417 Error *local_err = NULL; 418 419 if (riscv_has_ext(env, RVG)) { 420 riscv_cpu_validate_g(cpu); 421 } 422 423 if (riscv_has_ext(env, RVB)) { 424 riscv_cpu_validate_b(cpu); 425 } 426 427 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 428 error_setg(errp, 429 "I and E extensions are incompatible"); 430 return; 431 } 432 433 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 434 error_setg(errp, 435 "Either I or E extension must be set"); 436 return; 437 } 438 439 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 440 error_setg(errp, 441 "Setting S extension without U extension is illegal"); 442 return; 443 } 444 445 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 446 error_setg(errp, 447 "H depends on an I base integer ISA with 32 x registers"); 448 return; 449 } 450 451 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 452 error_setg(errp, "H extension implicitly requires S-mode"); 453 return; 454 } 455 456 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 457 error_setg(errp, "F extension requires Zicsr"); 458 return; 459 } 460 461 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 462 error_setg(errp, "Zacas extension requires A extension"); 463 return; 464 } 465 466 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 467 error_setg(errp, "Zawrs extension requires A extension"); 468 return; 469 } 470 471 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 472 error_setg(errp, "Zfa extension requires F extension"); 473 return; 474 } 475 476 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 477 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 478 return; 479 } 480 481 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 482 error_setg(errp, "Zfbfmin extension depends on F extension"); 483 return; 484 } 485 486 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 487 error_setg(errp, "D extension requires F extension"); 488 return; 489 } 490 491 if (riscv_has_ext(env, RVV)) { 492 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 493 if (local_err != NULL) { 494 error_propagate(errp, local_err); 495 return; 496 } 497 } 498 499 /* The Zve64d extension depends on the Zve64f extension */ 500 if (cpu->cfg.ext_zve64d) { 501 if (!riscv_has_ext(env, RVD)) { 502 error_setg(errp, "Zve64d/V extensions require D extension"); 503 return; 504 } 505 } 506 507 /* The Zve32f extension depends on the Zve32x extension */ 508 if (cpu->cfg.ext_zve32f) { 509 if (!riscv_has_ext(env, RVF)) { 510 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 511 return; 512 } 513 } 514 515 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 516 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 517 return; 518 } 519 520 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 521 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 522 return; 523 } 524 525 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 526 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 527 return; 528 } 529 530 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 531 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 532 return; 533 } 534 535 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 536 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 537 return; 538 } 539 540 if (cpu->cfg.ext_zfinx) { 541 if (!cpu->cfg.ext_zicsr) { 542 error_setg(errp, "Zfinx extension requires Zicsr"); 543 return; 544 } 545 if (riscv_has_ext(env, RVF)) { 546 error_setg(errp, 547 "Zfinx cannot be supported together with F extension"); 548 return; 549 } 550 } 551 552 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 553 error_setg(errp, "Zcf extension is only relevant to RV32"); 554 return; 555 } 556 557 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 558 error_setg(errp, "Zcf extension requires F extension"); 559 return; 560 } 561 562 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 563 error_setg(errp, "Zcd extension requires D extension"); 564 return; 565 } 566 567 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 568 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 569 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 570 "extension"); 571 return; 572 } 573 574 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 575 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 576 "Zcd extension"); 577 return; 578 } 579 580 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 581 error_setg(errp, "Zcmt extension requires Zicsr extension"); 582 return; 583 } 584 585 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 586 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 587 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { 588 error_setg(errp, 589 "Vector crypto extensions require V or Zve* extensions"); 590 return; 591 } 592 593 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { 594 error_setg( 595 errp, 596 "Zvbc and Zvknhb extensions require V or Zve64x extensions"); 597 return; 598 } 599 600 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 601 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 602 error_setg(errp, "zicntr requires zicsr"); 603 return; 604 } 605 cpu->cfg.ext_zicntr = false; 606 } 607 608 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 609 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 610 error_setg(errp, "zihpm requires zicsr"); 611 return; 612 } 613 cpu->cfg.ext_zihpm = false; 614 } 615 616 if (!cpu->cfg.ext_zihpm) { 617 cpu->cfg.pmu_mask = 0; 618 cpu->pmu_avail_ctrs = 0; 619 } 620 621 /* 622 * Disable isa extensions based on priv spec after we 623 * validated and set everything we need. 624 */ 625 riscv_cpu_disable_priv_spec_isa_exts(cpu); 626 } 627 628 #ifndef CONFIG_USER_ONLY 629 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 630 RISCVCPUProfile *profile, 631 bool send_warn) 632 { 633 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 634 635 if (profile->satp_mode > satp_max) { 636 if (send_warn) { 637 bool is_32bit = riscv_cpu_is_32bit(cpu); 638 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 639 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 640 641 warn_report("Profile %s requires satp mode %s, " 642 "but satp mode %s was set", profile->name, 643 req_satp, cur_satp); 644 } 645 646 return false; 647 } 648 649 return true; 650 } 651 #endif 652 653 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 654 RISCVCPUProfile *profile) 655 { 656 CPURISCVState *env = &cpu->env; 657 const char *warn_msg = "Profile %s mandates disabled extension %s"; 658 bool send_warn = profile->user_set && profile->enabled; 659 bool parent_enabled, profile_impl = true; 660 int i; 661 662 #ifndef CONFIG_USER_ONLY 663 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 664 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 665 send_warn); 666 } 667 #endif 668 669 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 670 profile->priv_spec != env->priv_ver) { 671 profile_impl = false; 672 673 if (send_warn) { 674 warn_report("Profile %s requires priv spec %s, " 675 "but priv ver %s was set", profile->name, 676 cpu_priv_ver_to_str(profile->priv_spec), 677 cpu_priv_ver_to_str(env->priv_ver)); 678 } 679 } 680 681 for (i = 0; misa_bits[i] != 0; i++) { 682 uint32_t bit = misa_bits[i]; 683 684 if (!(profile->misa_ext & bit)) { 685 continue; 686 } 687 688 if (!riscv_has_ext(&cpu->env, bit)) { 689 profile_impl = false; 690 691 if (send_warn) { 692 warn_report(warn_msg, profile->name, 693 riscv_get_misa_ext_name(bit)); 694 } 695 } 696 } 697 698 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 699 int ext_offset = profile->ext_offsets[i]; 700 701 if (!isa_ext_is_enabled(cpu, ext_offset)) { 702 profile_impl = false; 703 704 if (send_warn) { 705 warn_report(warn_msg, profile->name, 706 cpu_cfg_ext_get_name(ext_offset)); 707 } 708 } 709 } 710 711 profile->enabled = profile_impl; 712 713 if (profile->parent != NULL) { 714 parent_enabled = object_property_get_bool(OBJECT(cpu), 715 profile->parent->name, 716 NULL); 717 profile->enabled = profile->enabled && parent_enabled; 718 } 719 } 720 721 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 722 { 723 for (int i = 0; riscv_profiles[i] != NULL; i++) { 724 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 725 } 726 } 727 728 static void riscv_cpu_init_implied_exts_rules(void) 729 { 730 RISCVCPUImpliedExtsRule *rule; 731 #ifndef CONFIG_USER_ONLY 732 MachineState *ms = MACHINE(qdev_get_machine()); 733 #endif 734 static bool initialized; 735 int i; 736 737 /* Implied rules only need to be initialized once. */ 738 if (initialized) { 739 return; 740 } 741 742 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 743 #ifndef CONFIG_USER_ONLY 744 rule->enabled = bitmap_new(ms->smp.cpus); 745 #endif 746 g_hash_table_insert(misa_ext_implied_rules, 747 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 748 } 749 750 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 751 #ifndef CONFIG_USER_ONLY 752 rule->enabled = bitmap_new(ms->smp.cpus); 753 #endif 754 g_hash_table_insert(multi_ext_implied_rules, 755 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 756 } 757 758 initialized = true; 759 } 760 761 static void cpu_enable_implied_rule(RISCVCPU *cpu, 762 RISCVCPUImpliedExtsRule *rule) 763 { 764 CPURISCVState *env = &cpu->env; 765 RISCVCPUImpliedExtsRule *ir; 766 bool enabled = false; 767 int i; 768 769 #ifndef CONFIG_USER_ONLY 770 enabled = test_bit(cpu->env.mhartid, rule->enabled); 771 #endif 772 773 if (!enabled) { 774 /* Enable the implied MISAs. */ 775 if (rule->implied_misa_exts) { 776 riscv_cpu_set_misa_ext(env, 777 env->misa_ext | rule->implied_misa_exts); 778 779 for (i = 0; misa_bits[i] != 0; i++) { 780 if (rule->implied_misa_exts & misa_bits[i]) { 781 ir = g_hash_table_lookup(misa_ext_implied_rules, 782 GUINT_TO_POINTER(misa_bits[i])); 783 784 if (ir) { 785 cpu_enable_implied_rule(cpu, ir); 786 } 787 } 788 } 789 } 790 791 /* Enable the implied extensions. */ 792 for (i = 0; 793 rule->implied_multi_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) { 794 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); 795 796 ir = g_hash_table_lookup(multi_ext_implied_rules, 797 GUINT_TO_POINTER( 798 rule->implied_multi_exts[i])); 799 800 if (ir) { 801 cpu_enable_implied_rule(cpu, ir); 802 } 803 } 804 805 #ifndef CONFIG_USER_ONLY 806 bitmap_set(rule->enabled, cpu->env.mhartid, 1); 807 #endif 808 } 809 } 810 811 /* Zc extension has special implied rules that need to be handled separately. */ 812 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) 813 { 814 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 815 CPURISCVState *env = &cpu->env; 816 817 if (cpu->cfg.ext_zce) { 818 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 819 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 820 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 821 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 822 823 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 824 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 825 } 826 } 827 828 /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ 829 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 830 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 831 832 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 833 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 834 } 835 836 if (riscv_has_ext(env, RVD)) { 837 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 838 } 839 } 840 } 841 842 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) 843 { 844 RISCVCPUImpliedExtsRule *rule; 845 int i; 846 847 /* Enable the implied extensions for Zc. */ 848 cpu_enable_zc_implied_rules(cpu); 849 850 /* Enable the implied MISAs. */ 851 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 852 if (riscv_has_ext(&cpu->env, rule->ext)) { 853 cpu_enable_implied_rule(cpu, rule); 854 } 855 } 856 857 /* Enable the implied extensions. */ 858 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 859 if (isa_ext_is_enabled(cpu, rule->ext)) { 860 cpu_enable_implied_rule(cpu, rule); 861 } 862 } 863 } 864 865 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 866 { 867 CPURISCVState *env = &cpu->env; 868 Error *local_err = NULL; 869 870 riscv_cpu_init_implied_exts_rules(); 871 riscv_cpu_enable_implied_rules(cpu); 872 873 riscv_cpu_validate_misa_priv(env, &local_err); 874 if (local_err != NULL) { 875 error_propagate(errp, local_err); 876 return; 877 } 878 879 riscv_cpu_update_named_features(cpu); 880 riscv_cpu_validate_profiles(cpu); 881 882 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 883 /* 884 * Enhanced PMP should only be available 885 * on harts with PMP support 886 */ 887 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 888 return; 889 } 890 891 riscv_cpu_validate_set_extensions(cpu, &local_err); 892 if (local_err != NULL) { 893 error_propagate(errp, local_err); 894 return; 895 } 896 } 897 898 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) 899 { 900 GPtrArray *dynamic_decoders; 901 dynamic_decoders = g_ptr_array_sized_new(decoder_table_size); 902 for (size_t i = 0; i < decoder_table_size; ++i) { 903 if (decoder_table[i].guard_func && 904 decoder_table[i].guard_func(&cpu->cfg)) { 905 g_ptr_array_add(dynamic_decoders, 906 (gpointer)decoder_table[i].riscv_cpu_decode_fn); 907 } 908 } 909 910 cpu->decoders = dynamic_decoders; 911 } 912 913 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 914 { 915 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 916 } 917 918 static bool riscv_cpu_is_generic(Object *cpu_obj) 919 { 920 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 921 } 922 923 /* 924 * We'll get here via the following path: 925 * 926 * riscv_cpu_realize() 927 * -> cpu_exec_realizefn() 928 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 929 */ 930 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 931 { 932 RISCVCPU *cpu = RISCV_CPU(cs); 933 934 if (!riscv_cpu_tcg_compatible(cpu)) { 935 g_autofree char *name = riscv_cpu_get_name(cpu); 936 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 937 name); 938 return false; 939 } 940 941 #ifndef CONFIG_USER_ONLY 942 CPURISCVState *env = &cpu->env; 943 Error *local_err = NULL; 944 945 tcg_cflags_set(CPU(cs), CF_PCREL); 946 947 if (cpu->cfg.ext_sstc) { 948 riscv_timer_init(cpu); 949 } 950 951 if (cpu->cfg.pmu_mask) { 952 riscv_pmu_init(cpu, &local_err); 953 if (local_err != NULL) { 954 error_propagate(errp, local_err); 955 return false; 956 } 957 958 if (cpu->cfg.ext_sscofpmf) { 959 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 960 riscv_pmu_timer_cb, cpu); 961 } 962 } 963 964 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 965 if (riscv_has_ext(env, RVH)) { 966 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 967 } 968 #endif 969 970 return true; 971 } 972 973 typedef struct RISCVCPUMisaExtConfig { 974 target_ulong misa_bit; 975 bool enabled; 976 } RISCVCPUMisaExtConfig; 977 978 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 979 void *opaque, Error **errp) 980 { 981 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 982 target_ulong misa_bit = misa_ext_cfg->misa_bit; 983 RISCVCPU *cpu = RISCV_CPU(obj); 984 CPURISCVState *env = &cpu->env; 985 bool vendor_cpu = riscv_cpu_is_vendor(obj); 986 bool prev_val, value; 987 988 if (!visit_type_bool(v, name, &value, errp)) { 989 return; 990 } 991 992 cpu_misa_ext_add_user_opt(misa_bit, value); 993 994 prev_val = env->misa_ext & misa_bit; 995 996 if (value == prev_val) { 997 return; 998 } 999 1000 if (value) { 1001 if (vendor_cpu) { 1002 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1003 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1004 cpuname); 1005 return; 1006 } 1007 1008 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 1009 /* 1010 * Note: the 'priv_spec' command line option, if present, 1011 * will take precedence over this priv_ver bump. 1012 */ 1013 env->priv_ver = PRIV_VERSION_1_12_0; 1014 } 1015 } 1016 1017 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1018 } 1019 1020 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1021 void *opaque, Error **errp) 1022 { 1023 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1024 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1025 RISCVCPU *cpu = RISCV_CPU(obj); 1026 CPURISCVState *env = &cpu->env; 1027 bool value; 1028 1029 value = env->misa_ext & misa_bit; 1030 1031 visit_type_bool(v, name, &value, errp); 1032 } 1033 1034 #define MISA_CFG(_bit, _enabled) \ 1035 {.misa_bit = _bit, .enabled = _enabled} 1036 1037 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1038 MISA_CFG(RVA, true), 1039 MISA_CFG(RVC, true), 1040 MISA_CFG(RVD, true), 1041 MISA_CFG(RVF, true), 1042 MISA_CFG(RVI, true), 1043 MISA_CFG(RVE, false), 1044 MISA_CFG(RVM, true), 1045 MISA_CFG(RVS, true), 1046 MISA_CFG(RVU, true), 1047 MISA_CFG(RVH, true), 1048 MISA_CFG(RVJ, false), 1049 MISA_CFG(RVV, false), 1050 MISA_CFG(RVG, false), 1051 MISA_CFG(RVB, false), 1052 }; 1053 1054 /* 1055 * We do not support user choice tracking for MISA 1056 * extensions yet because, so far, we do not silently 1057 * change MISA bits during realize() (RVG enables MISA 1058 * bits but the user is warned about it). 1059 */ 1060 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1061 { 1062 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1063 int i; 1064 1065 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1066 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1067 int bit = misa_cfg->misa_bit; 1068 const char *name = riscv_get_misa_ext_name(bit); 1069 const char *desc = riscv_get_misa_ext_description(bit); 1070 1071 /* Check if KVM already created the property */ 1072 if (object_property_find(cpu_obj, name)) { 1073 continue; 1074 } 1075 1076 object_property_add(cpu_obj, name, "bool", 1077 cpu_get_misa_ext_cfg, 1078 cpu_set_misa_ext_cfg, 1079 NULL, (void *)misa_cfg); 1080 object_property_set_description(cpu_obj, name, desc); 1081 if (use_def_vals) { 1082 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1083 misa_cfg->enabled); 1084 } 1085 } 1086 } 1087 1088 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1089 void *opaque, Error **errp) 1090 { 1091 RISCVCPUProfile *profile = opaque; 1092 RISCVCPU *cpu = RISCV_CPU(obj); 1093 bool value; 1094 int i, ext_offset; 1095 1096 if (riscv_cpu_is_vendor(obj)) { 1097 error_setg(errp, "Profile %s is not available for vendor CPUs", 1098 profile->name); 1099 return; 1100 } 1101 1102 if (cpu->env.misa_mxl != MXL_RV64) { 1103 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1104 profile->name); 1105 return; 1106 } 1107 1108 if (!visit_type_bool(v, name, &value, errp)) { 1109 return; 1110 } 1111 1112 profile->user_set = true; 1113 profile->enabled = value; 1114 1115 if (profile->parent != NULL) { 1116 object_property_set_bool(obj, profile->parent->name, 1117 profile->enabled, NULL); 1118 } 1119 1120 if (profile->enabled) { 1121 cpu->env.priv_ver = profile->priv_spec; 1122 } 1123 1124 #ifndef CONFIG_USER_ONLY 1125 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1126 object_property_set_bool(obj, "mmu", true, NULL); 1127 const char *satp_prop = satp_mode_str(profile->satp_mode, 1128 riscv_cpu_is_32bit(cpu)); 1129 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1130 } 1131 #endif 1132 1133 for (i = 0; misa_bits[i] != 0; i++) { 1134 uint32_t bit = misa_bits[i]; 1135 1136 if (!(profile->misa_ext & bit)) { 1137 continue; 1138 } 1139 1140 if (bit == RVI && !profile->enabled) { 1141 /* 1142 * Disabling profiles will not disable the base 1143 * ISA RV64I. 1144 */ 1145 continue; 1146 } 1147 1148 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1149 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1150 } 1151 1152 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1153 ext_offset = profile->ext_offsets[i]; 1154 1155 if (profile->enabled) { 1156 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1157 riscv_cpu_enable_named_feat(cpu, ext_offset); 1158 } 1159 1160 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1161 } 1162 1163 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1164 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1165 } 1166 } 1167 1168 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1169 void *opaque, Error **errp) 1170 { 1171 RISCVCPUProfile *profile = opaque; 1172 bool value = profile->enabled; 1173 1174 visit_type_bool(v, name, &value, errp); 1175 } 1176 1177 static void riscv_cpu_add_profiles(Object *cpu_obj) 1178 { 1179 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1180 const RISCVCPUProfile *profile = riscv_profiles[i]; 1181 1182 object_property_add(cpu_obj, profile->name, "bool", 1183 cpu_get_profile, cpu_set_profile, 1184 NULL, (void *)profile); 1185 1186 /* 1187 * CPUs might enable a profile right from the start. 1188 * Enable its mandatory extensions right away in this 1189 * case. 1190 */ 1191 if (profile->enabled) { 1192 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1193 } 1194 } 1195 } 1196 1197 static bool cpu_ext_is_deprecated(const char *ext_name) 1198 { 1199 return isupper(ext_name[0]); 1200 } 1201 1202 /* 1203 * String will be allocated in the heap. Caller is responsible 1204 * for freeing it. 1205 */ 1206 static char *cpu_ext_to_lower(const char *ext_name) 1207 { 1208 char *ret = g_malloc0(strlen(ext_name) + 1); 1209 1210 strcpy(ret, ext_name); 1211 ret[0] = tolower(ret[0]); 1212 1213 return ret; 1214 } 1215 1216 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1217 void *opaque, Error **errp) 1218 { 1219 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1220 RISCVCPU *cpu = RISCV_CPU(obj); 1221 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1222 bool prev_val, value; 1223 1224 if (!visit_type_bool(v, name, &value, errp)) { 1225 return; 1226 } 1227 1228 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1229 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1230 1231 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1232 multi_ext_cfg->name, lower); 1233 } 1234 1235 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1236 1237 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1238 1239 if (value == prev_val) { 1240 return; 1241 } 1242 1243 if (value && vendor_cpu) { 1244 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1245 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1246 cpuname); 1247 return; 1248 } 1249 1250 if (value) { 1251 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1252 } 1253 1254 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1255 } 1256 1257 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1258 void *opaque, Error **errp) 1259 { 1260 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1261 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1262 1263 visit_type_bool(v, name, &value, errp); 1264 } 1265 1266 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1267 const RISCVCPUMultiExtConfig *multi_cfg) 1268 { 1269 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1270 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1271 1272 object_property_add(cpu_obj, multi_cfg->name, "bool", 1273 cpu_get_multi_ext_cfg, 1274 cpu_set_multi_ext_cfg, 1275 NULL, (void *)multi_cfg); 1276 1277 if (!generic_cpu || deprecated_ext) { 1278 return; 1279 } 1280 1281 /* 1282 * Set def val directly instead of using 1283 * object_property_set_bool() to save the set() 1284 * callback hash for user inputs. 1285 */ 1286 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1287 multi_cfg->enabled); 1288 } 1289 1290 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1291 const RISCVCPUMultiExtConfig *array) 1292 { 1293 const RISCVCPUMultiExtConfig *prop; 1294 1295 g_assert(array); 1296 1297 for (prop = array; prop && prop->name; prop++) { 1298 cpu_add_multi_ext_prop(obj, prop); 1299 } 1300 } 1301 1302 /* 1303 * Add CPU properties with user-facing flags. 1304 * 1305 * This will overwrite existing env->misa_ext values with the 1306 * defaults set via riscv_cpu_add_misa_properties(). 1307 */ 1308 static void riscv_cpu_add_user_properties(Object *obj) 1309 { 1310 #ifndef CONFIG_USER_ONLY 1311 riscv_add_satp_mode_properties(obj); 1312 #endif 1313 1314 riscv_cpu_add_misa_properties(obj); 1315 1316 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1317 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1318 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1319 1320 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1321 1322 riscv_cpu_add_profiles(obj); 1323 } 1324 1325 /* 1326 * The 'max' type CPU will have all possible ratified 1327 * non-vendor extensions enabled. 1328 */ 1329 static void riscv_init_max_cpu_extensions(Object *obj) 1330 { 1331 RISCVCPU *cpu = RISCV_CPU(obj); 1332 CPURISCVState *env = &cpu->env; 1333 const RISCVCPUMultiExtConfig *prop; 1334 1335 /* Enable RVG, RVJ and RVV that are disabled by default */ 1336 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV); 1337 1338 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1339 isa_ext_update_enabled(cpu, prop->offset, true); 1340 } 1341 1342 /* 1343 * Some extensions can't be added without backward compatibilty concerns. 1344 * Disable those, the user can still opt in to them on the command line. 1345 */ 1346 cpu->cfg.ext_svade = false; 1347 1348 /* set vector version */ 1349 env->vext_ver = VEXT_VERSION_1_00_0; 1350 1351 /* Zfinx is not compatible with F. Disable it */ 1352 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1353 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1354 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1355 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1356 1357 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1358 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1359 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1360 1361 if (env->misa_mxl != MXL_RV32) { 1362 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1363 } 1364 } 1365 1366 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1367 { 1368 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1369 } 1370 1371 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1372 { 1373 RISCVCPU *cpu = RISCV_CPU(cs); 1374 Object *obj = OBJECT(cpu); 1375 1376 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1377 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1378 1379 if (!misa_ext_implied_rules) { 1380 misa_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1381 } 1382 1383 if (!multi_ext_implied_rules) { 1384 multi_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1385 } 1386 1387 riscv_cpu_add_user_properties(obj); 1388 1389 if (riscv_cpu_has_max_extensions(obj)) { 1390 riscv_init_max_cpu_extensions(obj); 1391 } 1392 } 1393 1394 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1395 { 1396 /* 1397 * All cpus use the same set of operations. 1398 */ 1399 cc->tcg_ops = &riscv_tcg_ops; 1400 } 1401 1402 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1403 { 1404 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1405 } 1406 1407 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1408 { 1409 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1410 1411 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1412 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1413 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1414 } 1415 1416 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1417 .name = ACCEL_CPU_NAME("tcg"), 1418 1419 .parent = TYPE_ACCEL_CPU, 1420 .class_init = riscv_tcg_cpu_accel_class_init, 1421 .abstract = true, 1422 }; 1423 1424 static void riscv_tcg_cpu_accel_register_types(void) 1425 { 1426 type_register_static(&riscv_tcg_cpu_accel_type_info); 1427 } 1428 type_init(riscv_tcg_cpu_accel_register_types); 1429