1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "tcg-cpu.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "time_helper.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "qemu/accel.h" 29 #include "qemu/error-report.h" 30 #include "qemu/log.h" 31 #include "hw/core/accel-cpu.h" 32 #include "hw/core/tcg-cpu-ops.h" 33 #include "tcg/tcg.h" 34 35 /* Hash that stores user set extensions */ 36 static GHashTable *multi_ext_user_opts; 37 static GHashTable *misa_ext_user_opts; 38 39 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 40 { 41 return g_hash_table_contains(multi_ext_user_opts, 42 GUINT_TO_POINTER(ext_offset)); 43 } 44 45 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 46 { 47 return g_hash_table_contains(misa_ext_user_opts, 48 GUINT_TO_POINTER(misa_bit)); 49 } 50 51 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 52 { 53 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 54 (gpointer)value); 55 } 56 57 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 58 { 59 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 60 (gpointer)value); 61 } 62 63 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 64 bool enabled) 65 { 66 CPURISCVState *env = &cpu->env; 67 68 if (enabled) { 69 env->misa_ext |= bit; 70 env->misa_ext_mask |= bit; 71 } else { 72 env->misa_ext &= ~bit; 73 env->misa_ext_mask &= ~bit; 74 } 75 } 76 77 static const char *cpu_priv_ver_to_str(int priv_ver) 78 { 79 switch (priv_ver) { 80 case PRIV_VERSION_1_10_0: 81 return "v1.10.0"; 82 case PRIV_VERSION_1_11_0: 83 return "v1.11.0"; 84 case PRIV_VERSION_1_12_0: 85 return "v1.12.0"; 86 } 87 88 g_assert_not_reached(); 89 } 90 91 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 92 const TranslationBlock *tb) 93 { 94 if (!(tb_cflags(tb) & CF_PCREL)) { 95 RISCVCPU *cpu = RISCV_CPU(cs); 96 CPURISCVState *env = &cpu->env; 97 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 98 99 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 100 101 if (xl == MXL_RV32) { 102 env->pc = (int32_t) tb->pc; 103 } else { 104 env->pc = tb->pc; 105 } 106 } 107 } 108 109 static void riscv_restore_state_to_opc(CPUState *cs, 110 const TranslationBlock *tb, 111 const uint64_t *data) 112 { 113 RISCVCPU *cpu = RISCV_CPU(cs); 114 CPURISCVState *env = &cpu->env; 115 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 116 target_ulong pc; 117 118 if (tb_cflags(tb) & CF_PCREL) { 119 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 120 } else { 121 pc = data[0]; 122 } 123 124 if (xl == MXL_RV32) { 125 env->pc = (int32_t)pc; 126 } else { 127 env->pc = pc; 128 } 129 env->bins = data[1]; 130 } 131 132 static const TCGCPUOps riscv_tcg_ops = { 133 .initialize = riscv_translate_init, 134 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 135 .restore_state_to_opc = riscv_restore_state_to_opc, 136 137 #ifndef CONFIG_USER_ONLY 138 .tlb_fill = riscv_cpu_tlb_fill, 139 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 140 .do_interrupt = riscv_cpu_do_interrupt, 141 .do_transaction_failed = riscv_cpu_do_transaction_failed, 142 .do_unaligned_access = riscv_cpu_do_unaligned_access, 143 .debug_excp_handler = riscv_cpu_debug_excp_handler, 144 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 145 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 146 #endif /* !CONFIG_USER_ONLY */ 147 }; 148 149 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 150 { 151 const RISCVIsaExtData *edata; 152 153 for (edata = isa_edata_arr; edata && edata->name; edata++) { 154 if (edata->ext_enable_offset != ext_offset) { 155 continue; 156 } 157 158 return edata->min_version; 159 } 160 161 g_assert_not_reached(); 162 } 163 164 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 165 { 166 const RISCVCPUMultiExtConfig *feat; 167 const RISCVIsaExtData *edata; 168 169 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 170 if (edata->ext_enable_offset == ext_offset) { 171 return edata->name; 172 } 173 } 174 175 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 176 if (feat->offset == ext_offset) { 177 return feat->name; 178 } 179 } 180 181 g_assert_not_reached(); 182 } 183 184 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 185 { 186 const RISCVCPUMultiExtConfig *feat; 187 188 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 189 if (feat->offset == ext_offset) { 190 return true; 191 } 192 } 193 194 return false; 195 } 196 197 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 198 { 199 switch (feat_offset) { 200 case CPU_CFG_OFFSET(zic64b): 201 cpu->cfg.cbom_blocksize = 64; 202 cpu->cfg.cbop_blocksize = 64; 203 cpu->cfg.cboz_blocksize = 64; 204 break; 205 case CPU_CFG_OFFSET(svade): 206 cpu->cfg.ext_svadu = false; 207 break; 208 default: 209 g_assert_not_reached(); 210 } 211 } 212 213 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 214 uint32_t ext_offset) 215 { 216 int ext_priv_ver; 217 218 if (env->priv_ver == PRIV_VERSION_LATEST) { 219 return; 220 } 221 222 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 223 return; 224 } 225 226 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 227 228 if (env->priv_ver < ext_priv_ver) { 229 /* 230 * Note: the 'priv_spec' command line option, if present, 231 * will take precedence over this priv_ver bump. 232 */ 233 env->priv_ver = ext_priv_ver; 234 } 235 } 236 237 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 238 bool value) 239 { 240 CPURISCVState *env = &cpu->env; 241 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 242 int min_version; 243 244 if (prev_val == value) { 245 return; 246 } 247 248 if (cpu_cfg_ext_is_user_set(ext_offset)) { 249 return; 250 } 251 252 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 253 /* Do not enable it if priv_ver is older than min_version */ 254 min_version = cpu_cfg_ext_get_min_version(ext_offset); 255 if (env->priv_ver < min_version) { 256 return; 257 } 258 } 259 260 isa_ext_update_enabled(cpu, ext_offset, value); 261 } 262 263 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 264 { 265 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 266 error_setg(errp, "H extension requires priv spec 1.12.0"); 267 return; 268 } 269 } 270 271 static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) 272 { 273 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 274 CPUClass *cc = CPU_CLASS(mcc); 275 CPURISCVState *env = &cpu->env; 276 277 /* Validate that MISA_MXL is set properly. */ 278 switch (env->misa_mxl_max) { 279 #ifdef TARGET_RISCV64 280 case MXL_RV64: 281 case MXL_RV128: 282 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 283 break; 284 #endif 285 case MXL_RV32: 286 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 287 break; 288 default: 289 g_assert_not_reached(); 290 } 291 292 if (env->misa_mxl_max != env->misa_mxl) { 293 error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); 294 return; 295 } 296 } 297 298 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) 299 { 300 CPURISCVState *env = &cpu->env; 301 int priv_version = -1; 302 303 if (cpu->cfg.priv_spec) { 304 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 305 priv_version = PRIV_VERSION_1_12_0; 306 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 307 priv_version = PRIV_VERSION_1_11_0; 308 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 309 priv_version = PRIV_VERSION_1_10_0; 310 } else { 311 error_setg(errp, 312 "Unsupported privilege spec version '%s'", 313 cpu->cfg.priv_spec); 314 return; 315 } 316 317 env->priv_ver = priv_version; 318 } 319 } 320 321 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 322 Error **errp) 323 { 324 if (!is_power_of_2(cfg->vlen)) { 325 error_setg(errp, "Vector extension VLEN must be power of 2"); 326 return; 327 } 328 329 if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { 330 error_setg(errp, 331 "Vector extension implementation only supports VLEN " 332 "in the range [128, %d]", RV_VLEN_MAX); 333 return; 334 } 335 336 if (!is_power_of_2(cfg->elen)) { 337 error_setg(errp, "Vector extension ELEN must be power of 2"); 338 return; 339 } 340 341 if (cfg->elen > 64 || cfg->elen < 8) { 342 error_setg(errp, 343 "Vector extension implementation only supports ELEN " 344 "in the range [8, 64]"); 345 return; 346 } 347 348 if (cfg->vext_spec) { 349 if (!g_strcmp0(cfg->vext_spec, "v1.0")) { 350 env->vext_ver = VEXT_VERSION_1_00_0; 351 } else { 352 error_setg(errp, "Unsupported vector spec version '%s'", 353 cfg->vext_spec); 354 return; 355 } 356 } else if (env->vext_ver == 0) { 357 qemu_log("vector version is not specified, " 358 "use the default value v1.0\n"); 359 360 env->vext_ver = VEXT_VERSION_1_00_0; 361 } 362 } 363 364 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 365 { 366 CPURISCVState *env = &cpu->env; 367 const RISCVIsaExtData *edata; 368 369 /* Force disable extensions if priv spec version does not match */ 370 for (edata = isa_edata_arr; edata && edata->name; edata++) { 371 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 372 (env->priv_ver < edata->min_version)) { 373 /* 374 * These two extensions are always enabled as they were supported 375 * by QEMU before they were added as extensions in the ISA. 376 */ 377 if (!strcmp(edata->name, "zicntr") || 378 !strcmp(edata->name, "zihpm")) { 379 continue; 380 } 381 382 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 383 #ifndef CONFIG_USER_ONLY 384 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 385 " because privilege spec version does not match", 386 edata->name, env->mhartid); 387 #else 388 warn_report("disabling %s extension because " 389 "privilege spec version does not match", 390 edata->name); 391 #endif 392 } 393 } 394 } 395 396 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 397 { 398 cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 && 399 cpu->cfg.cbop_blocksize == 64 && 400 cpu->cfg.cboz_blocksize == 64; 401 402 cpu->cfg.svade = !cpu->cfg.ext_svadu; 403 } 404 405 static void riscv_cpu_validate_g(RISCVCPU *cpu) 406 { 407 const char *warn_msg = "RVG mandates disabled extension %s"; 408 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 409 bool send_warn = cpu_misa_ext_is_user_set(RVG); 410 411 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 412 uint32_t bit = g_misa_bits[i]; 413 414 if (riscv_has_ext(&cpu->env, bit)) { 415 continue; 416 } 417 418 if (!cpu_misa_ext_is_user_set(bit)) { 419 riscv_cpu_write_misa_bit(cpu, bit, true); 420 continue; 421 } 422 423 if (send_warn) { 424 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 425 } 426 } 427 428 if (!cpu->cfg.ext_zicsr) { 429 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 430 cpu->cfg.ext_zicsr = true; 431 } else if (send_warn) { 432 warn_report(warn_msg, "zicsr"); 433 } 434 } 435 436 if (!cpu->cfg.ext_zifencei) { 437 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 438 cpu->cfg.ext_zifencei = true; 439 } else if (send_warn) { 440 warn_report(warn_msg, "zifencei"); 441 } 442 } 443 } 444 445 static void riscv_cpu_validate_b(RISCVCPU *cpu) 446 { 447 const char *warn_msg = "RVB mandates disabled extension %s"; 448 449 if (!cpu->cfg.ext_zba) { 450 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 451 cpu->cfg.ext_zba = true; 452 } else { 453 warn_report(warn_msg, "zba"); 454 } 455 } 456 457 if (!cpu->cfg.ext_zbb) { 458 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 459 cpu->cfg.ext_zbb = true; 460 } else { 461 warn_report(warn_msg, "zbb"); 462 } 463 } 464 465 if (!cpu->cfg.ext_zbs) { 466 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 467 cpu->cfg.ext_zbs = true; 468 } else { 469 warn_report(warn_msg, "zbs"); 470 } 471 } 472 } 473 474 /* 475 * Check consistency between chosen extensions while setting 476 * cpu->cfg accordingly. 477 */ 478 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 479 { 480 CPURISCVState *env = &cpu->env; 481 Error *local_err = NULL; 482 483 if (riscv_has_ext(env, RVG)) { 484 riscv_cpu_validate_g(cpu); 485 } 486 487 if (riscv_has_ext(env, RVB)) { 488 riscv_cpu_validate_b(cpu); 489 } 490 491 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 492 error_setg(errp, 493 "I and E extensions are incompatible"); 494 return; 495 } 496 497 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 498 error_setg(errp, 499 "Either I or E extension must be set"); 500 return; 501 } 502 503 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 504 error_setg(errp, 505 "Setting S extension without U extension is illegal"); 506 return; 507 } 508 509 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 510 error_setg(errp, 511 "H depends on an I base integer ISA with 32 x registers"); 512 return; 513 } 514 515 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 516 error_setg(errp, "H extension implicitly requires S-mode"); 517 return; 518 } 519 520 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 521 error_setg(errp, "F extension requires Zicsr"); 522 return; 523 } 524 525 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 526 error_setg(errp, "Zacas extension requires A extension"); 527 return; 528 } 529 530 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 531 error_setg(errp, "Zawrs extension requires A extension"); 532 return; 533 } 534 535 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 536 error_setg(errp, "Zfa extension requires F extension"); 537 return; 538 } 539 540 if (cpu->cfg.ext_zfh) { 541 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); 542 } 543 544 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 545 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 546 return; 547 } 548 549 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 550 error_setg(errp, "Zfbfmin extension depends on F extension"); 551 return; 552 } 553 554 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 555 error_setg(errp, "D extension requires F extension"); 556 return; 557 } 558 559 if (riscv_has_ext(env, RVV)) { 560 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 561 if (local_err != NULL) { 562 error_propagate(errp, local_err); 563 return; 564 } 565 566 /* The V vector extension depends on the Zve64d extension */ 567 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); 568 } 569 570 /* The Zve64d extension depends on the Zve64f extension */ 571 if (cpu->cfg.ext_zve64d) { 572 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); 573 } 574 575 /* The Zve64f extension depends on the Zve32f extension */ 576 if (cpu->cfg.ext_zve64f) { 577 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); 578 } 579 580 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 581 error_setg(errp, "Zve64d/V extensions require D extension"); 582 return; 583 } 584 585 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 586 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 587 return; 588 } 589 590 if (cpu->cfg.ext_zvfh) { 591 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); 592 } 593 594 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 595 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 596 return; 597 } 598 599 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 600 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 601 return; 602 } 603 604 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { 605 error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"); 606 return; 607 } 608 609 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 610 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 611 return; 612 } 613 614 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 615 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 616 return; 617 } 618 619 /* Set the ISA extensions, checks should have happened above */ 620 if (cpu->cfg.ext_zhinx) { 621 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 622 } 623 624 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 625 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 626 return; 627 } 628 629 if (cpu->cfg.ext_zfinx) { 630 if (!cpu->cfg.ext_zicsr) { 631 error_setg(errp, "Zfinx extension requires Zicsr"); 632 return; 633 } 634 if (riscv_has_ext(env, RVF)) { 635 error_setg(errp, 636 "Zfinx cannot be supported together with F extension"); 637 return; 638 } 639 } 640 641 if (cpu->cfg.ext_zce) { 642 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 643 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 644 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 645 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 646 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 647 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 648 } 649 } 650 651 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ 652 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 653 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 654 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 655 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 656 } 657 if (riscv_has_ext(env, RVD)) { 658 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 659 } 660 } 661 662 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 663 error_setg(errp, "Zcf extension is only relevant to RV32"); 664 return; 665 } 666 667 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 668 error_setg(errp, "Zcf extension requires F extension"); 669 return; 670 } 671 672 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 673 error_setg(errp, "Zcd extension requires D extension"); 674 return; 675 } 676 677 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 678 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 679 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 680 "extension"); 681 return; 682 } 683 684 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 685 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 686 "Zcd extension"); 687 return; 688 } 689 690 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 691 error_setg(errp, "Zcmt extension requires Zicsr extension"); 692 return; 693 } 694 695 /* 696 * Shorthand vector crypto extensions 697 */ 698 if (cpu->cfg.ext_zvknc) { 699 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); 700 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 701 } 702 703 if (cpu->cfg.ext_zvkng) { 704 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); 705 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); 706 } 707 708 if (cpu->cfg.ext_zvkn) { 709 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true); 710 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true); 711 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); 712 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); 713 } 714 715 if (cpu->cfg.ext_zvksc) { 716 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); 717 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 718 } 719 720 if (cpu->cfg.ext_zvksg) { 721 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); 722 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); 723 } 724 725 if (cpu->cfg.ext_zvks) { 726 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true); 727 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true); 728 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); 729 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); 730 } 731 732 if (cpu->cfg.ext_zvkt) { 733 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); 734 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 735 } 736 737 /* 738 * In principle Zve*x would also suffice here, were they supported 739 * in qemu 740 */ 741 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 742 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 743 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { 744 error_setg(errp, 745 "Vector crypto extensions require V or Zve* extensions"); 746 return; 747 } 748 749 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) { 750 error_setg( 751 errp, 752 "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions"); 753 return; 754 } 755 756 if (cpu->cfg.ext_zk) { 757 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); 758 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); 759 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); 760 } 761 762 if (cpu->cfg.ext_zkn) { 763 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 764 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 765 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 766 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); 767 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); 768 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); 769 } 770 771 if (cpu->cfg.ext_zks) { 772 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 773 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 774 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 775 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); 776 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); 777 } 778 779 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 780 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 781 error_setg(errp, "zicntr requires zicsr"); 782 return; 783 } 784 cpu->cfg.ext_zicntr = false; 785 } 786 787 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 788 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 789 error_setg(errp, "zihpm requires zicsr"); 790 return; 791 } 792 cpu->cfg.ext_zihpm = false; 793 } 794 795 if (!cpu->cfg.ext_zihpm) { 796 cpu->cfg.pmu_mask = 0; 797 cpu->pmu_avail_ctrs = 0; 798 } 799 800 /* 801 * Disable isa extensions based on priv spec after we 802 * validated and set everything we need. 803 */ 804 riscv_cpu_disable_priv_spec_isa_exts(cpu); 805 } 806 807 #ifndef CONFIG_USER_ONLY 808 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 809 RISCVCPUProfile *profile, 810 bool send_warn) 811 { 812 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 813 814 if (profile->satp_mode > satp_max) { 815 if (send_warn) { 816 bool is_32bit = riscv_cpu_is_32bit(cpu); 817 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 818 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 819 820 warn_report("Profile %s requires satp mode %s, " 821 "but satp mode %s was set", profile->name, 822 req_satp, cur_satp); 823 } 824 825 return false; 826 } 827 828 return true; 829 } 830 #endif 831 832 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 833 RISCVCPUProfile *profile) 834 { 835 CPURISCVState *env = &cpu->env; 836 const char *warn_msg = "Profile %s mandates disabled extension %s"; 837 bool send_warn = profile->user_set && profile->enabled; 838 bool parent_enabled, profile_impl = true; 839 int i; 840 841 #ifndef CONFIG_USER_ONLY 842 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 843 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 844 send_warn); 845 } 846 #endif 847 848 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 849 profile->priv_spec != env->priv_ver) { 850 profile_impl = false; 851 852 if (send_warn) { 853 warn_report("Profile %s requires priv spec %s, " 854 "but priv ver %s was set", profile->name, 855 cpu_priv_ver_to_str(profile->priv_spec), 856 cpu_priv_ver_to_str(env->priv_ver)); 857 } 858 } 859 860 for (i = 0; misa_bits[i] != 0; i++) { 861 uint32_t bit = misa_bits[i]; 862 863 if (!(profile->misa_ext & bit)) { 864 continue; 865 } 866 867 if (!riscv_has_ext(&cpu->env, bit)) { 868 profile_impl = false; 869 870 if (send_warn) { 871 warn_report(warn_msg, profile->name, 872 riscv_get_misa_ext_name(bit)); 873 } 874 } 875 } 876 877 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 878 int ext_offset = profile->ext_offsets[i]; 879 880 if (!isa_ext_is_enabled(cpu, ext_offset)) { 881 profile_impl = false; 882 883 if (send_warn) { 884 warn_report(warn_msg, profile->name, 885 cpu_cfg_ext_get_name(ext_offset)); 886 } 887 } 888 } 889 890 profile->enabled = profile_impl; 891 892 if (profile->parent != NULL) { 893 parent_enabled = object_property_get_bool(OBJECT(cpu), 894 profile->parent->name, 895 NULL); 896 profile->enabled = profile->enabled && parent_enabled; 897 } 898 } 899 900 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 901 { 902 for (int i = 0; riscv_profiles[i] != NULL; i++) { 903 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 904 } 905 } 906 907 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 908 { 909 CPURISCVState *env = &cpu->env; 910 Error *local_err = NULL; 911 912 riscv_cpu_validate_priv_spec(cpu, &local_err); 913 if (local_err != NULL) { 914 error_propagate(errp, local_err); 915 return; 916 } 917 918 riscv_cpu_validate_misa_priv(env, &local_err); 919 if (local_err != NULL) { 920 error_propagate(errp, local_err); 921 return; 922 } 923 924 riscv_cpu_update_named_features(cpu); 925 riscv_cpu_validate_profiles(cpu); 926 927 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 928 /* 929 * Enhanced PMP should only be available 930 * on harts with PMP support 931 */ 932 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 933 return; 934 } 935 936 riscv_cpu_validate_set_extensions(cpu, &local_err); 937 if (local_err != NULL) { 938 error_propagate(errp, local_err); 939 return; 940 } 941 } 942 943 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 944 { 945 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 946 } 947 948 static bool riscv_cpu_is_generic(Object *cpu_obj) 949 { 950 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 951 } 952 953 static bool riscv_cpu_is_vendor(Object *cpu_obj) 954 { 955 return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) != NULL; 956 } 957 958 /* 959 * We'll get here via the following path: 960 * 961 * riscv_cpu_realize() 962 * -> cpu_exec_realizefn() 963 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 964 */ 965 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 966 { 967 RISCVCPU *cpu = RISCV_CPU(cs); 968 Error *local_err = NULL; 969 970 if (!riscv_cpu_tcg_compatible(cpu)) { 971 g_autofree char *name = riscv_cpu_get_name(cpu); 972 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 973 name); 974 return false; 975 } 976 977 riscv_cpu_validate_misa_mxl(cpu, &local_err); 978 if (local_err != NULL) { 979 error_propagate(errp, local_err); 980 return false; 981 } 982 983 #ifndef CONFIG_USER_ONLY 984 CPURISCVState *env = &cpu->env; 985 986 CPU(cs)->tcg_cflags |= CF_PCREL; 987 988 if (cpu->cfg.ext_sstc) { 989 riscv_timer_init(cpu); 990 } 991 992 if (cpu->cfg.pmu_mask) { 993 riscv_pmu_init(cpu, &local_err); 994 if (local_err != NULL) { 995 error_propagate(errp, local_err); 996 return false; 997 } 998 999 if (cpu->cfg.ext_sscofpmf) { 1000 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1001 riscv_pmu_timer_cb, cpu); 1002 } 1003 } 1004 1005 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 1006 if (riscv_has_ext(env, RVH)) { 1007 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 1008 } 1009 #endif 1010 1011 return true; 1012 } 1013 1014 typedef struct RISCVCPUMisaExtConfig { 1015 target_ulong misa_bit; 1016 bool enabled; 1017 } RISCVCPUMisaExtConfig; 1018 1019 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1020 void *opaque, Error **errp) 1021 { 1022 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1023 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1024 RISCVCPU *cpu = RISCV_CPU(obj); 1025 CPURISCVState *env = &cpu->env; 1026 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1027 bool prev_val, value; 1028 1029 if (!visit_type_bool(v, name, &value, errp)) { 1030 return; 1031 } 1032 1033 cpu_misa_ext_add_user_opt(misa_bit, value); 1034 1035 prev_val = env->misa_ext & misa_bit; 1036 1037 if (value == prev_val) { 1038 return; 1039 } 1040 1041 if (value) { 1042 if (vendor_cpu) { 1043 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1044 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1045 cpuname); 1046 return; 1047 } 1048 1049 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 1050 /* 1051 * Note: the 'priv_spec' command line option, if present, 1052 * will take precedence over this priv_ver bump. 1053 */ 1054 env->priv_ver = PRIV_VERSION_1_12_0; 1055 } 1056 } 1057 1058 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1059 } 1060 1061 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1062 void *opaque, Error **errp) 1063 { 1064 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1065 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1066 RISCVCPU *cpu = RISCV_CPU(obj); 1067 CPURISCVState *env = &cpu->env; 1068 bool value; 1069 1070 value = env->misa_ext & misa_bit; 1071 1072 visit_type_bool(v, name, &value, errp); 1073 } 1074 1075 #define MISA_CFG(_bit, _enabled) \ 1076 {.misa_bit = _bit, .enabled = _enabled} 1077 1078 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1079 MISA_CFG(RVA, true), 1080 MISA_CFG(RVC, true), 1081 MISA_CFG(RVD, true), 1082 MISA_CFG(RVF, true), 1083 MISA_CFG(RVI, true), 1084 MISA_CFG(RVE, false), 1085 MISA_CFG(RVM, true), 1086 MISA_CFG(RVS, true), 1087 MISA_CFG(RVU, true), 1088 MISA_CFG(RVH, true), 1089 MISA_CFG(RVJ, false), 1090 MISA_CFG(RVV, false), 1091 MISA_CFG(RVG, false), 1092 MISA_CFG(RVB, false), 1093 }; 1094 1095 /* 1096 * We do not support user choice tracking for MISA 1097 * extensions yet because, so far, we do not silently 1098 * change MISA bits during realize() (RVG enables MISA 1099 * bits but the user is warned about it). 1100 */ 1101 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1102 { 1103 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1104 int i; 1105 1106 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1107 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1108 int bit = misa_cfg->misa_bit; 1109 const char *name = riscv_get_misa_ext_name(bit); 1110 const char *desc = riscv_get_misa_ext_description(bit); 1111 1112 /* Check if KVM already created the property */ 1113 if (object_property_find(cpu_obj, name)) { 1114 continue; 1115 } 1116 1117 object_property_add(cpu_obj, name, "bool", 1118 cpu_get_misa_ext_cfg, 1119 cpu_set_misa_ext_cfg, 1120 NULL, (void *)misa_cfg); 1121 object_property_set_description(cpu_obj, name, desc); 1122 if (use_def_vals) { 1123 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1124 misa_cfg->enabled); 1125 } 1126 } 1127 } 1128 1129 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1130 void *opaque, Error **errp) 1131 { 1132 RISCVCPUProfile *profile = opaque; 1133 RISCVCPU *cpu = RISCV_CPU(obj); 1134 bool value; 1135 int i, ext_offset; 1136 1137 if (riscv_cpu_is_vendor(obj)) { 1138 error_setg(errp, "Profile %s is not available for vendor CPUs", 1139 profile->name); 1140 return; 1141 } 1142 1143 if (cpu->env.misa_mxl != MXL_RV64) { 1144 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1145 profile->name); 1146 return; 1147 } 1148 1149 if (!visit_type_bool(v, name, &value, errp)) { 1150 return; 1151 } 1152 1153 profile->user_set = true; 1154 profile->enabled = value; 1155 1156 if (profile->parent != NULL) { 1157 object_property_set_bool(obj, profile->parent->name, 1158 profile->enabled, NULL); 1159 } 1160 1161 if (profile->enabled) { 1162 cpu->env.priv_ver = profile->priv_spec; 1163 } 1164 1165 #ifndef CONFIG_USER_ONLY 1166 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1167 const char *satp_prop = satp_mode_str(profile->satp_mode, 1168 riscv_cpu_is_32bit(cpu)); 1169 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1170 } 1171 #endif 1172 1173 for (i = 0; misa_bits[i] != 0; i++) { 1174 uint32_t bit = misa_bits[i]; 1175 1176 if (!(profile->misa_ext & bit)) { 1177 continue; 1178 } 1179 1180 if (bit == RVI && !profile->enabled) { 1181 /* 1182 * Disabling profiles will not disable the base 1183 * ISA RV64I. 1184 */ 1185 continue; 1186 } 1187 1188 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1189 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1190 } 1191 1192 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1193 ext_offset = profile->ext_offsets[i]; 1194 1195 if (profile->enabled) { 1196 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1197 riscv_cpu_enable_named_feat(cpu, ext_offset); 1198 } 1199 1200 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1201 } 1202 1203 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1204 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1205 } 1206 } 1207 1208 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1209 void *opaque, Error **errp) 1210 { 1211 RISCVCPUProfile *profile = opaque; 1212 bool value = profile->enabled; 1213 1214 visit_type_bool(v, name, &value, errp); 1215 } 1216 1217 static void riscv_cpu_add_profiles(Object *cpu_obj) 1218 { 1219 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1220 const RISCVCPUProfile *profile = riscv_profiles[i]; 1221 1222 object_property_add(cpu_obj, profile->name, "bool", 1223 cpu_get_profile, cpu_set_profile, 1224 NULL, (void *)profile); 1225 1226 /* 1227 * CPUs might enable a profile right from the start. 1228 * Enable its mandatory extensions right away in this 1229 * case. 1230 */ 1231 if (profile->enabled) { 1232 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1233 } 1234 } 1235 } 1236 1237 static bool cpu_ext_is_deprecated(const char *ext_name) 1238 { 1239 return isupper(ext_name[0]); 1240 } 1241 1242 /* 1243 * String will be allocated in the heap. Caller is responsible 1244 * for freeing it. 1245 */ 1246 static char *cpu_ext_to_lower(const char *ext_name) 1247 { 1248 char *ret = g_malloc0(strlen(ext_name) + 1); 1249 1250 strcpy(ret, ext_name); 1251 ret[0] = tolower(ret[0]); 1252 1253 return ret; 1254 } 1255 1256 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1257 void *opaque, Error **errp) 1258 { 1259 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1260 RISCVCPU *cpu = RISCV_CPU(obj); 1261 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1262 bool prev_val, value; 1263 1264 if (!visit_type_bool(v, name, &value, errp)) { 1265 return; 1266 } 1267 1268 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1269 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1270 1271 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1272 multi_ext_cfg->name, lower); 1273 } 1274 1275 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1276 1277 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1278 1279 if (value == prev_val) { 1280 return; 1281 } 1282 1283 if (value && vendor_cpu) { 1284 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1285 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1286 cpuname); 1287 return; 1288 } 1289 1290 if (value) { 1291 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1292 } 1293 1294 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1295 } 1296 1297 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1298 void *opaque, Error **errp) 1299 { 1300 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1301 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1302 1303 visit_type_bool(v, name, &value, errp); 1304 } 1305 1306 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1307 const RISCVCPUMultiExtConfig *multi_cfg) 1308 { 1309 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1310 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1311 1312 object_property_add(cpu_obj, multi_cfg->name, "bool", 1313 cpu_get_multi_ext_cfg, 1314 cpu_set_multi_ext_cfg, 1315 NULL, (void *)multi_cfg); 1316 1317 if (!generic_cpu || deprecated_ext) { 1318 return; 1319 } 1320 1321 /* 1322 * Set def val directly instead of using 1323 * object_property_set_bool() to save the set() 1324 * callback hash for user inputs. 1325 */ 1326 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1327 multi_cfg->enabled); 1328 } 1329 1330 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1331 const RISCVCPUMultiExtConfig *array) 1332 { 1333 const RISCVCPUMultiExtConfig *prop; 1334 1335 g_assert(array); 1336 1337 for (prop = array; prop && prop->name; prop++) { 1338 cpu_add_multi_ext_prop(obj, prop); 1339 } 1340 } 1341 1342 /* 1343 * Add CPU properties with user-facing flags. 1344 * 1345 * This will overwrite existing env->misa_ext values with the 1346 * defaults set via riscv_cpu_add_misa_properties(). 1347 */ 1348 static void riscv_cpu_add_user_properties(Object *obj) 1349 { 1350 #ifndef CONFIG_USER_ONLY 1351 riscv_add_satp_mode_properties(obj); 1352 #endif 1353 1354 riscv_cpu_add_misa_properties(obj); 1355 1356 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1357 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1358 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1359 1360 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1361 1362 riscv_cpu_add_profiles(obj); 1363 1364 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1365 qdev_property_add_static(DEVICE(obj), prop); 1366 } 1367 } 1368 1369 /* 1370 * The 'max' type CPU will have all possible ratified 1371 * non-vendor extensions enabled. 1372 */ 1373 static void riscv_init_max_cpu_extensions(Object *obj) 1374 { 1375 RISCVCPU *cpu = RISCV_CPU(obj); 1376 CPURISCVState *env = &cpu->env; 1377 const RISCVCPUMultiExtConfig *prop; 1378 1379 /* Enable RVG, RVJ and RVV that are disabled by default */ 1380 riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); 1381 1382 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1383 isa_ext_update_enabled(cpu, prop->offset, true); 1384 } 1385 1386 /* set vector version */ 1387 env->vext_ver = VEXT_VERSION_1_00_0; 1388 1389 /* Zfinx is not compatible with F. Disable it */ 1390 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1391 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1392 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1393 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1394 1395 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1396 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1397 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1398 1399 if (env->misa_mxl != MXL_RV32) { 1400 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1401 } 1402 } 1403 1404 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1405 { 1406 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1407 } 1408 1409 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1410 { 1411 RISCVCPU *cpu = RISCV_CPU(cs); 1412 Object *obj = OBJECT(cpu); 1413 1414 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1415 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1416 riscv_cpu_add_user_properties(obj); 1417 1418 if (riscv_cpu_has_max_extensions(obj)) { 1419 riscv_init_max_cpu_extensions(obj); 1420 } 1421 } 1422 1423 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1424 { 1425 /* 1426 * All cpus use the same set of operations. 1427 */ 1428 cc->tcg_ops = &riscv_tcg_ops; 1429 } 1430 1431 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1432 { 1433 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1434 } 1435 1436 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1437 { 1438 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1439 1440 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1441 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1442 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1443 } 1444 1445 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1446 .name = ACCEL_CPU_NAME("tcg"), 1447 1448 .parent = TYPE_ACCEL_CPU, 1449 .class_init = riscv_tcg_cpu_accel_class_init, 1450 .abstract = true, 1451 }; 1452 1453 static void riscv_tcg_cpu_accel_register_types(void) 1454 { 1455 type_register_static(&riscv_tcg_cpu_accel_type_info); 1456 } 1457 type_init(riscv_tcg_cpu_accel_register_types); 1458