1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "exec/translation-block.h" 23 #include "tcg-cpu.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "pmu.h" 27 #include "time_helper.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "qemu/accel.h" 31 #include "qemu/error-report.h" 32 #include "qemu/log.h" 33 #include "hw/core/accel-cpu.h" 34 #include "hw/core/tcg-cpu-ops.h" 35 #include "tcg/tcg.h" 36 #ifndef CONFIG_USER_ONLY 37 #include "hw/boards.h" 38 #endif 39 40 /* Hash that stores user set extensions */ 41 static GHashTable *multi_ext_user_opts; 42 static GHashTable *misa_ext_user_opts; 43 44 static GHashTable *multi_ext_implied_rules; 45 static GHashTable *misa_ext_implied_rules; 46 47 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 48 { 49 return g_hash_table_contains(multi_ext_user_opts, 50 GUINT_TO_POINTER(ext_offset)); 51 } 52 53 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 54 { 55 return g_hash_table_contains(misa_ext_user_opts, 56 GUINT_TO_POINTER(misa_bit)); 57 } 58 59 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 60 { 61 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 62 (gpointer)value); 63 } 64 65 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 66 { 67 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 68 (gpointer)value); 69 } 70 71 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 72 bool enabled) 73 { 74 CPURISCVState *env = &cpu->env; 75 76 if (enabled) { 77 env->misa_ext |= bit; 78 env->misa_ext_mask |= bit; 79 } else { 80 env->misa_ext &= ~bit; 81 env->misa_ext_mask &= ~bit; 82 } 83 } 84 85 static const char *cpu_priv_ver_to_str(int priv_ver) 86 { 87 const char *priv_spec_str = priv_spec_to_str(priv_ver); 88 89 g_assert(priv_spec_str); 90 91 return priv_spec_str; 92 } 93 94 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 95 const TranslationBlock *tb) 96 { 97 if (!(tb_cflags(tb) & CF_PCREL)) { 98 RISCVCPU *cpu = RISCV_CPU(cs); 99 CPURISCVState *env = &cpu->env; 100 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 101 102 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 103 104 if (xl == MXL_RV32) { 105 env->pc = (int32_t) tb->pc; 106 } else { 107 env->pc = tb->pc; 108 } 109 } 110 } 111 112 static void riscv_restore_state_to_opc(CPUState *cs, 113 const TranslationBlock *tb, 114 const uint64_t *data) 115 { 116 RISCVCPU *cpu = RISCV_CPU(cs); 117 CPURISCVState *env = &cpu->env; 118 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 119 target_ulong pc; 120 121 if (tb_cflags(tb) & CF_PCREL) { 122 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 123 } else { 124 pc = data[0]; 125 } 126 127 if (xl == MXL_RV32) { 128 env->pc = (int32_t)pc; 129 } else { 130 env->pc = pc; 131 } 132 env->bins = data[1]; 133 env->excp_uw2 = data[2]; 134 } 135 136 static const TCGCPUOps riscv_tcg_ops = { 137 .initialize = riscv_translate_init, 138 .translate_code = riscv_translate_code, 139 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 140 .restore_state_to_opc = riscv_restore_state_to_opc, 141 142 #ifndef CONFIG_USER_ONLY 143 .tlb_fill = riscv_cpu_tlb_fill, 144 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 145 .cpu_exec_halt = riscv_cpu_has_work, 146 .do_interrupt = riscv_cpu_do_interrupt, 147 .do_transaction_failed = riscv_cpu_do_transaction_failed, 148 .do_unaligned_access = riscv_cpu_do_unaligned_access, 149 .debug_excp_handler = riscv_cpu_debug_excp_handler, 150 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 151 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 152 #endif /* !CONFIG_USER_ONLY */ 153 }; 154 155 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 156 { 157 const RISCVIsaExtData *edata; 158 159 for (edata = isa_edata_arr; edata && edata->name; edata++) { 160 if (edata->ext_enable_offset != ext_offset) { 161 continue; 162 } 163 164 return edata->min_version; 165 } 166 167 g_assert_not_reached(); 168 } 169 170 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 171 { 172 const RISCVCPUMultiExtConfig *feat; 173 const RISCVIsaExtData *edata; 174 175 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 176 if (edata->ext_enable_offset == ext_offset) { 177 return edata->name; 178 } 179 } 180 181 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 182 if (feat->offset == ext_offset) { 183 return feat->name; 184 } 185 } 186 187 g_assert_not_reached(); 188 } 189 190 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 191 { 192 const RISCVCPUMultiExtConfig *feat; 193 194 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 195 if (feat->offset == ext_offset) { 196 return true; 197 } 198 } 199 200 return false; 201 } 202 203 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 204 { 205 /* 206 * All other named features are already enabled 207 * in riscv_tcg_cpu_instance_init(). 208 */ 209 switch (feat_offset) { 210 case CPU_CFG_OFFSET(ext_zic64b): 211 cpu->cfg.cbom_blocksize = 64; 212 cpu->cfg.cbop_blocksize = 64; 213 cpu->cfg.cboz_blocksize = 64; 214 break; 215 case CPU_CFG_OFFSET(ext_sha): 216 if (!cpu_misa_ext_is_user_set(RVH)) { 217 riscv_cpu_write_misa_bit(cpu, RVH, true); 218 } 219 /* fallthrough */ 220 case CPU_CFG_OFFSET(ext_ssstateen): 221 cpu->cfg.ext_smstateen = true; 222 break; 223 } 224 } 225 226 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 227 uint32_t ext_offset) 228 { 229 int ext_priv_ver; 230 231 if (env->priv_ver == PRIV_VERSION_LATEST) { 232 return; 233 } 234 235 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 236 237 if (env->priv_ver < ext_priv_ver) { 238 /* 239 * Note: the 'priv_spec' command line option, if present, 240 * will take precedence over this priv_ver bump. 241 */ 242 env->priv_ver = ext_priv_ver; 243 } 244 } 245 246 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 247 bool value) 248 { 249 CPURISCVState *env = &cpu->env; 250 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 251 int min_version; 252 253 if (prev_val == value) { 254 return; 255 } 256 257 if (cpu_cfg_ext_is_user_set(ext_offset)) { 258 return; 259 } 260 261 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 262 /* Do not enable it if priv_ver is older than min_version */ 263 min_version = cpu_cfg_ext_get_min_version(ext_offset); 264 if (env->priv_ver < min_version) { 265 return; 266 } 267 } 268 269 isa_ext_update_enabled(cpu, ext_offset, value); 270 } 271 272 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 273 { 274 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 275 error_setg(errp, "H extension requires priv spec 1.12.0"); 276 return; 277 } 278 } 279 280 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 281 Error **errp) 282 { 283 uint32_t vlen = cfg->vlenb << 3; 284 285 if (vlen > RV_VLEN_MAX || vlen < 128) { 286 error_setg(errp, 287 "Vector extension implementation only supports VLEN " 288 "in the range [128, %d]", RV_VLEN_MAX); 289 return; 290 } 291 292 if (cfg->elen > 64 || cfg->elen < 8) { 293 error_setg(errp, 294 "Vector extension implementation only supports ELEN " 295 "in the range [8, 64]"); 296 return; 297 } 298 } 299 300 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 301 { 302 CPURISCVState *env = &cpu->env; 303 const RISCVIsaExtData *edata; 304 305 /* Force disable extensions if priv spec version does not match */ 306 for (edata = isa_edata_arr; edata && edata->name; edata++) { 307 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 308 (env->priv_ver < edata->min_version)) { 309 /* 310 * These two extensions are always enabled as they were supported 311 * by QEMU before they were added as extensions in the ISA. 312 */ 313 if (!strcmp(edata->name, "zicntr") || 314 !strcmp(edata->name, "zihpm")) { 315 continue; 316 } 317 318 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 319 320 /* 321 * Do not show user warnings for named features that users 322 * can't enable/disable in the command line. See commit 323 * 68c9e54bea for more info. 324 */ 325 if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) { 326 continue; 327 } 328 #ifndef CONFIG_USER_ONLY 329 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 330 " because privilege spec version does not match", 331 edata->name, env->mhartid); 332 #else 333 warn_report("disabling %s extension because " 334 "privilege spec version does not match", 335 edata->name); 336 #endif 337 } 338 } 339 } 340 341 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 342 { 343 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { 344 cpu->cfg.has_priv_1_11 = true; 345 } 346 347 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { 348 cpu->cfg.has_priv_1_12 = true; 349 } 350 351 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { 352 cpu->cfg.has_priv_1_13 = true; 353 } 354 355 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && 356 cpu->cfg.cbop_blocksize == 64 && 357 cpu->cfg.cboz_blocksize == 64; 358 359 cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; 360 361 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && 362 cpu->cfg.ext_ssstateen; 363 } 364 365 static void riscv_cpu_validate_g(RISCVCPU *cpu) 366 { 367 const char *warn_msg = "RVG mandates disabled extension %s"; 368 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 369 bool send_warn = cpu_misa_ext_is_user_set(RVG); 370 371 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 372 uint32_t bit = g_misa_bits[i]; 373 374 if (riscv_has_ext(&cpu->env, bit)) { 375 continue; 376 } 377 378 if (!cpu_misa_ext_is_user_set(bit)) { 379 riscv_cpu_write_misa_bit(cpu, bit, true); 380 continue; 381 } 382 383 if (send_warn) { 384 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 385 } 386 } 387 388 if (!cpu->cfg.ext_zicsr) { 389 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 390 cpu->cfg.ext_zicsr = true; 391 } else if (send_warn) { 392 warn_report(warn_msg, "zicsr"); 393 } 394 } 395 396 if (!cpu->cfg.ext_zifencei) { 397 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 398 cpu->cfg.ext_zifencei = true; 399 } else if (send_warn) { 400 warn_report(warn_msg, "zifencei"); 401 } 402 } 403 } 404 405 static void riscv_cpu_validate_b(RISCVCPU *cpu) 406 { 407 const char *warn_msg = "RVB mandates disabled extension %s"; 408 409 if (!cpu->cfg.ext_zba) { 410 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 411 cpu->cfg.ext_zba = true; 412 } else { 413 warn_report(warn_msg, "zba"); 414 } 415 } 416 417 if (!cpu->cfg.ext_zbb) { 418 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 419 cpu->cfg.ext_zbb = true; 420 } else { 421 warn_report(warn_msg, "zbb"); 422 } 423 } 424 425 if (!cpu->cfg.ext_zbs) { 426 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 427 cpu->cfg.ext_zbs = true; 428 } else { 429 warn_report(warn_msg, "zbs"); 430 } 431 } 432 } 433 434 /* 435 * Check consistency between chosen extensions while setting 436 * cpu->cfg accordingly. 437 */ 438 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 439 { 440 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 441 CPURISCVState *env = &cpu->env; 442 Error *local_err = NULL; 443 444 if (riscv_has_ext(env, RVG)) { 445 riscv_cpu_validate_g(cpu); 446 } 447 448 if (riscv_has_ext(env, RVB)) { 449 riscv_cpu_validate_b(cpu); 450 } 451 452 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 453 error_setg(errp, 454 "I and E extensions are incompatible"); 455 return; 456 } 457 458 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 459 error_setg(errp, 460 "Either I or E extension must be set"); 461 return; 462 } 463 464 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 465 error_setg(errp, 466 "Setting S extension without U extension is illegal"); 467 return; 468 } 469 470 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 471 error_setg(errp, 472 "H depends on an I base integer ISA with 32 x registers"); 473 return; 474 } 475 476 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 477 error_setg(errp, "H extension implicitly requires S-mode"); 478 return; 479 } 480 481 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 482 error_setg(errp, "F extension requires Zicsr"); 483 return; 484 } 485 486 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 487 error_setg(errp, "Zacas extension requires A extension"); 488 return; 489 } 490 491 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 492 error_setg(errp, "Zawrs extension requires A extension"); 493 return; 494 } 495 496 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 497 error_setg(errp, "Zfa extension requires F extension"); 498 return; 499 } 500 501 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 502 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 503 return; 504 } 505 506 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 507 error_setg(errp, "Zfbfmin extension depends on F extension"); 508 return; 509 } 510 511 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 512 error_setg(errp, "D extension requires F extension"); 513 return; 514 } 515 516 if (riscv_has_ext(env, RVV)) { 517 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 518 if (local_err != NULL) { 519 error_propagate(errp, local_err); 520 return; 521 } 522 } 523 524 /* The Zve64d extension depends on the Zve64f extension */ 525 if (cpu->cfg.ext_zve64d) { 526 if (!riscv_has_ext(env, RVD)) { 527 error_setg(errp, "Zve64d/V extensions require D extension"); 528 return; 529 } 530 } 531 532 /* The Zve32f extension depends on the Zve32x extension */ 533 if (cpu->cfg.ext_zve32f) { 534 if (!riscv_has_ext(env, RVF)) { 535 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 536 return; 537 } 538 } 539 540 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 541 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 542 return; 543 } 544 545 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 546 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 547 return; 548 } 549 550 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 551 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 552 return; 553 } 554 555 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 556 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 557 return; 558 } 559 560 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 561 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 562 return; 563 } 564 565 if (cpu->cfg.ext_zfinx) { 566 if (!cpu->cfg.ext_zicsr) { 567 error_setg(errp, "Zfinx extension requires Zicsr"); 568 return; 569 } 570 if (riscv_has_ext(env, RVF)) { 571 error_setg(errp, 572 "Zfinx cannot be supported together with F extension"); 573 return; 574 } 575 } 576 577 if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { 578 error_setg(errp, "Zcmop extensions require Zca"); 579 return; 580 } 581 582 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 583 error_setg(errp, "Zcf extension is only relevant to RV32"); 584 return; 585 } 586 587 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 588 error_setg(errp, "Zcf extension requires F extension"); 589 return; 590 } 591 592 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 593 error_setg(errp, "Zcd extension requires D extension"); 594 return; 595 } 596 597 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 598 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 599 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 600 "extension"); 601 return; 602 } 603 604 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 605 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 606 "Zcd extension"); 607 return; 608 } 609 610 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 611 error_setg(errp, "Zcmt extension requires Zicsr extension"); 612 return; 613 } 614 615 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 616 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 617 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { 618 error_setg(errp, 619 "Vector crypto extensions require V or Zve* extensions"); 620 return; 621 } 622 623 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { 624 error_setg( 625 errp, 626 "Zvbc and Zvknhb extensions require V or Zve64x extensions"); 627 return; 628 } 629 630 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 631 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 632 error_setg(errp, "zicntr requires zicsr"); 633 return; 634 } 635 cpu->cfg.ext_zicntr = false; 636 } 637 638 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 639 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 640 error_setg(errp, "zihpm requires zicsr"); 641 return; 642 } 643 cpu->cfg.ext_zihpm = false; 644 } 645 646 if (cpu->cfg.ext_zicfiss) { 647 if (!cpu->cfg.ext_zicsr) { 648 error_setg(errp, "zicfiss extension requires zicsr extension"); 649 return; 650 } 651 if (!riscv_has_ext(env, RVA)) { 652 error_setg(errp, "zicfiss extension requires A extension"); 653 return; 654 } 655 if (!riscv_has_ext(env, RVS)) { 656 error_setg(errp, "zicfiss extension requires S"); 657 return; 658 } 659 if (!cpu->cfg.ext_zimop) { 660 error_setg(errp, "zicfiss extension requires zimop extension"); 661 return; 662 } 663 if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { 664 error_setg(errp, "zicfiss with zca requires zcmop extension"); 665 return; 666 } 667 } 668 669 if (!cpu->cfg.ext_zihpm) { 670 cpu->cfg.pmu_mask = 0; 671 cpu->pmu_avail_ctrs = 0; 672 } 673 674 if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { 675 error_setg(errp, "zicfilp extension requires zicsr extension"); 676 return; 677 } 678 679 if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { 680 error_setg(errp, "svukte is not supported for RV32"); 681 return; 682 } 683 684 if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && 685 (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { 686 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) || 687 cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) { 688 error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind"); 689 return; 690 } 691 cpu->cfg.ext_smctr = false; 692 cpu->cfg.ext_ssctr = false; 693 } 694 695 /* 696 * Disable isa extensions based on priv spec after we 697 * validated and set everything we need. 698 */ 699 riscv_cpu_disable_priv_spec_isa_exts(cpu); 700 } 701 702 #ifndef CONFIG_USER_ONLY 703 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 704 RISCVCPUProfile *profile, 705 bool send_warn) 706 { 707 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 708 709 if (profile->satp_mode > satp_max) { 710 if (send_warn) { 711 bool is_32bit = riscv_cpu_is_32bit(cpu); 712 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 713 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 714 715 warn_report("Profile %s requires satp mode %s, " 716 "but satp mode %s was set", profile->name, 717 req_satp, cur_satp); 718 } 719 720 return false; 721 } 722 723 return true; 724 } 725 #endif 726 727 static void riscv_cpu_check_parent_profile(RISCVCPU *cpu, 728 RISCVCPUProfile *profile, 729 RISCVCPUProfile *parent) 730 { 731 const char *parent_name; 732 bool parent_enabled; 733 734 if (!profile->enabled || !parent) { 735 return; 736 } 737 738 parent_name = parent->name; 739 parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, NULL); 740 profile->enabled = parent_enabled; 741 } 742 743 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 744 RISCVCPUProfile *profile) 745 { 746 CPURISCVState *env = &cpu->env; 747 const char *warn_msg = "Profile %s mandates disabled extension %s"; 748 bool send_warn = profile->user_set && profile->enabled; 749 bool profile_impl = true; 750 int i; 751 752 #ifndef CONFIG_USER_ONLY 753 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 754 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 755 send_warn); 756 } 757 #endif 758 759 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 760 profile->priv_spec > env->priv_ver) { 761 profile_impl = false; 762 763 if (send_warn) { 764 warn_report("Profile %s requires priv spec %s, " 765 "but priv ver %s was set", profile->name, 766 cpu_priv_ver_to_str(profile->priv_spec), 767 cpu_priv_ver_to_str(env->priv_ver)); 768 } 769 } 770 771 for (i = 0; misa_bits[i] != 0; i++) { 772 uint32_t bit = misa_bits[i]; 773 774 if (!(profile->misa_ext & bit)) { 775 continue; 776 } 777 778 if (!riscv_has_ext(&cpu->env, bit)) { 779 profile_impl = false; 780 781 if (send_warn) { 782 warn_report(warn_msg, profile->name, 783 riscv_get_misa_ext_name(bit)); 784 } 785 } 786 } 787 788 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 789 int ext_offset = profile->ext_offsets[i]; 790 791 if (!isa_ext_is_enabled(cpu, ext_offset)) { 792 profile_impl = false; 793 794 if (send_warn) { 795 warn_report(warn_msg, profile->name, 796 cpu_cfg_ext_get_name(ext_offset)); 797 } 798 } 799 } 800 801 profile->enabled = profile_impl; 802 803 riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); 804 riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); 805 } 806 807 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 808 { 809 for (int i = 0; riscv_profiles[i] != NULL; i++) { 810 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 811 } 812 } 813 814 static void riscv_cpu_init_implied_exts_rules(void) 815 { 816 RISCVCPUImpliedExtsRule *rule; 817 #ifndef CONFIG_USER_ONLY 818 MachineState *ms = MACHINE(qdev_get_machine()); 819 #endif 820 static bool initialized; 821 int i; 822 823 /* Implied rules only need to be initialized once. */ 824 if (initialized) { 825 return; 826 } 827 828 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 829 #ifndef CONFIG_USER_ONLY 830 rule->enabled = bitmap_new(ms->smp.cpus); 831 #endif 832 g_hash_table_insert(misa_ext_implied_rules, 833 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 834 } 835 836 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 837 #ifndef CONFIG_USER_ONLY 838 rule->enabled = bitmap_new(ms->smp.cpus); 839 #endif 840 g_hash_table_insert(multi_ext_implied_rules, 841 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 842 } 843 844 initialized = true; 845 } 846 847 static void cpu_enable_implied_rule(RISCVCPU *cpu, 848 RISCVCPUImpliedExtsRule *rule) 849 { 850 CPURISCVState *env = &cpu->env; 851 RISCVCPUImpliedExtsRule *ir; 852 bool enabled = false; 853 int i; 854 855 #ifndef CONFIG_USER_ONLY 856 enabled = test_bit(cpu->env.mhartid, rule->enabled); 857 #endif 858 859 if (!enabled) { 860 /* Enable the implied MISAs. */ 861 if (rule->implied_misa_exts) { 862 for (i = 0; misa_bits[i] != 0; i++) { 863 if (rule->implied_misa_exts & misa_bits[i]) { 864 /* 865 * If the user disabled the misa_bit do not re-enable it 866 * and do not apply any implied rules related to it. 867 */ 868 if (cpu_misa_ext_is_user_set(misa_bits[i]) && 869 !(env->misa_ext & misa_bits[i])) { 870 continue; 871 } 872 873 riscv_cpu_set_misa_ext(env, env->misa_ext | misa_bits[i]); 874 ir = g_hash_table_lookup(misa_ext_implied_rules, 875 GUINT_TO_POINTER(misa_bits[i])); 876 877 if (ir) { 878 cpu_enable_implied_rule(cpu, ir); 879 } 880 } 881 } 882 } 883 884 /* Enable the implied extensions. */ 885 for (i = 0; 886 rule->implied_multi_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) { 887 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); 888 889 ir = g_hash_table_lookup(multi_ext_implied_rules, 890 GUINT_TO_POINTER( 891 rule->implied_multi_exts[i])); 892 893 if (ir) { 894 cpu_enable_implied_rule(cpu, ir); 895 } 896 } 897 898 #ifndef CONFIG_USER_ONLY 899 bitmap_set(rule->enabled, cpu->env.mhartid, 1); 900 #endif 901 } 902 } 903 904 /* Zc extension has special implied rules that need to be handled separately. */ 905 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) 906 { 907 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 908 CPURISCVState *env = &cpu->env; 909 910 if (cpu->cfg.ext_zce) { 911 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 912 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 913 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 914 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 915 916 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 917 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 918 } 919 } 920 921 /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ 922 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 923 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 924 925 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 926 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 927 } 928 929 if (riscv_has_ext(env, RVD)) { 930 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 931 } 932 } 933 } 934 935 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) 936 { 937 RISCVCPUImpliedExtsRule *rule; 938 int i; 939 940 /* Enable the implied extensions for Zc. */ 941 cpu_enable_zc_implied_rules(cpu); 942 943 /* Enable the implied MISAs. */ 944 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 945 if (riscv_has_ext(&cpu->env, rule->ext)) { 946 cpu_enable_implied_rule(cpu, rule); 947 } 948 } 949 950 /* Enable the implied extensions. */ 951 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 952 if (isa_ext_is_enabled(cpu, rule->ext)) { 953 cpu_enable_implied_rule(cpu, rule); 954 } 955 } 956 } 957 958 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 959 { 960 CPURISCVState *env = &cpu->env; 961 Error *local_err = NULL; 962 963 riscv_cpu_init_implied_exts_rules(); 964 riscv_cpu_enable_implied_rules(cpu); 965 966 riscv_cpu_validate_misa_priv(env, &local_err); 967 if (local_err != NULL) { 968 error_propagate(errp, local_err); 969 return; 970 } 971 972 riscv_cpu_update_named_features(cpu); 973 riscv_cpu_validate_profiles(cpu); 974 975 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 976 /* 977 * Enhanced PMP should only be available 978 * on harts with PMP support 979 */ 980 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 981 return; 982 } 983 984 riscv_cpu_validate_set_extensions(cpu, &local_err); 985 if (local_err != NULL) { 986 error_propagate(errp, local_err); 987 return; 988 } 989 #ifndef CONFIG_USER_ONLY 990 if (cpu->cfg.pmu_mask) { 991 riscv_pmu_init(cpu, &local_err); 992 if (local_err != NULL) { 993 error_propagate(errp, local_err); 994 return; 995 } 996 997 if (cpu->cfg.ext_sscofpmf) { 998 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 999 riscv_pmu_timer_cb, cpu); 1000 } 1001 } 1002 #endif 1003 } 1004 1005 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) 1006 { 1007 GPtrArray *dynamic_decoders; 1008 dynamic_decoders = g_ptr_array_sized_new(decoder_table_size); 1009 for (size_t i = 0; i < decoder_table_size; ++i) { 1010 if (decoder_table[i].guard_func && 1011 decoder_table[i].guard_func(&cpu->cfg)) { 1012 g_ptr_array_add(dynamic_decoders, 1013 (gpointer)decoder_table[i].riscv_cpu_decode_fn); 1014 } 1015 } 1016 1017 cpu->decoders = dynamic_decoders; 1018 } 1019 1020 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 1021 { 1022 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 1023 } 1024 1025 static bool riscv_cpu_is_generic(Object *cpu_obj) 1026 { 1027 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 1028 } 1029 1030 /* 1031 * We'll get here via the following path: 1032 * 1033 * riscv_cpu_realize() 1034 * -> cpu_exec_realizefn() 1035 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 1036 */ 1037 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 1038 { 1039 RISCVCPU *cpu = RISCV_CPU(cs); 1040 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 1041 1042 if (!riscv_cpu_tcg_compatible(cpu)) { 1043 g_autofree char *name = riscv_cpu_get_name(cpu); 1044 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 1045 name); 1046 return false; 1047 } 1048 1049 if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) { 1050 /* Missing 128-bit aligned atomics */ 1051 error_setg(errp, 1052 "128-bit RISC-V currently does not work with Multi " 1053 "Threaded TCG. Please use: -accel tcg,thread=single"); 1054 return false; 1055 } 1056 1057 #ifndef CONFIG_USER_ONLY 1058 CPURISCVState *env = &cpu->env; 1059 1060 tcg_cflags_set(CPU(cs), CF_PCREL); 1061 1062 if (cpu->cfg.ext_sstc) { 1063 riscv_timer_init(cpu); 1064 } 1065 1066 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 1067 if (riscv_has_ext(env, RVH)) { 1068 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 1069 } 1070 #endif 1071 1072 return true; 1073 } 1074 1075 typedef struct RISCVCPUMisaExtConfig { 1076 target_ulong misa_bit; 1077 bool enabled; 1078 } RISCVCPUMisaExtConfig; 1079 1080 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1081 void *opaque, Error **errp) 1082 { 1083 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1084 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1085 RISCVCPU *cpu = RISCV_CPU(obj); 1086 CPURISCVState *env = &cpu->env; 1087 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1088 bool prev_val, value; 1089 1090 if (!visit_type_bool(v, name, &value, errp)) { 1091 return; 1092 } 1093 1094 cpu_misa_ext_add_user_opt(misa_bit, value); 1095 1096 prev_val = env->misa_ext & misa_bit; 1097 1098 if (value == prev_val) { 1099 return; 1100 } 1101 1102 if (value) { 1103 if (vendor_cpu) { 1104 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1105 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1106 cpuname); 1107 return; 1108 } 1109 1110 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 1111 /* 1112 * Note: the 'priv_spec' command line option, if present, 1113 * will take precedence over this priv_ver bump. 1114 */ 1115 env->priv_ver = PRIV_VERSION_1_12_0; 1116 } 1117 } 1118 1119 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1120 } 1121 1122 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1123 void *opaque, Error **errp) 1124 { 1125 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1126 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1127 RISCVCPU *cpu = RISCV_CPU(obj); 1128 CPURISCVState *env = &cpu->env; 1129 bool value; 1130 1131 value = env->misa_ext & misa_bit; 1132 1133 visit_type_bool(v, name, &value, errp); 1134 } 1135 1136 #define MISA_CFG(_bit, _enabled) \ 1137 {.misa_bit = _bit, .enabled = _enabled} 1138 1139 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1140 MISA_CFG(RVA, true), 1141 MISA_CFG(RVC, true), 1142 MISA_CFG(RVD, true), 1143 MISA_CFG(RVF, true), 1144 MISA_CFG(RVI, true), 1145 MISA_CFG(RVE, false), 1146 MISA_CFG(RVM, true), 1147 MISA_CFG(RVS, true), 1148 MISA_CFG(RVU, true), 1149 MISA_CFG(RVH, true), 1150 MISA_CFG(RVV, false), 1151 MISA_CFG(RVG, false), 1152 MISA_CFG(RVB, false), 1153 }; 1154 1155 /* 1156 * We do not support user choice tracking for MISA 1157 * extensions yet because, so far, we do not silently 1158 * change MISA bits during realize() (RVG enables MISA 1159 * bits but the user is warned about it). 1160 */ 1161 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1162 { 1163 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1164 int i; 1165 1166 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1167 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1168 int bit = misa_cfg->misa_bit; 1169 const char *name = riscv_get_misa_ext_name(bit); 1170 const char *desc = riscv_get_misa_ext_description(bit); 1171 1172 /* Check if KVM already created the property */ 1173 if (object_property_find(cpu_obj, name)) { 1174 continue; 1175 } 1176 1177 object_property_add(cpu_obj, name, "bool", 1178 cpu_get_misa_ext_cfg, 1179 cpu_set_misa_ext_cfg, 1180 NULL, (void *)misa_cfg); 1181 object_property_set_description(cpu_obj, name, desc); 1182 if (use_def_vals) { 1183 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1184 misa_cfg->enabled); 1185 } 1186 } 1187 } 1188 1189 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1190 void *opaque, Error **errp) 1191 { 1192 RISCVCPUProfile *profile = opaque; 1193 RISCVCPU *cpu = RISCV_CPU(obj); 1194 bool value; 1195 int i, ext_offset; 1196 1197 if (riscv_cpu_is_vendor(obj)) { 1198 error_setg(errp, "Profile %s is not available for vendor CPUs", 1199 profile->name); 1200 return; 1201 } 1202 1203 if (cpu->env.misa_mxl != MXL_RV64) { 1204 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1205 profile->name); 1206 return; 1207 } 1208 1209 if (!visit_type_bool(v, name, &value, errp)) { 1210 return; 1211 } 1212 1213 profile->user_set = true; 1214 profile->enabled = value; 1215 1216 if (profile->u_parent != NULL) { 1217 object_property_set_bool(obj, profile->u_parent->name, 1218 profile->enabled, NULL); 1219 } 1220 1221 if (profile->s_parent != NULL) { 1222 object_property_set_bool(obj, profile->s_parent->name, 1223 profile->enabled, NULL); 1224 } 1225 1226 if (profile->enabled) { 1227 cpu->env.priv_ver = profile->priv_spec; 1228 } 1229 1230 #ifndef CONFIG_USER_ONLY 1231 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1232 object_property_set_bool(obj, "mmu", true, NULL); 1233 const char *satp_prop = satp_mode_str(profile->satp_mode, 1234 riscv_cpu_is_32bit(cpu)); 1235 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1236 } 1237 #endif 1238 1239 for (i = 0; misa_bits[i] != 0; i++) { 1240 uint32_t bit = misa_bits[i]; 1241 1242 if (!(profile->misa_ext & bit)) { 1243 continue; 1244 } 1245 1246 if (bit == RVI && !profile->enabled) { 1247 /* 1248 * Disabling profiles will not disable the base 1249 * ISA RV64I. 1250 */ 1251 continue; 1252 } 1253 1254 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1255 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1256 } 1257 1258 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1259 ext_offset = profile->ext_offsets[i]; 1260 1261 if (profile->enabled) { 1262 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1263 riscv_cpu_enable_named_feat(cpu, ext_offset); 1264 } 1265 1266 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1267 } 1268 1269 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1270 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1271 } 1272 } 1273 1274 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1275 void *opaque, Error **errp) 1276 { 1277 RISCVCPUProfile *profile = opaque; 1278 bool value = profile->enabled; 1279 1280 visit_type_bool(v, name, &value, errp); 1281 } 1282 1283 static void riscv_cpu_add_profiles(Object *cpu_obj) 1284 { 1285 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1286 const RISCVCPUProfile *profile = riscv_profiles[i]; 1287 1288 object_property_add(cpu_obj, profile->name, "bool", 1289 cpu_get_profile, cpu_set_profile, 1290 NULL, (void *)profile); 1291 1292 /* 1293 * CPUs might enable a profile right from the start. 1294 * Enable its mandatory extensions right away in this 1295 * case. 1296 */ 1297 if (profile->enabled) { 1298 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1299 } 1300 } 1301 } 1302 1303 static bool cpu_ext_is_deprecated(const char *ext_name) 1304 { 1305 return isupper(ext_name[0]); 1306 } 1307 1308 /* 1309 * String will be allocated in the heap. Caller is responsible 1310 * for freeing it. 1311 */ 1312 static char *cpu_ext_to_lower(const char *ext_name) 1313 { 1314 char *ret = g_malloc0(strlen(ext_name) + 1); 1315 1316 strcpy(ret, ext_name); 1317 ret[0] = tolower(ret[0]); 1318 1319 return ret; 1320 } 1321 1322 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1323 void *opaque, Error **errp) 1324 { 1325 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1326 RISCVCPU *cpu = RISCV_CPU(obj); 1327 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1328 bool prev_val, value; 1329 1330 if (!visit_type_bool(v, name, &value, errp)) { 1331 return; 1332 } 1333 1334 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1335 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1336 1337 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1338 multi_ext_cfg->name, lower); 1339 } 1340 1341 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1342 1343 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1344 1345 if (value == prev_val) { 1346 return; 1347 } 1348 1349 if (value && vendor_cpu) { 1350 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1351 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1352 cpuname); 1353 return; 1354 } 1355 1356 if (value) { 1357 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1358 } 1359 1360 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1361 } 1362 1363 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1364 void *opaque, Error **errp) 1365 { 1366 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1367 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1368 1369 visit_type_bool(v, name, &value, errp); 1370 } 1371 1372 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1373 const RISCVCPUMultiExtConfig *multi_cfg) 1374 { 1375 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1376 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1377 1378 object_property_add(cpu_obj, multi_cfg->name, "bool", 1379 cpu_get_multi_ext_cfg, 1380 cpu_set_multi_ext_cfg, 1381 NULL, (void *)multi_cfg); 1382 1383 if (!generic_cpu || deprecated_ext) { 1384 return; 1385 } 1386 1387 /* 1388 * Set def val directly instead of using 1389 * object_property_set_bool() to save the set() 1390 * callback hash for user inputs. 1391 */ 1392 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1393 multi_cfg->enabled); 1394 } 1395 1396 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1397 const RISCVCPUMultiExtConfig *array) 1398 { 1399 const RISCVCPUMultiExtConfig *prop; 1400 1401 g_assert(array); 1402 1403 for (prop = array; prop && prop->name; prop++) { 1404 cpu_add_multi_ext_prop(obj, prop); 1405 } 1406 } 1407 1408 /* 1409 * Add CPU properties with user-facing flags. 1410 * 1411 * This will overwrite existing env->misa_ext values with the 1412 * defaults set via riscv_cpu_add_misa_properties(). 1413 */ 1414 static void riscv_cpu_add_user_properties(Object *obj) 1415 { 1416 #ifndef CONFIG_USER_ONLY 1417 riscv_add_satp_mode_properties(obj); 1418 #endif 1419 1420 riscv_cpu_add_misa_properties(obj); 1421 1422 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1423 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1424 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1425 1426 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1427 1428 riscv_cpu_add_profiles(obj); 1429 } 1430 1431 /* 1432 * The 'max' type CPU will have all possible ratified 1433 * non-vendor extensions enabled. 1434 */ 1435 static void riscv_init_max_cpu_extensions(Object *obj) 1436 { 1437 RISCVCPU *cpu = RISCV_CPU(obj); 1438 CPURISCVState *env = &cpu->env; 1439 const RISCVCPUMultiExtConfig *prop; 1440 1441 /* Enable RVG and RVV that are disabled by default */ 1442 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); 1443 1444 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1445 isa_ext_update_enabled(cpu, prop->offset, true); 1446 } 1447 1448 /* 1449 * Some extensions can't be added without backward compatibilty concerns. 1450 * Disable those, the user can still opt in to them on the command line. 1451 */ 1452 cpu->cfg.ext_svade = false; 1453 1454 /* set vector version */ 1455 env->vext_ver = VEXT_VERSION_1_00_0; 1456 1457 /* Zfinx is not compatible with F. Disable it */ 1458 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1459 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1460 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1461 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1462 1463 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1464 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1465 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1466 1467 if (env->misa_mxl != MXL_RV32) { 1468 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1469 } 1470 1471 /* 1472 * TODO: ext_smrnmi requires OpenSBI changes that our current 1473 * image does not have. Disable it for now. 1474 */ 1475 if (cpu->cfg.ext_smrnmi) { 1476 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); 1477 } 1478 1479 /* 1480 * TODO: ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup 1481 * to avoid generating a double trap. OpenSBI does not currently support it, 1482 * disable it for now. 1483 */ 1484 if (cpu->cfg.ext_smdbltrp) { 1485 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); 1486 } 1487 } 1488 1489 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1490 { 1491 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1492 } 1493 1494 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1495 { 1496 RISCVCPU *cpu = RISCV_CPU(cs); 1497 Object *obj = OBJECT(cpu); 1498 1499 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1500 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1501 1502 if (!misa_ext_implied_rules) { 1503 misa_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1504 } 1505 1506 if (!multi_ext_implied_rules) { 1507 multi_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1508 } 1509 1510 riscv_cpu_add_user_properties(obj); 1511 1512 if (riscv_cpu_has_max_extensions(obj)) { 1513 riscv_init_max_cpu_extensions(obj); 1514 } 1515 } 1516 1517 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1518 { 1519 /* 1520 * All cpus use the same set of operations. 1521 */ 1522 cc->tcg_ops = &riscv_tcg_ops; 1523 } 1524 1525 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1526 { 1527 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1528 } 1529 1530 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1531 { 1532 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1533 1534 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1535 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1536 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1537 } 1538 1539 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1540 .name = ACCEL_CPU_NAME("tcg"), 1541 1542 .parent = TYPE_ACCEL_CPU, 1543 .class_init = riscv_tcg_cpu_accel_class_init, 1544 .abstract = true, 1545 }; 1546 1547 static void riscv_tcg_cpu_accel_register_types(void) 1548 { 1549 type_register_static(&riscv_tcg_cpu_accel_type_info); 1550 } 1551 type_init(riscv_tcg_cpu_accel_register_types); 1552