1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "tcg-cpu.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "time_helper.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "qemu/accel.h" 29 #include "qemu/error-report.h" 30 #include "qemu/log.h" 31 #include "hw/core/accel-cpu.h" 32 #include "hw/core/tcg-cpu-ops.h" 33 #include "tcg/tcg.h" 34 35 /* Hash that stores user set extensions */ 36 static GHashTable *multi_ext_user_opts; 37 static GHashTable *misa_ext_user_opts; 38 39 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 40 { 41 return g_hash_table_contains(multi_ext_user_opts, 42 GUINT_TO_POINTER(ext_offset)); 43 } 44 45 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 46 { 47 return g_hash_table_contains(misa_ext_user_opts, 48 GUINT_TO_POINTER(misa_bit)); 49 } 50 51 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 52 { 53 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 54 (gpointer)value); 55 } 56 57 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 58 { 59 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 60 (gpointer)value); 61 } 62 63 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 64 bool enabled) 65 { 66 CPURISCVState *env = &cpu->env; 67 68 if (enabled) { 69 env->misa_ext |= bit; 70 env->misa_ext_mask |= bit; 71 } else { 72 env->misa_ext &= ~bit; 73 env->misa_ext_mask &= ~bit; 74 } 75 } 76 77 static const char *cpu_priv_ver_to_str(int priv_ver) 78 { 79 switch (priv_ver) { 80 case PRIV_VERSION_1_10_0: 81 return "v1.10.0"; 82 case PRIV_VERSION_1_11_0: 83 return "v1.11.0"; 84 case PRIV_VERSION_1_12_0: 85 return "v1.12.0"; 86 } 87 88 g_assert_not_reached(); 89 } 90 91 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 92 const TranslationBlock *tb) 93 { 94 if (!(tb_cflags(tb) & CF_PCREL)) { 95 RISCVCPU *cpu = RISCV_CPU(cs); 96 CPURISCVState *env = &cpu->env; 97 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 98 99 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 100 101 if (xl == MXL_RV32) { 102 env->pc = (int32_t) tb->pc; 103 } else { 104 env->pc = tb->pc; 105 } 106 } 107 } 108 109 static void riscv_restore_state_to_opc(CPUState *cs, 110 const TranslationBlock *tb, 111 const uint64_t *data) 112 { 113 RISCVCPU *cpu = RISCV_CPU(cs); 114 CPURISCVState *env = &cpu->env; 115 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 116 target_ulong pc; 117 118 if (tb_cflags(tb) & CF_PCREL) { 119 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 120 } else { 121 pc = data[0]; 122 } 123 124 if (xl == MXL_RV32) { 125 env->pc = (int32_t)pc; 126 } else { 127 env->pc = pc; 128 } 129 env->bins = data[1]; 130 } 131 132 static const TCGCPUOps riscv_tcg_ops = { 133 .initialize = riscv_translate_init, 134 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 135 .restore_state_to_opc = riscv_restore_state_to_opc, 136 137 #ifndef CONFIG_USER_ONLY 138 .tlb_fill = riscv_cpu_tlb_fill, 139 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 140 .do_interrupt = riscv_cpu_do_interrupt, 141 .do_transaction_failed = riscv_cpu_do_transaction_failed, 142 .do_unaligned_access = riscv_cpu_do_unaligned_access, 143 .debug_excp_handler = riscv_cpu_debug_excp_handler, 144 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 145 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 146 #endif /* !CONFIG_USER_ONLY */ 147 }; 148 149 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 150 { 151 const RISCVIsaExtData *edata; 152 153 for (edata = isa_edata_arr; edata && edata->name; edata++) { 154 if (edata->ext_enable_offset != ext_offset) { 155 continue; 156 } 157 158 return edata->min_version; 159 } 160 161 g_assert_not_reached(); 162 } 163 164 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 165 { 166 const RISCVCPUMultiExtConfig *feat; 167 const RISCVIsaExtData *edata; 168 169 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 170 if (edata->ext_enable_offset == ext_offset) { 171 return edata->name; 172 } 173 } 174 175 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 176 if (feat->offset == ext_offset) { 177 return feat->name; 178 } 179 } 180 181 g_assert_not_reached(); 182 } 183 184 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 185 { 186 const RISCVCPUMultiExtConfig *feat; 187 188 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 189 if (feat->offset == ext_offset) { 190 return true; 191 } 192 } 193 194 return false; 195 } 196 197 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 198 { 199 switch (feat_offset) { 200 case CPU_CFG_OFFSET(zic64b): 201 cpu->cfg.cbom_blocksize = 64; 202 cpu->cfg.cbop_blocksize = 64; 203 cpu->cfg.cboz_blocksize = 64; 204 break; 205 case CPU_CFG_OFFSET(svade): 206 cpu->cfg.ext_svadu = false; 207 break; 208 default: 209 g_assert_not_reached(); 210 } 211 } 212 213 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 214 uint32_t ext_offset) 215 { 216 int ext_priv_ver; 217 218 if (env->priv_ver == PRIV_VERSION_LATEST) { 219 return; 220 } 221 222 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 223 return; 224 } 225 226 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 227 228 if (env->priv_ver < ext_priv_ver) { 229 /* 230 * Note: the 'priv_spec' command line option, if present, 231 * will take precedence over this priv_ver bump. 232 */ 233 env->priv_ver = ext_priv_ver; 234 } 235 } 236 237 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 238 bool value) 239 { 240 CPURISCVState *env = &cpu->env; 241 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 242 int min_version; 243 244 if (prev_val == value) { 245 return; 246 } 247 248 if (cpu_cfg_ext_is_user_set(ext_offset)) { 249 return; 250 } 251 252 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 253 /* Do not enable it if priv_ver is older than min_version */ 254 min_version = cpu_cfg_ext_get_min_version(ext_offset); 255 if (env->priv_ver < min_version) { 256 return; 257 } 258 } 259 260 isa_ext_update_enabled(cpu, ext_offset, value); 261 } 262 263 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 264 { 265 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 266 error_setg(errp, "H extension requires priv spec 1.12.0"); 267 return; 268 } 269 } 270 271 static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) 272 { 273 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 274 CPUClass *cc = CPU_CLASS(mcc); 275 CPURISCVState *env = &cpu->env; 276 277 /* Validate that MISA_MXL is set properly. */ 278 switch (env->misa_mxl_max) { 279 #ifdef TARGET_RISCV64 280 case MXL_RV64: 281 case MXL_RV128: 282 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 283 break; 284 #endif 285 case MXL_RV32: 286 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 287 break; 288 default: 289 g_assert_not_reached(); 290 } 291 292 if (env->misa_mxl_max != env->misa_mxl) { 293 error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); 294 return; 295 } 296 } 297 298 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 299 Error **errp) 300 { 301 if (!is_power_of_2(cfg->vlen)) { 302 error_setg(errp, "Vector extension VLEN must be power of 2"); 303 return; 304 } 305 306 if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { 307 error_setg(errp, 308 "Vector extension implementation only supports VLEN " 309 "in the range [128, %d]", RV_VLEN_MAX); 310 return; 311 } 312 313 if (!is_power_of_2(cfg->elen)) { 314 error_setg(errp, "Vector extension ELEN must be power of 2"); 315 return; 316 } 317 318 if (cfg->elen > 64 || cfg->elen < 8) { 319 error_setg(errp, 320 "Vector extension implementation only supports ELEN " 321 "in the range [8, 64]"); 322 return; 323 } 324 } 325 326 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 327 { 328 CPURISCVState *env = &cpu->env; 329 const RISCVIsaExtData *edata; 330 331 /* Force disable extensions if priv spec version does not match */ 332 for (edata = isa_edata_arr; edata && edata->name; edata++) { 333 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 334 (env->priv_ver < edata->min_version)) { 335 /* 336 * These two extensions are always enabled as they were supported 337 * by QEMU before they were added as extensions in the ISA. 338 */ 339 if (!strcmp(edata->name, "zicntr") || 340 !strcmp(edata->name, "zihpm")) { 341 continue; 342 } 343 344 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 345 #ifndef CONFIG_USER_ONLY 346 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 347 " because privilege spec version does not match", 348 edata->name, env->mhartid); 349 #else 350 warn_report("disabling %s extension because " 351 "privilege spec version does not match", 352 edata->name); 353 #endif 354 } 355 } 356 } 357 358 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 359 { 360 cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 && 361 cpu->cfg.cbop_blocksize == 64 && 362 cpu->cfg.cboz_blocksize == 64; 363 364 cpu->cfg.svade = !cpu->cfg.ext_svadu; 365 } 366 367 static void riscv_cpu_validate_g(RISCVCPU *cpu) 368 { 369 const char *warn_msg = "RVG mandates disabled extension %s"; 370 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 371 bool send_warn = cpu_misa_ext_is_user_set(RVG); 372 373 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 374 uint32_t bit = g_misa_bits[i]; 375 376 if (riscv_has_ext(&cpu->env, bit)) { 377 continue; 378 } 379 380 if (!cpu_misa_ext_is_user_set(bit)) { 381 riscv_cpu_write_misa_bit(cpu, bit, true); 382 continue; 383 } 384 385 if (send_warn) { 386 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 387 } 388 } 389 390 if (!cpu->cfg.ext_zicsr) { 391 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 392 cpu->cfg.ext_zicsr = true; 393 } else if (send_warn) { 394 warn_report(warn_msg, "zicsr"); 395 } 396 } 397 398 if (!cpu->cfg.ext_zifencei) { 399 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 400 cpu->cfg.ext_zifencei = true; 401 } else if (send_warn) { 402 warn_report(warn_msg, "zifencei"); 403 } 404 } 405 } 406 407 static void riscv_cpu_validate_b(RISCVCPU *cpu) 408 { 409 const char *warn_msg = "RVB mandates disabled extension %s"; 410 411 if (!cpu->cfg.ext_zba) { 412 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 413 cpu->cfg.ext_zba = true; 414 } else { 415 warn_report(warn_msg, "zba"); 416 } 417 } 418 419 if (!cpu->cfg.ext_zbb) { 420 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 421 cpu->cfg.ext_zbb = true; 422 } else { 423 warn_report(warn_msg, "zbb"); 424 } 425 } 426 427 if (!cpu->cfg.ext_zbs) { 428 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 429 cpu->cfg.ext_zbs = true; 430 } else { 431 warn_report(warn_msg, "zbs"); 432 } 433 } 434 } 435 436 /* 437 * Check consistency between chosen extensions while setting 438 * cpu->cfg accordingly. 439 */ 440 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 441 { 442 CPURISCVState *env = &cpu->env; 443 Error *local_err = NULL; 444 445 if (riscv_has_ext(env, RVG)) { 446 riscv_cpu_validate_g(cpu); 447 } 448 449 if (riscv_has_ext(env, RVB)) { 450 riscv_cpu_validate_b(cpu); 451 } 452 453 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 454 error_setg(errp, 455 "I and E extensions are incompatible"); 456 return; 457 } 458 459 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 460 error_setg(errp, 461 "Either I or E extension must be set"); 462 return; 463 } 464 465 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 466 error_setg(errp, 467 "Setting S extension without U extension is illegal"); 468 return; 469 } 470 471 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 472 error_setg(errp, 473 "H depends on an I base integer ISA with 32 x registers"); 474 return; 475 } 476 477 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 478 error_setg(errp, "H extension implicitly requires S-mode"); 479 return; 480 } 481 482 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 483 error_setg(errp, "F extension requires Zicsr"); 484 return; 485 } 486 487 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 488 error_setg(errp, "Zacas extension requires A extension"); 489 return; 490 } 491 492 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 493 error_setg(errp, "Zawrs extension requires A extension"); 494 return; 495 } 496 497 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 498 error_setg(errp, "Zfa extension requires F extension"); 499 return; 500 } 501 502 if (cpu->cfg.ext_zfh) { 503 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); 504 } 505 506 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 507 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 508 return; 509 } 510 511 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 512 error_setg(errp, "Zfbfmin extension depends on F extension"); 513 return; 514 } 515 516 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 517 error_setg(errp, "D extension requires F extension"); 518 return; 519 } 520 521 if (riscv_has_ext(env, RVV)) { 522 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 523 if (local_err != NULL) { 524 error_propagate(errp, local_err); 525 return; 526 } 527 528 /* The V vector extension depends on the Zve64d extension */ 529 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); 530 } 531 532 /* The Zve64d extension depends on the Zve64f extension */ 533 if (cpu->cfg.ext_zve64d) { 534 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); 535 } 536 537 /* The Zve64f extension depends on the Zve32f extension */ 538 if (cpu->cfg.ext_zve64f) { 539 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); 540 } 541 542 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 543 error_setg(errp, "Zve64d/V extensions require D extension"); 544 return; 545 } 546 547 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 548 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 549 return; 550 } 551 552 if (cpu->cfg.ext_zvfh) { 553 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); 554 } 555 556 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 557 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 558 return; 559 } 560 561 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 562 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 563 return; 564 } 565 566 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { 567 error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"); 568 return; 569 } 570 571 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 572 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 573 return; 574 } 575 576 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 577 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 578 return; 579 } 580 581 /* Set the ISA extensions, checks should have happened above */ 582 if (cpu->cfg.ext_zhinx) { 583 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 584 } 585 586 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 587 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 588 return; 589 } 590 591 if (cpu->cfg.ext_zfinx) { 592 if (!cpu->cfg.ext_zicsr) { 593 error_setg(errp, "Zfinx extension requires Zicsr"); 594 return; 595 } 596 if (riscv_has_ext(env, RVF)) { 597 error_setg(errp, 598 "Zfinx cannot be supported together with F extension"); 599 return; 600 } 601 } 602 603 if (cpu->cfg.ext_zce) { 604 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 605 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 606 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 607 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 608 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 609 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 610 } 611 } 612 613 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ 614 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 615 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 616 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 617 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 618 } 619 if (riscv_has_ext(env, RVD)) { 620 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 621 } 622 } 623 624 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 625 error_setg(errp, "Zcf extension is only relevant to RV32"); 626 return; 627 } 628 629 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 630 error_setg(errp, "Zcf extension requires F extension"); 631 return; 632 } 633 634 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 635 error_setg(errp, "Zcd extension requires D extension"); 636 return; 637 } 638 639 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 640 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 641 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 642 "extension"); 643 return; 644 } 645 646 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 647 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 648 "Zcd extension"); 649 return; 650 } 651 652 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 653 error_setg(errp, "Zcmt extension requires Zicsr extension"); 654 return; 655 } 656 657 /* 658 * Shorthand vector crypto extensions 659 */ 660 if (cpu->cfg.ext_zvknc) { 661 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); 662 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 663 } 664 665 if (cpu->cfg.ext_zvkng) { 666 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); 667 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); 668 } 669 670 if (cpu->cfg.ext_zvkn) { 671 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true); 672 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true); 673 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); 674 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); 675 } 676 677 if (cpu->cfg.ext_zvksc) { 678 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); 679 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 680 } 681 682 if (cpu->cfg.ext_zvksg) { 683 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); 684 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); 685 } 686 687 if (cpu->cfg.ext_zvks) { 688 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true); 689 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true); 690 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); 691 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); 692 } 693 694 if (cpu->cfg.ext_zvkt) { 695 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); 696 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); 697 } 698 699 /* 700 * In principle Zve*x would also suffice here, were they supported 701 * in qemu 702 */ 703 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 704 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 705 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { 706 error_setg(errp, 707 "Vector crypto extensions require V or Zve* extensions"); 708 return; 709 } 710 711 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) { 712 error_setg( 713 errp, 714 "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions"); 715 return; 716 } 717 718 if (cpu->cfg.ext_zk) { 719 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); 720 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); 721 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); 722 } 723 724 if (cpu->cfg.ext_zkn) { 725 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 726 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 727 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 728 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); 729 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); 730 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); 731 } 732 733 if (cpu->cfg.ext_zks) { 734 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); 735 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); 736 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); 737 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); 738 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); 739 } 740 741 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 742 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 743 error_setg(errp, "zicntr requires zicsr"); 744 return; 745 } 746 cpu->cfg.ext_zicntr = false; 747 } 748 749 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 750 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 751 error_setg(errp, "zihpm requires zicsr"); 752 return; 753 } 754 cpu->cfg.ext_zihpm = false; 755 } 756 757 if (!cpu->cfg.ext_zihpm) { 758 cpu->cfg.pmu_mask = 0; 759 cpu->pmu_avail_ctrs = 0; 760 } 761 762 /* 763 * Disable isa extensions based on priv spec after we 764 * validated and set everything we need. 765 */ 766 riscv_cpu_disable_priv_spec_isa_exts(cpu); 767 } 768 769 #ifndef CONFIG_USER_ONLY 770 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 771 RISCVCPUProfile *profile, 772 bool send_warn) 773 { 774 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 775 776 if (profile->satp_mode > satp_max) { 777 if (send_warn) { 778 bool is_32bit = riscv_cpu_is_32bit(cpu); 779 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 780 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 781 782 warn_report("Profile %s requires satp mode %s, " 783 "but satp mode %s was set", profile->name, 784 req_satp, cur_satp); 785 } 786 787 return false; 788 } 789 790 return true; 791 } 792 #endif 793 794 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 795 RISCVCPUProfile *profile) 796 { 797 CPURISCVState *env = &cpu->env; 798 const char *warn_msg = "Profile %s mandates disabled extension %s"; 799 bool send_warn = profile->user_set && profile->enabled; 800 bool parent_enabled, profile_impl = true; 801 int i; 802 803 #ifndef CONFIG_USER_ONLY 804 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 805 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 806 send_warn); 807 } 808 #endif 809 810 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 811 profile->priv_spec != env->priv_ver) { 812 profile_impl = false; 813 814 if (send_warn) { 815 warn_report("Profile %s requires priv spec %s, " 816 "but priv ver %s was set", profile->name, 817 cpu_priv_ver_to_str(profile->priv_spec), 818 cpu_priv_ver_to_str(env->priv_ver)); 819 } 820 } 821 822 for (i = 0; misa_bits[i] != 0; i++) { 823 uint32_t bit = misa_bits[i]; 824 825 if (!(profile->misa_ext & bit)) { 826 continue; 827 } 828 829 if (!riscv_has_ext(&cpu->env, bit)) { 830 profile_impl = false; 831 832 if (send_warn) { 833 warn_report(warn_msg, profile->name, 834 riscv_get_misa_ext_name(bit)); 835 } 836 } 837 } 838 839 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 840 int ext_offset = profile->ext_offsets[i]; 841 842 if (!isa_ext_is_enabled(cpu, ext_offset)) { 843 profile_impl = false; 844 845 if (send_warn) { 846 warn_report(warn_msg, profile->name, 847 cpu_cfg_ext_get_name(ext_offset)); 848 } 849 } 850 } 851 852 profile->enabled = profile_impl; 853 854 if (profile->parent != NULL) { 855 parent_enabled = object_property_get_bool(OBJECT(cpu), 856 profile->parent->name, 857 NULL); 858 profile->enabled = profile->enabled && parent_enabled; 859 } 860 } 861 862 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 863 { 864 for (int i = 0; riscv_profiles[i] != NULL; i++) { 865 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 866 } 867 } 868 869 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 870 { 871 CPURISCVState *env = &cpu->env; 872 Error *local_err = NULL; 873 874 riscv_cpu_validate_misa_priv(env, &local_err); 875 if (local_err != NULL) { 876 error_propagate(errp, local_err); 877 return; 878 } 879 880 riscv_cpu_update_named_features(cpu); 881 riscv_cpu_validate_profiles(cpu); 882 883 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 884 /* 885 * Enhanced PMP should only be available 886 * on harts with PMP support 887 */ 888 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 889 return; 890 } 891 892 riscv_cpu_validate_set_extensions(cpu, &local_err); 893 if (local_err != NULL) { 894 error_propagate(errp, local_err); 895 return; 896 } 897 } 898 899 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 900 { 901 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 902 } 903 904 static bool riscv_cpu_is_generic(Object *cpu_obj) 905 { 906 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 907 } 908 909 /* 910 * We'll get here via the following path: 911 * 912 * riscv_cpu_realize() 913 * -> cpu_exec_realizefn() 914 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 915 */ 916 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 917 { 918 RISCVCPU *cpu = RISCV_CPU(cs); 919 Error *local_err = NULL; 920 921 if (!riscv_cpu_tcg_compatible(cpu)) { 922 g_autofree char *name = riscv_cpu_get_name(cpu); 923 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 924 name); 925 return false; 926 } 927 928 riscv_cpu_validate_misa_mxl(cpu, &local_err); 929 if (local_err != NULL) { 930 error_propagate(errp, local_err); 931 return false; 932 } 933 934 #ifndef CONFIG_USER_ONLY 935 CPURISCVState *env = &cpu->env; 936 937 CPU(cs)->tcg_cflags |= CF_PCREL; 938 939 if (cpu->cfg.ext_sstc) { 940 riscv_timer_init(cpu); 941 } 942 943 if (cpu->cfg.pmu_mask) { 944 riscv_pmu_init(cpu, &local_err); 945 if (local_err != NULL) { 946 error_propagate(errp, local_err); 947 return false; 948 } 949 950 if (cpu->cfg.ext_sscofpmf) { 951 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 952 riscv_pmu_timer_cb, cpu); 953 } 954 } 955 956 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 957 if (riscv_has_ext(env, RVH)) { 958 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 959 } 960 #endif 961 962 return true; 963 } 964 965 typedef struct RISCVCPUMisaExtConfig { 966 target_ulong misa_bit; 967 bool enabled; 968 } RISCVCPUMisaExtConfig; 969 970 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 971 void *opaque, Error **errp) 972 { 973 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 974 target_ulong misa_bit = misa_ext_cfg->misa_bit; 975 RISCVCPU *cpu = RISCV_CPU(obj); 976 CPURISCVState *env = &cpu->env; 977 bool vendor_cpu = riscv_cpu_is_vendor(obj); 978 bool prev_val, value; 979 980 if (!visit_type_bool(v, name, &value, errp)) { 981 return; 982 } 983 984 cpu_misa_ext_add_user_opt(misa_bit, value); 985 986 prev_val = env->misa_ext & misa_bit; 987 988 if (value == prev_val) { 989 return; 990 } 991 992 if (value) { 993 if (vendor_cpu) { 994 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 995 error_setg(errp, "'%s' CPU does not allow enabling extensions", 996 cpuname); 997 return; 998 } 999 1000 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 1001 /* 1002 * Note: the 'priv_spec' command line option, if present, 1003 * will take precedence over this priv_ver bump. 1004 */ 1005 env->priv_ver = PRIV_VERSION_1_12_0; 1006 } 1007 } 1008 1009 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1010 } 1011 1012 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1013 void *opaque, Error **errp) 1014 { 1015 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1016 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1017 RISCVCPU *cpu = RISCV_CPU(obj); 1018 CPURISCVState *env = &cpu->env; 1019 bool value; 1020 1021 value = env->misa_ext & misa_bit; 1022 1023 visit_type_bool(v, name, &value, errp); 1024 } 1025 1026 #define MISA_CFG(_bit, _enabled) \ 1027 {.misa_bit = _bit, .enabled = _enabled} 1028 1029 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1030 MISA_CFG(RVA, true), 1031 MISA_CFG(RVC, true), 1032 MISA_CFG(RVD, true), 1033 MISA_CFG(RVF, true), 1034 MISA_CFG(RVI, true), 1035 MISA_CFG(RVE, false), 1036 MISA_CFG(RVM, true), 1037 MISA_CFG(RVS, true), 1038 MISA_CFG(RVU, true), 1039 MISA_CFG(RVH, true), 1040 MISA_CFG(RVJ, false), 1041 MISA_CFG(RVV, false), 1042 MISA_CFG(RVG, false), 1043 MISA_CFG(RVB, false), 1044 }; 1045 1046 /* 1047 * We do not support user choice tracking for MISA 1048 * extensions yet because, so far, we do not silently 1049 * change MISA bits during realize() (RVG enables MISA 1050 * bits but the user is warned about it). 1051 */ 1052 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1053 { 1054 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1055 int i; 1056 1057 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1058 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1059 int bit = misa_cfg->misa_bit; 1060 const char *name = riscv_get_misa_ext_name(bit); 1061 const char *desc = riscv_get_misa_ext_description(bit); 1062 1063 /* Check if KVM already created the property */ 1064 if (object_property_find(cpu_obj, name)) { 1065 continue; 1066 } 1067 1068 object_property_add(cpu_obj, name, "bool", 1069 cpu_get_misa_ext_cfg, 1070 cpu_set_misa_ext_cfg, 1071 NULL, (void *)misa_cfg); 1072 object_property_set_description(cpu_obj, name, desc); 1073 if (use_def_vals) { 1074 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1075 misa_cfg->enabled); 1076 } 1077 } 1078 } 1079 1080 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1081 void *opaque, Error **errp) 1082 { 1083 RISCVCPUProfile *profile = opaque; 1084 RISCVCPU *cpu = RISCV_CPU(obj); 1085 bool value; 1086 int i, ext_offset; 1087 1088 if (riscv_cpu_is_vendor(obj)) { 1089 error_setg(errp, "Profile %s is not available for vendor CPUs", 1090 profile->name); 1091 return; 1092 } 1093 1094 if (cpu->env.misa_mxl != MXL_RV64) { 1095 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1096 profile->name); 1097 return; 1098 } 1099 1100 if (!visit_type_bool(v, name, &value, errp)) { 1101 return; 1102 } 1103 1104 profile->user_set = true; 1105 profile->enabled = value; 1106 1107 if (profile->parent != NULL) { 1108 object_property_set_bool(obj, profile->parent->name, 1109 profile->enabled, NULL); 1110 } 1111 1112 if (profile->enabled) { 1113 cpu->env.priv_ver = profile->priv_spec; 1114 } 1115 1116 #ifndef CONFIG_USER_ONLY 1117 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1118 const char *satp_prop = satp_mode_str(profile->satp_mode, 1119 riscv_cpu_is_32bit(cpu)); 1120 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1121 } 1122 #endif 1123 1124 for (i = 0; misa_bits[i] != 0; i++) { 1125 uint32_t bit = misa_bits[i]; 1126 1127 if (!(profile->misa_ext & bit)) { 1128 continue; 1129 } 1130 1131 if (bit == RVI && !profile->enabled) { 1132 /* 1133 * Disabling profiles will not disable the base 1134 * ISA RV64I. 1135 */ 1136 continue; 1137 } 1138 1139 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1140 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1141 } 1142 1143 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1144 ext_offset = profile->ext_offsets[i]; 1145 1146 if (profile->enabled) { 1147 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1148 riscv_cpu_enable_named_feat(cpu, ext_offset); 1149 } 1150 1151 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1152 } 1153 1154 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1155 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1156 } 1157 } 1158 1159 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1160 void *opaque, Error **errp) 1161 { 1162 RISCVCPUProfile *profile = opaque; 1163 bool value = profile->enabled; 1164 1165 visit_type_bool(v, name, &value, errp); 1166 } 1167 1168 static void riscv_cpu_add_profiles(Object *cpu_obj) 1169 { 1170 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1171 const RISCVCPUProfile *profile = riscv_profiles[i]; 1172 1173 object_property_add(cpu_obj, profile->name, "bool", 1174 cpu_get_profile, cpu_set_profile, 1175 NULL, (void *)profile); 1176 1177 /* 1178 * CPUs might enable a profile right from the start. 1179 * Enable its mandatory extensions right away in this 1180 * case. 1181 */ 1182 if (profile->enabled) { 1183 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1184 } 1185 } 1186 } 1187 1188 static bool cpu_ext_is_deprecated(const char *ext_name) 1189 { 1190 return isupper(ext_name[0]); 1191 } 1192 1193 /* 1194 * String will be allocated in the heap. Caller is responsible 1195 * for freeing it. 1196 */ 1197 static char *cpu_ext_to_lower(const char *ext_name) 1198 { 1199 char *ret = g_malloc0(strlen(ext_name) + 1); 1200 1201 strcpy(ret, ext_name); 1202 ret[0] = tolower(ret[0]); 1203 1204 return ret; 1205 } 1206 1207 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1208 void *opaque, Error **errp) 1209 { 1210 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1211 RISCVCPU *cpu = RISCV_CPU(obj); 1212 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1213 bool prev_val, value; 1214 1215 if (!visit_type_bool(v, name, &value, errp)) { 1216 return; 1217 } 1218 1219 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1220 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1221 1222 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1223 multi_ext_cfg->name, lower); 1224 } 1225 1226 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1227 1228 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1229 1230 if (value == prev_val) { 1231 return; 1232 } 1233 1234 if (value && vendor_cpu) { 1235 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1236 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1237 cpuname); 1238 return; 1239 } 1240 1241 if (value) { 1242 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1243 } 1244 1245 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1246 } 1247 1248 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1249 void *opaque, Error **errp) 1250 { 1251 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1252 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1253 1254 visit_type_bool(v, name, &value, errp); 1255 } 1256 1257 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1258 const RISCVCPUMultiExtConfig *multi_cfg) 1259 { 1260 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1261 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1262 1263 object_property_add(cpu_obj, multi_cfg->name, "bool", 1264 cpu_get_multi_ext_cfg, 1265 cpu_set_multi_ext_cfg, 1266 NULL, (void *)multi_cfg); 1267 1268 if (!generic_cpu || deprecated_ext) { 1269 return; 1270 } 1271 1272 /* 1273 * Set def val directly instead of using 1274 * object_property_set_bool() to save the set() 1275 * callback hash for user inputs. 1276 */ 1277 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1278 multi_cfg->enabled); 1279 } 1280 1281 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1282 const RISCVCPUMultiExtConfig *array) 1283 { 1284 const RISCVCPUMultiExtConfig *prop; 1285 1286 g_assert(array); 1287 1288 for (prop = array; prop && prop->name; prop++) { 1289 cpu_add_multi_ext_prop(obj, prop); 1290 } 1291 } 1292 1293 /* 1294 * Add CPU properties with user-facing flags. 1295 * 1296 * This will overwrite existing env->misa_ext values with the 1297 * defaults set via riscv_cpu_add_misa_properties(). 1298 */ 1299 static void riscv_cpu_add_user_properties(Object *obj) 1300 { 1301 #ifndef CONFIG_USER_ONLY 1302 riscv_add_satp_mode_properties(obj); 1303 #endif 1304 1305 riscv_cpu_add_misa_properties(obj); 1306 1307 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1308 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1309 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1310 1311 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1312 1313 riscv_cpu_add_profiles(obj); 1314 1315 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1316 qdev_property_add_static(DEVICE(obj), prop); 1317 } 1318 } 1319 1320 /* 1321 * The 'max' type CPU will have all possible ratified 1322 * non-vendor extensions enabled. 1323 */ 1324 static void riscv_init_max_cpu_extensions(Object *obj) 1325 { 1326 RISCVCPU *cpu = RISCV_CPU(obj); 1327 CPURISCVState *env = &cpu->env; 1328 const RISCVCPUMultiExtConfig *prop; 1329 1330 /* Enable RVG, RVJ and RVV that are disabled by default */ 1331 riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); 1332 1333 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1334 isa_ext_update_enabled(cpu, prop->offset, true); 1335 } 1336 1337 /* set vector version */ 1338 env->vext_ver = VEXT_VERSION_1_00_0; 1339 1340 /* Zfinx is not compatible with F. Disable it */ 1341 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1342 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1343 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1344 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1345 1346 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1347 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1348 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1349 1350 if (env->misa_mxl != MXL_RV32) { 1351 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1352 } 1353 } 1354 1355 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1356 { 1357 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1358 } 1359 1360 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1361 { 1362 RISCVCPU *cpu = RISCV_CPU(cs); 1363 Object *obj = OBJECT(cpu); 1364 1365 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1366 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1367 riscv_cpu_add_user_properties(obj); 1368 1369 if (riscv_cpu_has_max_extensions(obj)) { 1370 riscv_init_max_cpu_extensions(obj); 1371 } 1372 } 1373 1374 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1375 { 1376 /* 1377 * All cpus use the same set of operations. 1378 */ 1379 cc->tcg_ops = &riscv_tcg_ops; 1380 } 1381 1382 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1383 { 1384 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1385 } 1386 1387 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1388 { 1389 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1390 1391 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1392 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1393 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1394 } 1395 1396 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1397 .name = ACCEL_CPU_NAME("tcg"), 1398 1399 .parent = TYPE_ACCEL_CPU, 1400 .class_init = riscv_tcg_cpu_accel_class_init, 1401 .abstract = true, 1402 }; 1403 1404 static void riscv_tcg_cpu_accel_register_types(void) 1405 { 1406 type_register_static(&riscv_tcg_cpu_accel_type_info); 1407 } 1408 type_init(riscv_tcg_cpu_accel_register_types); 1409