1 /* 2 * riscv TCG cpu class initialization 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/exec-all.h" 22 #include "tcg-cpu.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "time_helper.h" 26 #include "qapi/error.h" 27 #include "qapi/visitor.h" 28 #include "qemu/accel.h" 29 #include "qemu/error-report.h" 30 #include "qemu/log.h" 31 #include "hw/core/accel-cpu.h" 32 #include "hw/core/tcg-cpu-ops.h" 33 #include "tcg/tcg.h" 34 #ifndef CONFIG_USER_ONLY 35 #include "hw/boards.h" 36 #endif 37 38 /* Hash that stores user set extensions */ 39 static GHashTable *multi_ext_user_opts; 40 static GHashTable *misa_ext_user_opts; 41 42 static GHashTable *multi_ext_implied_rules; 43 static GHashTable *misa_ext_implied_rules; 44 45 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 46 { 47 return g_hash_table_contains(multi_ext_user_opts, 48 GUINT_TO_POINTER(ext_offset)); 49 } 50 51 static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) 52 { 53 return g_hash_table_contains(misa_ext_user_opts, 54 GUINT_TO_POINTER(misa_bit)); 55 } 56 57 static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) 58 { 59 g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), 60 (gpointer)value); 61 } 62 63 static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) 64 { 65 g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), 66 (gpointer)value); 67 } 68 69 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, 70 bool enabled) 71 { 72 CPURISCVState *env = &cpu->env; 73 74 if (enabled) { 75 env->misa_ext |= bit; 76 env->misa_ext_mask |= bit; 77 } else { 78 env->misa_ext &= ~bit; 79 env->misa_ext_mask &= ~bit; 80 } 81 } 82 83 static const char *cpu_priv_ver_to_str(int priv_ver) 84 { 85 const char *priv_spec_str = priv_spec_to_str(priv_ver); 86 87 g_assert(priv_spec_str); 88 89 return priv_spec_str; 90 } 91 92 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 93 const TranslationBlock *tb) 94 { 95 if (!(tb_cflags(tb) & CF_PCREL)) { 96 RISCVCPU *cpu = RISCV_CPU(cs); 97 CPURISCVState *env = &cpu->env; 98 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 99 100 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 101 102 if (xl == MXL_RV32) { 103 env->pc = (int32_t) tb->pc; 104 } else { 105 env->pc = tb->pc; 106 } 107 } 108 } 109 110 static void riscv_restore_state_to_opc(CPUState *cs, 111 const TranslationBlock *tb, 112 const uint64_t *data) 113 { 114 RISCVCPU *cpu = RISCV_CPU(cs); 115 CPURISCVState *env = &cpu->env; 116 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 117 target_ulong pc; 118 119 if (tb_cflags(tb) & CF_PCREL) { 120 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 121 } else { 122 pc = data[0]; 123 } 124 125 if (xl == MXL_RV32) { 126 env->pc = (int32_t)pc; 127 } else { 128 env->pc = pc; 129 } 130 env->bins = data[1]; 131 } 132 133 static const TCGCPUOps riscv_tcg_ops = { 134 .initialize = riscv_translate_init, 135 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 136 .restore_state_to_opc = riscv_restore_state_to_opc, 137 138 #ifndef CONFIG_USER_ONLY 139 .tlb_fill = riscv_cpu_tlb_fill, 140 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 141 .do_interrupt = riscv_cpu_do_interrupt, 142 .do_transaction_failed = riscv_cpu_do_transaction_failed, 143 .do_unaligned_access = riscv_cpu_do_unaligned_access, 144 .debug_excp_handler = riscv_cpu_debug_excp_handler, 145 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 146 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 147 #endif /* !CONFIG_USER_ONLY */ 148 }; 149 150 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 151 { 152 const RISCVIsaExtData *edata; 153 154 for (edata = isa_edata_arr; edata && edata->name; edata++) { 155 if (edata->ext_enable_offset != ext_offset) { 156 continue; 157 } 158 159 return edata->min_version; 160 } 161 162 g_assert_not_reached(); 163 } 164 165 static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) 166 { 167 const RISCVCPUMultiExtConfig *feat; 168 const RISCVIsaExtData *edata; 169 170 for (edata = isa_edata_arr; edata->name != NULL; edata++) { 171 if (edata->ext_enable_offset == ext_offset) { 172 return edata->name; 173 } 174 } 175 176 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 177 if (feat->offset == ext_offset) { 178 return feat->name; 179 } 180 } 181 182 g_assert_not_reached(); 183 } 184 185 static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) 186 { 187 const RISCVCPUMultiExtConfig *feat; 188 189 for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { 190 if (feat->offset == ext_offset) { 191 return true; 192 } 193 } 194 195 return false; 196 } 197 198 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) 199 { 200 /* 201 * All other named features are already enabled 202 * in riscv_tcg_cpu_instance_init(). 203 */ 204 if (feat_offset == CPU_CFG_OFFSET(ext_zic64b)) { 205 cpu->cfg.cbom_blocksize = 64; 206 cpu->cfg.cbop_blocksize = 64; 207 cpu->cfg.cboz_blocksize = 64; 208 } 209 } 210 211 static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, 212 uint32_t ext_offset) 213 { 214 int ext_priv_ver; 215 216 if (env->priv_ver == PRIV_VERSION_LATEST) { 217 return; 218 } 219 220 ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); 221 222 if (env->priv_ver < ext_priv_ver) { 223 /* 224 * Note: the 'priv_spec' command line option, if present, 225 * will take precedence over this priv_ver bump. 226 */ 227 env->priv_ver = ext_priv_ver; 228 } 229 } 230 231 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, 232 bool value) 233 { 234 CPURISCVState *env = &cpu->env; 235 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); 236 int min_version; 237 238 if (prev_val == value) { 239 return; 240 } 241 242 if (cpu_cfg_ext_is_user_set(ext_offset)) { 243 return; 244 } 245 246 if (value && env->priv_ver != PRIV_VERSION_LATEST) { 247 /* Do not enable it if priv_ver is older than min_version */ 248 min_version = cpu_cfg_ext_get_min_version(ext_offset); 249 if (env->priv_ver < min_version) { 250 return; 251 } 252 } 253 254 isa_ext_update_enabled(cpu, ext_offset, value); 255 } 256 257 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 258 { 259 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 260 error_setg(errp, "H extension requires priv spec 1.12.0"); 261 return; 262 } 263 } 264 265 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 266 Error **errp) 267 { 268 uint32_t vlen = cfg->vlenb << 3; 269 270 if (vlen > RV_VLEN_MAX || vlen < 128) { 271 error_setg(errp, 272 "Vector extension implementation only supports VLEN " 273 "in the range [128, %d]", RV_VLEN_MAX); 274 return; 275 } 276 277 if (cfg->elen > 64 || cfg->elen < 8) { 278 error_setg(errp, 279 "Vector extension implementation only supports ELEN " 280 "in the range [8, 64]"); 281 return; 282 } 283 } 284 285 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 286 { 287 CPURISCVState *env = &cpu->env; 288 const RISCVIsaExtData *edata; 289 290 /* Force disable extensions if priv spec version does not match */ 291 for (edata = isa_edata_arr; edata && edata->name; edata++) { 292 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && 293 (env->priv_ver < edata->min_version)) { 294 /* 295 * These two extensions are always enabled as they were supported 296 * by QEMU before they were added as extensions in the ISA. 297 */ 298 if (!strcmp(edata->name, "zicntr") || 299 !strcmp(edata->name, "zihpm")) { 300 continue; 301 } 302 303 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); 304 #ifndef CONFIG_USER_ONLY 305 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 306 " because privilege spec version does not match", 307 edata->name, env->mhartid); 308 #else 309 warn_report("disabling %s extension because " 310 "privilege spec version does not match", 311 edata->name); 312 #endif 313 } 314 } 315 } 316 317 static void riscv_cpu_update_named_features(RISCVCPU *cpu) 318 { 319 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { 320 cpu->cfg.has_priv_1_11 = true; 321 } 322 323 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { 324 cpu->cfg.has_priv_1_12 = true; 325 } 326 327 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { 328 cpu->cfg.has_priv_1_13 = true; 329 } 330 331 /* zic64b is 1.12 or later */ 332 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && 333 cpu->cfg.cbop_blocksize == 64 && 334 cpu->cfg.cboz_blocksize == 64 && 335 cpu->cfg.has_priv_1_12; 336 } 337 338 static void riscv_cpu_validate_g(RISCVCPU *cpu) 339 { 340 const char *warn_msg = "RVG mandates disabled extension %s"; 341 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; 342 bool send_warn = cpu_misa_ext_is_user_set(RVG); 343 344 for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) { 345 uint32_t bit = g_misa_bits[i]; 346 347 if (riscv_has_ext(&cpu->env, bit)) { 348 continue; 349 } 350 351 if (!cpu_misa_ext_is_user_set(bit)) { 352 riscv_cpu_write_misa_bit(cpu, bit, true); 353 continue; 354 } 355 356 if (send_warn) { 357 warn_report(warn_msg, riscv_get_misa_ext_name(bit)); 358 } 359 } 360 361 if (!cpu->cfg.ext_zicsr) { 362 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { 363 cpu->cfg.ext_zicsr = true; 364 } else if (send_warn) { 365 warn_report(warn_msg, "zicsr"); 366 } 367 } 368 369 if (!cpu->cfg.ext_zifencei) { 370 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { 371 cpu->cfg.ext_zifencei = true; 372 } else if (send_warn) { 373 warn_report(warn_msg, "zifencei"); 374 } 375 } 376 } 377 378 static void riscv_cpu_validate_b(RISCVCPU *cpu) 379 { 380 const char *warn_msg = "RVB mandates disabled extension %s"; 381 382 if (!cpu->cfg.ext_zba) { 383 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { 384 cpu->cfg.ext_zba = true; 385 } else { 386 warn_report(warn_msg, "zba"); 387 } 388 } 389 390 if (!cpu->cfg.ext_zbb) { 391 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { 392 cpu->cfg.ext_zbb = true; 393 } else { 394 warn_report(warn_msg, "zbb"); 395 } 396 } 397 398 if (!cpu->cfg.ext_zbs) { 399 if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { 400 cpu->cfg.ext_zbs = true; 401 } else { 402 warn_report(warn_msg, "zbs"); 403 } 404 } 405 } 406 407 /* 408 * Check consistency between chosen extensions while setting 409 * cpu->cfg accordingly. 410 */ 411 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 412 { 413 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 414 CPURISCVState *env = &cpu->env; 415 Error *local_err = NULL; 416 417 if (riscv_has_ext(env, RVG)) { 418 riscv_cpu_validate_g(cpu); 419 } 420 421 if (riscv_has_ext(env, RVB)) { 422 riscv_cpu_validate_b(cpu); 423 } 424 425 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 426 error_setg(errp, 427 "I and E extensions are incompatible"); 428 return; 429 } 430 431 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 432 error_setg(errp, 433 "Either I or E extension must be set"); 434 return; 435 } 436 437 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 438 error_setg(errp, 439 "Setting S extension without U extension is illegal"); 440 return; 441 } 442 443 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 444 error_setg(errp, 445 "H depends on an I base integer ISA with 32 x registers"); 446 return; 447 } 448 449 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 450 error_setg(errp, "H extension implicitly requires S-mode"); 451 return; 452 } 453 454 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { 455 error_setg(errp, "F extension requires Zicsr"); 456 return; 457 } 458 459 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { 460 error_setg(errp, "Zacas extension requires A extension"); 461 return; 462 } 463 464 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 465 error_setg(errp, "Zawrs extension requires A extension"); 466 return; 467 } 468 469 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 470 error_setg(errp, "Zfa extension requires F extension"); 471 return; 472 } 473 474 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 475 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 476 return; 477 } 478 479 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 480 error_setg(errp, "Zfbfmin extension depends on F extension"); 481 return; 482 } 483 484 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 485 error_setg(errp, "D extension requires F extension"); 486 return; 487 } 488 489 if (riscv_has_ext(env, RVV)) { 490 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 491 if (local_err != NULL) { 492 error_propagate(errp, local_err); 493 return; 494 } 495 } 496 497 /* The Zve64d extension depends on the Zve64f extension */ 498 if (cpu->cfg.ext_zve64d) { 499 if (!riscv_has_ext(env, RVD)) { 500 error_setg(errp, "Zve64d/V extensions require D extension"); 501 return; 502 } 503 } 504 505 /* The Zve32f extension depends on the Zve32x extension */ 506 if (cpu->cfg.ext_zve32f) { 507 if (!riscv_has_ext(env, RVF)) { 508 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 509 return; 510 } 511 } 512 513 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 514 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 515 return; 516 } 517 518 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 519 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 520 return; 521 } 522 523 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 524 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 525 return; 526 } 527 528 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 529 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 530 return; 531 } 532 533 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 534 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 535 return; 536 } 537 538 if (cpu->cfg.ext_zfinx) { 539 if (!cpu->cfg.ext_zicsr) { 540 error_setg(errp, "Zfinx extension requires Zicsr"); 541 return; 542 } 543 if (riscv_has_ext(env, RVF)) { 544 error_setg(errp, 545 "Zfinx cannot be supported together with F extension"); 546 return; 547 } 548 } 549 550 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 551 error_setg(errp, "Zcf extension is only relevant to RV32"); 552 return; 553 } 554 555 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 556 error_setg(errp, "Zcf extension requires F extension"); 557 return; 558 } 559 560 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 561 error_setg(errp, "Zcd extension requires D extension"); 562 return; 563 } 564 565 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 566 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 567 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 568 "extension"); 569 return; 570 } 571 572 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 573 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 574 "Zcd extension"); 575 return; 576 } 577 578 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { 579 error_setg(errp, "Zcmt extension requires Zicsr extension"); 580 return; 581 } 582 583 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || 584 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || 585 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { 586 error_setg(errp, 587 "Vector crypto extensions require V or Zve* extensions"); 588 return; 589 } 590 591 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { 592 error_setg( 593 errp, 594 "Zvbc and Zvknhb extensions require V or Zve64x extensions"); 595 return; 596 } 597 598 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { 599 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { 600 error_setg(errp, "zicntr requires zicsr"); 601 return; 602 } 603 cpu->cfg.ext_zicntr = false; 604 } 605 606 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { 607 if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { 608 error_setg(errp, "zihpm requires zicsr"); 609 return; 610 } 611 cpu->cfg.ext_zihpm = false; 612 } 613 614 if (!cpu->cfg.ext_zihpm) { 615 cpu->cfg.pmu_mask = 0; 616 cpu->pmu_avail_ctrs = 0; 617 } 618 619 /* 620 * Disable isa extensions based on priv spec after we 621 * validated and set everything we need. 622 */ 623 riscv_cpu_disable_priv_spec_isa_exts(cpu); 624 } 625 626 #ifndef CONFIG_USER_ONLY 627 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, 628 RISCVCPUProfile *profile, 629 bool send_warn) 630 { 631 int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 632 633 if (profile->satp_mode > satp_max) { 634 if (send_warn) { 635 bool is_32bit = riscv_cpu_is_32bit(cpu); 636 const char *req_satp = satp_mode_str(profile->satp_mode, is_32bit); 637 const char *cur_satp = satp_mode_str(satp_max, is_32bit); 638 639 warn_report("Profile %s requires satp mode %s, " 640 "but satp mode %s was set", profile->name, 641 req_satp, cur_satp); 642 } 643 644 return false; 645 } 646 647 return true; 648 } 649 #endif 650 651 static void riscv_cpu_validate_profile(RISCVCPU *cpu, 652 RISCVCPUProfile *profile) 653 { 654 CPURISCVState *env = &cpu->env; 655 const char *warn_msg = "Profile %s mandates disabled extension %s"; 656 bool send_warn = profile->user_set && profile->enabled; 657 bool parent_enabled, profile_impl = true; 658 int i; 659 660 #ifndef CONFIG_USER_ONLY 661 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 662 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, 663 send_warn); 664 } 665 #endif 666 667 if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && 668 profile->priv_spec != env->priv_ver) { 669 profile_impl = false; 670 671 if (send_warn) { 672 warn_report("Profile %s requires priv spec %s, " 673 "but priv ver %s was set", profile->name, 674 cpu_priv_ver_to_str(profile->priv_spec), 675 cpu_priv_ver_to_str(env->priv_ver)); 676 } 677 } 678 679 for (i = 0; misa_bits[i] != 0; i++) { 680 uint32_t bit = misa_bits[i]; 681 682 if (!(profile->misa_ext & bit)) { 683 continue; 684 } 685 686 if (!riscv_has_ext(&cpu->env, bit)) { 687 profile_impl = false; 688 689 if (send_warn) { 690 warn_report(warn_msg, profile->name, 691 riscv_get_misa_ext_name(bit)); 692 } 693 } 694 } 695 696 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 697 int ext_offset = profile->ext_offsets[i]; 698 699 if (!isa_ext_is_enabled(cpu, ext_offset)) { 700 profile_impl = false; 701 702 if (send_warn) { 703 warn_report(warn_msg, profile->name, 704 cpu_cfg_ext_get_name(ext_offset)); 705 } 706 } 707 } 708 709 profile->enabled = profile_impl; 710 711 if (profile->parent != NULL) { 712 parent_enabled = object_property_get_bool(OBJECT(cpu), 713 profile->parent->name, 714 NULL); 715 profile->enabled = profile->enabled && parent_enabled; 716 } 717 } 718 719 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) 720 { 721 for (int i = 0; riscv_profiles[i] != NULL; i++) { 722 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); 723 } 724 } 725 726 static void riscv_cpu_init_implied_exts_rules(void) 727 { 728 RISCVCPUImpliedExtsRule *rule; 729 #ifndef CONFIG_USER_ONLY 730 MachineState *ms = MACHINE(qdev_get_machine()); 731 #endif 732 static bool initialized; 733 int i; 734 735 /* Implied rules only need to be initialized once. */ 736 if (initialized) { 737 return; 738 } 739 740 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 741 #ifndef CONFIG_USER_ONLY 742 rule->enabled = bitmap_new(ms->smp.cpus); 743 #endif 744 g_hash_table_insert(misa_ext_implied_rules, 745 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 746 } 747 748 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 749 #ifndef CONFIG_USER_ONLY 750 rule->enabled = bitmap_new(ms->smp.cpus); 751 #endif 752 g_hash_table_insert(multi_ext_implied_rules, 753 GUINT_TO_POINTER(rule->ext), (gpointer)rule); 754 } 755 756 initialized = true; 757 } 758 759 static void cpu_enable_implied_rule(RISCVCPU *cpu, 760 RISCVCPUImpliedExtsRule *rule) 761 { 762 CPURISCVState *env = &cpu->env; 763 RISCVCPUImpliedExtsRule *ir; 764 bool enabled = false; 765 int i; 766 767 #ifndef CONFIG_USER_ONLY 768 enabled = test_bit(cpu->env.mhartid, rule->enabled); 769 #endif 770 771 if (!enabled) { 772 /* Enable the implied MISAs. */ 773 if (rule->implied_misa_exts) { 774 riscv_cpu_set_misa_ext(env, 775 env->misa_ext | rule->implied_misa_exts); 776 777 for (i = 0; misa_bits[i] != 0; i++) { 778 if (rule->implied_misa_exts & misa_bits[i]) { 779 ir = g_hash_table_lookup(misa_ext_implied_rules, 780 GUINT_TO_POINTER(misa_bits[i])); 781 782 if (ir) { 783 cpu_enable_implied_rule(cpu, ir); 784 } 785 } 786 } 787 } 788 789 /* Enable the implied extensions. */ 790 for (i = 0; 791 rule->implied_multi_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) { 792 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); 793 794 ir = g_hash_table_lookup(multi_ext_implied_rules, 795 GUINT_TO_POINTER( 796 rule->implied_multi_exts[i])); 797 798 if (ir) { 799 cpu_enable_implied_rule(cpu, ir); 800 } 801 } 802 803 #ifndef CONFIG_USER_ONLY 804 bitmap_set(rule->enabled, cpu->env.mhartid, 1); 805 #endif 806 } 807 } 808 809 /* Zc extension has special implied rules that need to be handled separately. */ 810 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) 811 { 812 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 813 CPURISCVState *env = &cpu->env; 814 815 if (cpu->cfg.ext_zce) { 816 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 817 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); 818 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); 819 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); 820 821 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 822 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 823 } 824 } 825 826 /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ 827 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 828 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); 829 830 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { 831 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); 832 } 833 834 if (riscv_has_ext(env, RVD)) { 835 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); 836 } 837 } 838 } 839 840 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) 841 { 842 RISCVCPUImpliedExtsRule *rule; 843 int i; 844 845 /* Enable the implied extensions for Zc. */ 846 cpu_enable_zc_implied_rules(cpu); 847 848 /* Enable the implied MISAs. */ 849 for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) { 850 if (riscv_has_ext(&cpu->env, rule->ext)) { 851 cpu_enable_implied_rule(cpu, rule); 852 } 853 } 854 855 /* Enable the implied extensions. */ 856 for (i = 0; (rule = riscv_multi_ext_implied_rules[i]); i++) { 857 if (isa_ext_is_enabled(cpu, rule->ext)) { 858 cpu_enable_implied_rule(cpu, rule); 859 } 860 } 861 } 862 863 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 864 { 865 CPURISCVState *env = &cpu->env; 866 Error *local_err = NULL; 867 868 riscv_cpu_init_implied_exts_rules(); 869 riscv_cpu_enable_implied_rules(cpu); 870 871 riscv_cpu_validate_misa_priv(env, &local_err); 872 if (local_err != NULL) { 873 error_propagate(errp, local_err); 874 return; 875 } 876 877 riscv_cpu_update_named_features(cpu); 878 riscv_cpu_validate_profiles(cpu); 879 880 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { 881 /* 882 * Enhanced PMP should only be available 883 * on harts with PMP support 884 */ 885 error_setg(errp, "Invalid configuration: Smepmp requires PMP support"); 886 return; 887 } 888 889 riscv_cpu_validate_set_extensions(cpu, &local_err); 890 if (local_err != NULL) { 891 error_propagate(errp, local_err); 892 return; 893 } 894 } 895 896 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) 897 { 898 GPtrArray *dynamic_decoders; 899 dynamic_decoders = g_ptr_array_sized_new(decoder_table_size); 900 for (size_t i = 0; i < decoder_table_size; ++i) { 901 if (decoder_table[i].guard_func && 902 decoder_table[i].guard_func(&cpu->cfg)) { 903 g_ptr_array_add(dynamic_decoders, 904 (gpointer)decoder_table[i].riscv_cpu_decode_fn); 905 } 906 } 907 908 cpu->decoders = dynamic_decoders; 909 } 910 911 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) 912 { 913 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; 914 } 915 916 static bool riscv_cpu_is_generic(Object *cpu_obj) 917 { 918 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 919 } 920 921 /* 922 * We'll get here via the following path: 923 * 924 * riscv_cpu_realize() 925 * -> cpu_exec_realizefn() 926 * -> tcg_cpu_realize() (via accel_cpu_common_realize()) 927 */ 928 static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) 929 { 930 RISCVCPU *cpu = RISCV_CPU(cs); 931 932 if (!riscv_cpu_tcg_compatible(cpu)) { 933 g_autofree char *name = riscv_cpu_get_name(cpu); 934 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", 935 name); 936 return false; 937 } 938 939 #ifndef CONFIG_USER_ONLY 940 CPURISCVState *env = &cpu->env; 941 Error *local_err = NULL; 942 943 tcg_cflags_set(CPU(cs), CF_PCREL); 944 945 if (cpu->cfg.ext_sstc) { 946 riscv_timer_init(cpu); 947 } 948 949 if (cpu->cfg.pmu_mask) { 950 riscv_pmu_init(cpu, &local_err); 951 if (local_err != NULL) { 952 error_propagate(errp, local_err); 953 return false; 954 } 955 956 if (cpu->cfg.ext_sscofpmf) { 957 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 958 riscv_pmu_timer_cb, cpu); 959 } 960 } 961 962 /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ 963 if (riscv_has_ext(env, RVH)) { 964 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; 965 } 966 #endif 967 968 return true; 969 } 970 971 typedef struct RISCVCPUMisaExtConfig { 972 target_ulong misa_bit; 973 bool enabled; 974 } RISCVCPUMisaExtConfig; 975 976 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 977 void *opaque, Error **errp) 978 { 979 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 980 target_ulong misa_bit = misa_ext_cfg->misa_bit; 981 RISCVCPU *cpu = RISCV_CPU(obj); 982 CPURISCVState *env = &cpu->env; 983 bool vendor_cpu = riscv_cpu_is_vendor(obj); 984 bool prev_val, value; 985 986 if (!visit_type_bool(v, name, &value, errp)) { 987 return; 988 } 989 990 cpu_misa_ext_add_user_opt(misa_bit, value); 991 992 prev_val = env->misa_ext & misa_bit; 993 994 if (value == prev_val) { 995 return; 996 } 997 998 if (value) { 999 if (vendor_cpu) { 1000 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1001 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1002 cpuname); 1003 return; 1004 } 1005 1006 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { 1007 /* 1008 * Note: the 'priv_spec' command line option, if present, 1009 * will take precedence over this priv_ver bump. 1010 */ 1011 env->priv_ver = PRIV_VERSION_1_12_0; 1012 } 1013 } 1014 1015 riscv_cpu_write_misa_bit(cpu, misa_bit, value); 1016 } 1017 1018 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1019 void *opaque, Error **errp) 1020 { 1021 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1022 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1023 RISCVCPU *cpu = RISCV_CPU(obj); 1024 CPURISCVState *env = &cpu->env; 1025 bool value; 1026 1027 value = env->misa_ext & misa_bit; 1028 1029 visit_type_bool(v, name, &value, errp); 1030 } 1031 1032 #define MISA_CFG(_bit, _enabled) \ 1033 {.misa_bit = _bit, .enabled = _enabled} 1034 1035 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1036 MISA_CFG(RVA, true), 1037 MISA_CFG(RVC, true), 1038 MISA_CFG(RVD, true), 1039 MISA_CFG(RVF, true), 1040 MISA_CFG(RVI, true), 1041 MISA_CFG(RVE, false), 1042 MISA_CFG(RVM, true), 1043 MISA_CFG(RVS, true), 1044 MISA_CFG(RVU, true), 1045 MISA_CFG(RVH, true), 1046 MISA_CFG(RVJ, false), 1047 MISA_CFG(RVV, false), 1048 MISA_CFG(RVG, false), 1049 MISA_CFG(RVB, false), 1050 }; 1051 1052 /* 1053 * We do not support user choice tracking for MISA 1054 * extensions yet because, so far, we do not silently 1055 * change MISA bits during realize() (RVG enables MISA 1056 * bits but the user is warned about it). 1057 */ 1058 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1059 { 1060 bool use_def_vals = riscv_cpu_is_generic(cpu_obj); 1061 int i; 1062 1063 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1064 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1065 int bit = misa_cfg->misa_bit; 1066 const char *name = riscv_get_misa_ext_name(bit); 1067 const char *desc = riscv_get_misa_ext_description(bit); 1068 1069 /* Check if KVM already created the property */ 1070 if (object_property_find(cpu_obj, name)) { 1071 continue; 1072 } 1073 1074 object_property_add(cpu_obj, name, "bool", 1075 cpu_get_misa_ext_cfg, 1076 cpu_set_misa_ext_cfg, 1077 NULL, (void *)misa_cfg); 1078 object_property_set_description(cpu_obj, name, desc); 1079 if (use_def_vals) { 1080 riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, 1081 misa_cfg->enabled); 1082 } 1083 } 1084 } 1085 1086 static void cpu_set_profile(Object *obj, Visitor *v, const char *name, 1087 void *opaque, Error **errp) 1088 { 1089 RISCVCPUProfile *profile = opaque; 1090 RISCVCPU *cpu = RISCV_CPU(obj); 1091 bool value; 1092 int i, ext_offset; 1093 1094 if (riscv_cpu_is_vendor(obj)) { 1095 error_setg(errp, "Profile %s is not available for vendor CPUs", 1096 profile->name); 1097 return; 1098 } 1099 1100 if (cpu->env.misa_mxl != MXL_RV64) { 1101 error_setg(errp, "Profile %s only available for 64 bit CPUs", 1102 profile->name); 1103 return; 1104 } 1105 1106 if (!visit_type_bool(v, name, &value, errp)) { 1107 return; 1108 } 1109 1110 profile->user_set = true; 1111 profile->enabled = value; 1112 1113 if (profile->parent != NULL) { 1114 object_property_set_bool(obj, profile->parent->name, 1115 profile->enabled, NULL); 1116 } 1117 1118 if (profile->enabled) { 1119 cpu->env.priv_ver = profile->priv_spec; 1120 } 1121 1122 #ifndef CONFIG_USER_ONLY 1123 if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) { 1124 object_property_set_bool(obj, "mmu", true, NULL); 1125 const char *satp_prop = satp_mode_str(profile->satp_mode, 1126 riscv_cpu_is_32bit(cpu)); 1127 object_property_set_bool(obj, satp_prop, profile->enabled, NULL); 1128 } 1129 #endif 1130 1131 for (i = 0; misa_bits[i] != 0; i++) { 1132 uint32_t bit = misa_bits[i]; 1133 1134 if (!(profile->misa_ext & bit)) { 1135 continue; 1136 } 1137 1138 if (bit == RVI && !profile->enabled) { 1139 /* 1140 * Disabling profiles will not disable the base 1141 * ISA RV64I. 1142 */ 1143 continue; 1144 } 1145 1146 cpu_misa_ext_add_user_opt(bit, profile->enabled); 1147 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); 1148 } 1149 1150 for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { 1151 ext_offset = profile->ext_offsets[i]; 1152 1153 if (profile->enabled) { 1154 if (cpu_cfg_offset_is_named_feat(ext_offset)) { 1155 riscv_cpu_enable_named_feat(cpu, ext_offset); 1156 } 1157 1158 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); 1159 } 1160 1161 cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); 1162 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); 1163 } 1164 } 1165 1166 static void cpu_get_profile(Object *obj, Visitor *v, const char *name, 1167 void *opaque, Error **errp) 1168 { 1169 RISCVCPUProfile *profile = opaque; 1170 bool value = profile->enabled; 1171 1172 visit_type_bool(v, name, &value, errp); 1173 } 1174 1175 static void riscv_cpu_add_profiles(Object *cpu_obj) 1176 { 1177 for (int i = 0; riscv_profiles[i] != NULL; i++) { 1178 const RISCVCPUProfile *profile = riscv_profiles[i]; 1179 1180 object_property_add(cpu_obj, profile->name, "bool", 1181 cpu_get_profile, cpu_set_profile, 1182 NULL, (void *)profile); 1183 1184 /* 1185 * CPUs might enable a profile right from the start. 1186 * Enable its mandatory extensions right away in this 1187 * case. 1188 */ 1189 if (profile->enabled) { 1190 object_property_set_bool(cpu_obj, profile->name, true, NULL); 1191 } 1192 } 1193 } 1194 1195 static bool cpu_ext_is_deprecated(const char *ext_name) 1196 { 1197 return isupper(ext_name[0]); 1198 } 1199 1200 /* 1201 * String will be allocated in the heap. Caller is responsible 1202 * for freeing it. 1203 */ 1204 static char *cpu_ext_to_lower(const char *ext_name) 1205 { 1206 char *ret = g_malloc0(strlen(ext_name) + 1); 1207 1208 strcpy(ret, ext_name); 1209 ret[0] = tolower(ret[0]); 1210 1211 return ret; 1212 } 1213 1214 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1215 void *opaque, Error **errp) 1216 { 1217 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1218 RISCVCPU *cpu = RISCV_CPU(obj); 1219 bool vendor_cpu = riscv_cpu_is_vendor(obj); 1220 bool prev_val, value; 1221 1222 if (!visit_type_bool(v, name, &value, errp)) { 1223 return; 1224 } 1225 1226 if (cpu_ext_is_deprecated(multi_ext_cfg->name)) { 1227 g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name); 1228 1229 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", 1230 multi_ext_cfg->name, lower); 1231 } 1232 1233 cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); 1234 1235 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); 1236 1237 if (value == prev_val) { 1238 return; 1239 } 1240 1241 if (value && vendor_cpu) { 1242 g_autofree char *cpuname = riscv_cpu_get_name(cpu); 1243 error_setg(errp, "'%s' CPU does not allow enabling extensions", 1244 cpuname); 1245 return; 1246 } 1247 1248 if (value) { 1249 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); 1250 } 1251 1252 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); 1253 } 1254 1255 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1256 void *opaque, Error **errp) 1257 { 1258 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1259 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1260 1261 visit_type_bool(v, name, &value, errp); 1262 } 1263 1264 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1265 const RISCVCPUMultiExtConfig *multi_cfg) 1266 { 1267 bool generic_cpu = riscv_cpu_is_generic(cpu_obj); 1268 bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name); 1269 1270 object_property_add(cpu_obj, multi_cfg->name, "bool", 1271 cpu_get_multi_ext_cfg, 1272 cpu_set_multi_ext_cfg, 1273 NULL, (void *)multi_cfg); 1274 1275 if (!generic_cpu || deprecated_ext) { 1276 return; 1277 } 1278 1279 /* 1280 * Set def val directly instead of using 1281 * object_property_set_bool() to save the set() 1282 * callback hash for user inputs. 1283 */ 1284 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1285 multi_cfg->enabled); 1286 } 1287 1288 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1289 const RISCVCPUMultiExtConfig *array) 1290 { 1291 const RISCVCPUMultiExtConfig *prop; 1292 1293 g_assert(array); 1294 1295 for (prop = array; prop && prop->name; prop++) { 1296 cpu_add_multi_ext_prop(obj, prop); 1297 } 1298 } 1299 1300 /* 1301 * Add CPU properties with user-facing flags. 1302 * 1303 * This will overwrite existing env->misa_ext values with the 1304 * defaults set via riscv_cpu_add_misa_properties(). 1305 */ 1306 static void riscv_cpu_add_user_properties(Object *obj) 1307 { 1308 #ifndef CONFIG_USER_ONLY 1309 riscv_add_satp_mode_properties(obj); 1310 #endif 1311 1312 riscv_cpu_add_misa_properties(obj); 1313 1314 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1315 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1316 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1317 1318 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); 1319 1320 riscv_cpu_add_profiles(obj); 1321 } 1322 1323 /* 1324 * The 'max' type CPU will have all possible ratified 1325 * non-vendor extensions enabled. 1326 */ 1327 static void riscv_init_max_cpu_extensions(Object *obj) 1328 { 1329 RISCVCPU *cpu = RISCV_CPU(obj); 1330 CPURISCVState *env = &cpu->env; 1331 const RISCVCPUMultiExtConfig *prop; 1332 1333 /* Enable RVG, RVJ and RVV that are disabled by default */ 1334 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV); 1335 1336 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1337 isa_ext_update_enabled(cpu, prop->offset, true); 1338 } 1339 1340 /* 1341 * Some extensions can't be added without backward compatibilty concerns. 1342 * Disable those, the user can still opt in to them on the command line. 1343 */ 1344 cpu->cfg.ext_svade = false; 1345 1346 /* set vector version */ 1347 env->vext_ver = VEXT_VERSION_1_00_0; 1348 1349 /* Zfinx is not compatible with F. Disable it */ 1350 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1351 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1352 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1353 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1354 1355 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1356 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1357 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1358 1359 if (env->misa_mxl != MXL_RV32) { 1360 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1361 } 1362 } 1363 1364 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1365 { 1366 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1367 } 1368 1369 static void riscv_tcg_cpu_instance_init(CPUState *cs) 1370 { 1371 RISCVCPU *cpu = RISCV_CPU(cs); 1372 Object *obj = OBJECT(cpu); 1373 1374 misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1375 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1376 1377 if (!misa_ext_implied_rules) { 1378 misa_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1379 } 1380 1381 if (!multi_ext_implied_rules) { 1382 multi_ext_implied_rules = g_hash_table_new(NULL, g_direct_equal); 1383 } 1384 1385 riscv_cpu_add_user_properties(obj); 1386 1387 if (riscv_cpu_has_max_extensions(obj)) { 1388 riscv_init_max_cpu_extensions(obj); 1389 } 1390 } 1391 1392 static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) 1393 { 1394 /* 1395 * All cpus use the same set of operations. 1396 */ 1397 cc->tcg_ops = &riscv_tcg_ops; 1398 } 1399 1400 static void riscv_tcg_cpu_class_init(CPUClass *cc) 1401 { 1402 cc->init_accel_cpu = riscv_tcg_cpu_init_ops; 1403 } 1404 1405 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) 1406 { 1407 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1408 1409 acc->cpu_class_init = riscv_tcg_cpu_class_init; 1410 acc->cpu_instance_init = riscv_tcg_cpu_instance_init; 1411 acc->cpu_target_realize = riscv_tcg_cpu_realize; 1412 } 1413 1414 static const TypeInfo riscv_tcg_cpu_accel_type_info = { 1415 .name = ACCEL_CPU_NAME("tcg"), 1416 1417 .parent = TYPE_ACCEL_CPU, 1418 .class_init = riscv_tcg_cpu_accel_class_init, 1419 .abstract = true, 1420 }; 1421 1422 static void riscv_tcg_cpu_accel_register_types(void) 1423 { 1424 type_register_static(&riscv_tcg_cpu_accel_type_info); 1425 } 1426 type_init(riscv_tcg_cpu_accel_register_types); 1427