1 /* 2 * RISC-V PMU file. 3 * 4 * Copyright (c) 2021 Western Digital Corporation or its affiliates. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "qemu/error-report.h" 22 #include "qemu/timer.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "sysemu/cpu-timers.h" 26 #include "sysemu/device_tree.h" 27 28 #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ 29 30 /* 31 * To keep it simple, any event can be mapped to any programmable counters in 32 * QEMU. The generic cycle & instruction count events can also be monitored 33 * using programmable counters. In that case, mcycle & minstret must continue 34 * to provide the correct value as well. Heterogeneous PMU per hart is not 35 * supported yet. Thus, number of counters are same across all harts. 36 */ 37 void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) 38 { 39 uint32_t fdt_event_ctr_map[15] = {}; 40 41 /* 42 * The event encoding is specified in the SBI specification 43 * Event idx is a 20bits wide number encoded as follows: 44 * event_idx[19:16] = type 45 * event_idx[15:0] = code 46 * The code field in cache events are encoded as follows: 47 * event_idx.code[15:3] = cache_id 48 * event_idx.code[2:1] = op_id 49 * event_idx.code[0:0] = result_id 50 */ 51 52 /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ 53 fdt_event_ctr_map[0] = cpu_to_be32(0x00000001); 54 fdt_event_ctr_map[1] = cpu_to_be32(0x00000001); 55 fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0); 56 57 /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ 58 fdt_event_ctr_map[3] = cpu_to_be32(0x00000002); 59 fdt_event_ctr_map[4] = cpu_to_be32(0x00000002); 60 fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2); 61 62 /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ 63 fdt_event_ctr_map[6] = cpu_to_be32(0x00010019); 64 fdt_event_ctr_map[7] = cpu_to_be32(0x00010019); 65 fdt_event_ctr_map[8] = cpu_to_be32(cmask); 66 67 /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ 68 fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B); 69 fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B); 70 fdt_event_ctr_map[11] = cpu_to_be32(cmask); 71 72 /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ 73 fdt_event_ctr_map[12] = cpu_to_be32(0x00010021); 74 fdt_event_ctr_map[13] = cpu_to_be32(0x00010021); 75 fdt_event_ctr_map[14] = cpu_to_be32(cmask); 76 77 /* This a OpenSBI specific DT property documented in OpenSBI docs */ 78 qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", 79 fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); 80 } 81 82 static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) 83 { 84 if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS || 85 !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) { 86 return false; 87 } else { 88 return true; 89 } 90 } 91 92 static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx) 93 { 94 CPURISCVState *env = &cpu->env; 95 96 if (riscv_pmu_counter_valid(cpu, ctr_idx) && 97 !get_field(env->mcountinhibit, BIT(ctr_idx))) { 98 return true; 99 } else { 100 return false; 101 } 102 } 103 104 static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) 105 { 106 CPURISCVState *env = &cpu->env; 107 target_ulong max_val = UINT32_MAX; 108 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 109 bool virt_on = env->virt_enabled; 110 111 /* Privilege mode filtering */ 112 if ((env->priv == PRV_M && 113 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || 114 (env->priv == PRV_S && virt_on && 115 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || 116 (env->priv == PRV_U && virt_on && 117 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) || 118 (env->priv == PRV_S && !virt_on && 119 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) || 120 (env->priv == PRV_U && !virt_on && 121 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) { 122 return 0; 123 } 124 125 /* Handle the overflow scenario */ 126 if (counter->mhpmcounter_val == max_val) { 127 if (counter->mhpmcounterh_val == max_val) { 128 counter->mhpmcounter_val = 0; 129 counter->mhpmcounterh_val = 0; 130 /* Generate interrupt only if OF bit is clear */ 131 if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { 132 env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF; 133 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); 134 } 135 } else { 136 counter->mhpmcounterh_val++; 137 } 138 } else { 139 counter->mhpmcounter_val++; 140 } 141 142 return 0; 143 } 144 145 static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx) 146 { 147 CPURISCVState *env = &cpu->env; 148 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 149 uint64_t max_val = UINT64_MAX; 150 bool virt_on = env->virt_enabled; 151 152 /* Privilege mode filtering */ 153 if ((env->priv == PRV_M && 154 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || 155 (env->priv == PRV_S && virt_on && 156 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || 157 (env->priv == PRV_U && virt_on && 158 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || 159 (env->priv == PRV_S && !virt_on && 160 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || 161 (env->priv == PRV_U && !virt_on && 162 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { 163 return 0; 164 } 165 166 /* Handle the overflow scenario */ 167 if (counter->mhpmcounter_val == max_val) { 168 counter->mhpmcounter_val = 0; 169 /* Generate interrupt only if OF bit is clear */ 170 if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { 171 env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF; 172 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); 173 } 174 } else { 175 counter->mhpmcounter_val++; 176 } 177 return 0; 178 } 179 180 /* 181 * Information needed to update counters: 182 * new_priv, new_virt: To correctly save starting snapshot for the newly 183 * started mode. Look at array being indexed with newprv. 184 * old_priv, old_virt: To correctly select previous snapshot for old priv 185 * and compute delta. Also to select correct counter 186 * to inc. Look at arrays being indexed with env->priv. 187 * 188 * To avoid the complexity of calling this function, we assume that 189 * env->priv and env->virt_enabled contain old priv and old virt and 190 * new priv and new virt values are passed in as arguments. 191 */ 192 static void riscv_pmu_icount_update_priv(CPURISCVState *env, 193 target_ulong newpriv, bool new_virt) 194 { 195 uint64_t *snapshot_prev, *snapshot_new; 196 uint64_t current_icount; 197 uint64_t *counter_arr; 198 uint64_t delta; 199 200 if (icount_enabled()) { 201 current_icount = icount_get_raw(); 202 } else { 203 current_icount = cpu_get_host_ticks(); 204 } 205 206 if (env->virt_enabled) { 207 counter_arr = env->pmu_fixed_ctrs[1].counter_virt; 208 snapshot_prev = env->pmu_fixed_ctrs[1].counter_virt_prev; 209 } else { 210 counter_arr = env->pmu_fixed_ctrs[1].counter; 211 snapshot_prev = env->pmu_fixed_ctrs[1].counter_prev; 212 } 213 214 if (new_virt) { 215 snapshot_new = env->pmu_fixed_ctrs[1].counter_virt_prev; 216 } else { 217 snapshot_new = env->pmu_fixed_ctrs[1].counter_prev; 218 } 219 220 /* 221 * new_priv can be same as env->priv. So we need to calculate 222 * delta first before updating snapshot_new[new_priv]. 223 */ 224 delta = current_icount - snapshot_prev[env->priv]; 225 snapshot_new[newpriv] = current_icount; 226 227 counter_arr[env->priv] += delta; 228 } 229 230 static void riscv_pmu_cycle_update_priv(CPURISCVState *env, 231 target_ulong newpriv, bool new_virt) 232 { 233 uint64_t *snapshot_prev, *snapshot_new; 234 uint64_t current_ticks; 235 uint64_t *counter_arr; 236 uint64_t delta; 237 238 if (icount_enabled()) { 239 current_ticks = icount_get(); 240 } else { 241 current_ticks = cpu_get_host_ticks(); 242 } 243 244 if (env->virt_enabled) { 245 counter_arr = env->pmu_fixed_ctrs[0].counter_virt; 246 snapshot_prev = env->pmu_fixed_ctrs[0].counter_virt_prev; 247 } else { 248 counter_arr = env->pmu_fixed_ctrs[0].counter; 249 snapshot_prev = env->pmu_fixed_ctrs[0].counter_prev; 250 } 251 252 if (new_virt) { 253 snapshot_new = env->pmu_fixed_ctrs[0].counter_virt_prev; 254 } else { 255 snapshot_new = env->pmu_fixed_ctrs[0].counter_prev; 256 } 257 258 delta = current_ticks - snapshot_prev[env->priv]; 259 snapshot_new[newpriv] = current_ticks; 260 261 counter_arr[env->priv] += delta; 262 } 263 264 void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, 265 bool new_virt) 266 { 267 riscv_pmu_cycle_update_priv(env, newpriv, new_virt); 268 riscv_pmu_icount_update_priv(env, newpriv, new_virt); 269 } 270 271 int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) 272 { 273 uint32_t ctr_idx; 274 int ret; 275 CPURISCVState *env = &cpu->env; 276 gpointer value; 277 278 if (!cpu->cfg.pmu_mask) { 279 return 0; 280 } 281 value = g_hash_table_lookup(cpu->pmu_event_ctr_map, 282 GUINT_TO_POINTER(event_idx)); 283 if (!value) { 284 return -1; 285 } 286 287 ctr_idx = GPOINTER_TO_UINT(value); 288 if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { 289 return -1; 290 } 291 292 if (riscv_cpu_mxl(env) == MXL_RV32) { 293 ret = riscv_pmu_incr_ctr_rv32(cpu, ctr_idx); 294 } else { 295 ret = riscv_pmu_incr_ctr_rv64(cpu, ctr_idx); 296 } 297 298 return ret; 299 } 300 301 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, 302 uint32_t target_ctr) 303 { 304 RISCVCPU *cpu; 305 uint32_t event_idx; 306 uint32_t ctr_idx; 307 308 /* Fixed instret counter */ 309 if (target_ctr == 2) { 310 return true; 311 } 312 313 cpu = env_archcpu(env); 314 if (!cpu->pmu_event_ctr_map) { 315 return false; 316 } 317 318 event_idx = RISCV_PMU_EVENT_HW_INSTRUCTIONS; 319 ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map, 320 GUINT_TO_POINTER(event_idx))); 321 if (!ctr_idx) { 322 return false; 323 } 324 325 return target_ctr == ctr_idx ? true : false; 326 } 327 328 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) 329 { 330 RISCVCPU *cpu; 331 uint32_t event_idx; 332 uint32_t ctr_idx; 333 334 /* Fixed mcycle counter */ 335 if (target_ctr == 0) { 336 return true; 337 } 338 339 cpu = env_archcpu(env); 340 if (!cpu->pmu_event_ctr_map) { 341 return false; 342 } 343 344 event_idx = RISCV_PMU_EVENT_HW_CPU_CYCLES; 345 ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map, 346 GUINT_TO_POINTER(event_idx))); 347 348 /* Counter zero is not used for event_ctr_map */ 349 if (!ctr_idx) { 350 return false; 351 } 352 353 return (target_ctr == ctr_idx) ? true : false; 354 } 355 356 static gboolean pmu_remove_event_map(gpointer key, gpointer value, 357 gpointer udata) 358 { 359 return (GPOINTER_TO_UINT(value) == GPOINTER_TO_UINT(udata)) ? true : false; 360 } 361 362 static int64_t pmu_icount_ticks_to_ns(int64_t value) 363 { 364 int64_t ret = 0; 365 366 if (icount_enabled()) { 367 ret = icount_to_ns(value); 368 } else { 369 ret = (NANOSECONDS_PER_SECOND / RISCV_TIMEBASE_FREQ) * value; 370 } 371 372 return ret; 373 } 374 375 int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, 376 uint32_t ctr_idx) 377 { 378 uint32_t event_idx; 379 RISCVCPU *cpu = env_archcpu(env); 380 381 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) { 382 return -1; 383 } 384 385 /* 386 * Expected mhpmevent value is zero for reset case. Remove the current 387 * mapping. 388 */ 389 if (!value) { 390 g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, 391 pmu_remove_event_map, 392 GUINT_TO_POINTER(ctr_idx)); 393 return 0; 394 } 395 396 event_idx = value & MHPMEVENT_IDX_MASK; 397 if (g_hash_table_lookup(cpu->pmu_event_ctr_map, 398 GUINT_TO_POINTER(event_idx))) { 399 return 0; 400 } 401 402 switch (event_idx) { 403 case RISCV_PMU_EVENT_HW_CPU_CYCLES: 404 case RISCV_PMU_EVENT_HW_INSTRUCTIONS: 405 case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS: 406 case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS: 407 case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: 408 break; 409 default: 410 /* We don't support any raw events right now */ 411 return -1; 412 } 413 g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx), 414 GUINT_TO_POINTER(ctr_idx)); 415 416 return 0; 417 } 418 419 static bool pmu_hpmevent_is_of_set(CPURISCVState *env, uint32_t ctr_idx) 420 { 421 target_ulong mhpmevent_val; 422 uint64_t of_bit_mask; 423 424 if (riscv_cpu_mxl(env) == MXL_RV32) { 425 mhpmevent_val = env->mhpmeventh_val[ctr_idx]; 426 of_bit_mask = MHPMEVENTH_BIT_OF; 427 } else { 428 mhpmevent_val = env->mhpmevent_val[ctr_idx]; 429 of_bit_mask = MHPMEVENT_BIT_OF; 430 } 431 432 return get_field(mhpmevent_val, of_bit_mask); 433 } 434 435 static bool pmu_hpmevent_set_of_if_clear(CPURISCVState *env, uint32_t ctr_idx) 436 { 437 target_ulong *mhpmevent_val; 438 uint64_t of_bit_mask; 439 440 if (riscv_cpu_mxl(env) == MXL_RV32) { 441 mhpmevent_val = &env->mhpmeventh_val[ctr_idx]; 442 of_bit_mask = MHPMEVENTH_BIT_OF; 443 } else { 444 mhpmevent_val = &env->mhpmevent_val[ctr_idx]; 445 of_bit_mask = MHPMEVENT_BIT_OF; 446 } 447 448 if (!get_field(*mhpmevent_val, of_bit_mask)) { 449 *mhpmevent_val |= of_bit_mask; 450 return true; 451 } 452 453 return false; 454 } 455 456 static void pmu_timer_trigger_irq(RISCVCPU *cpu, 457 enum riscv_pmu_event_idx evt_idx) 458 { 459 uint32_t ctr_idx; 460 CPURISCVState *env = &cpu->env; 461 PMUCTRState *counter; 462 int64_t irq_trigger_at; 463 uint64_t curr_ctr_val, curr_ctrh_val; 464 uint64_t ctr_val; 465 466 if (evt_idx != RISCV_PMU_EVENT_HW_CPU_CYCLES && 467 evt_idx != RISCV_PMU_EVENT_HW_INSTRUCTIONS) { 468 return; 469 } 470 471 ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map, 472 GUINT_TO_POINTER(evt_idx))); 473 if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { 474 return; 475 } 476 477 /* Generate interrupt only if OF bit is clear */ 478 if (pmu_hpmevent_is_of_set(env, ctr_idx)) { 479 return; 480 } 481 482 counter = &env->pmu_ctrs[ctr_idx]; 483 if (counter->irq_overflow_left > 0) { 484 irq_trigger_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 485 counter->irq_overflow_left; 486 timer_mod_anticipate_ns(cpu->pmu_timer, irq_trigger_at); 487 counter->irq_overflow_left = 0; 488 return; 489 } 490 491 riscv_pmu_read_ctr(env, (target_ulong *)&curr_ctr_val, false, ctr_idx); 492 ctr_val = counter->mhpmcounter_val; 493 if (riscv_cpu_mxl(env) == MXL_RV32) { 494 riscv_pmu_read_ctr(env, (target_ulong *)&curr_ctrh_val, true, ctr_idx); 495 curr_ctr_val = curr_ctr_val | (curr_ctrh_val << 32); 496 ctr_val = ctr_val | 497 ((uint64_t)counter->mhpmcounterh_val << 32); 498 } 499 500 /* 501 * We can not accommodate for inhibited modes when setting up timer. Check 502 * if the counter has actually overflowed or not by comparing current 503 * counter value (accommodated for inhibited modes) with software written 504 * counter value. 505 */ 506 if (curr_ctr_val >= ctr_val) { 507 riscv_pmu_setup_timer(env, curr_ctr_val, ctr_idx); 508 return; 509 } 510 511 if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) { 512 if (pmu_hpmevent_set_of_if_clear(env, ctr_idx)) { 513 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); 514 } 515 } 516 } 517 518 /* Timer callback for instret and cycle counter overflow */ 519 void riscv_pmu_timer_cb(void *priv) 520 { 521 RISCVCPU *cpu = priv; 522 523 /* Timer event was triggered only for these events */ 524 pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES); 525 pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS); 526 } 527 528 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) 529 { 530 uint64_t overflow_delta, overflow_at, curr_ns; 531 int64_t overflow_ns, overflow_left = 0; 532 RISCVCPU *cpu = env_archcpu(env); 533 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 534 535 /* No need to setup a timer if LCOFI is disabled when OF is set */ 536 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf || 537 pmu_hpmevent_is_of_set(env, ctr_idx)) { 538 return -1; 539 } 540 541 if (value) { 542 overflow_delta = UINT64_MAX - value + 1; 543 } else { 544 overflow_delta = UINT64_MAX; 545 } 546 547 /* 548 * QEMU supports only int64_t timers while RISC-V counters are uint64_t. 549 * Compute the leftover and save it so that it can be reprogrammed again 550 * when timer expires. 551 */ 552 if (overflow_delta > INT64_MAX) { 553 overflow_left = overflow_delta - INT64_MAX; 554 } 555 556 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 557 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 558 overflow_ns = pmu_icount_ticks_to_ns((int64_t)overflow_delta); 559 overflow_left = pmu_icount_ticks_to_ns(overflow_left) ; 560 } else { 561 return -1; 562 } 563 curr_ns = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 564 overflow_at = curr_ns + overflow_ns; 565 if (overflow_at <= curr_ns) 566 overflow_at = UINT64_MAX; 567 568 if (overflow_at > INT64_MAX) { 569 overflow_left += overflow_at - INT64_MAX; 570 counter->irq_overflow_left = overflow_left; 571 overflow_at = INT64_MAX; 572 } 573 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); 574 575 return 0; 576 } 577 578 579 void riscv_pmu_init(RISCVCPU *cpu, Error **errp) 580 { 581 if (cpu->cfg.pmu_mask & (COUNTEREN_CY | COUNTEREN_TM | COUNTEREN_IR)) { 582 error_setg(errp, "\"pmu-mask\" contains invalid bits (0-2) set"); 583 return; 584 } 585 586 if (ctpop32(cpu->cfg.pmu_mask) > (RV_MAX_MHPMCOUNTERS - 3)) { 587 error_setg(errp, "Number of counters exceeds maximum available"); 588 return; 589 } 590 591 cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal); 592 if (!cpu->pmu_event_ctr_map) { 593 error_setg(errp, "Unable to allocate PMU event hash table"); 594 return; 595 } 596 597 cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask; 598 } 599