1 /* 2 * RISC-V PMU file. 3 * 4 * Copyright (c) 2021 Western Digital Corporation or its affiliates. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "qemu/error-report.h" 22 #include "qemu/timer.h" 23 #include "cpu.h" 24 #include "pmu.h" 25 #include "sysemu/cpu-timers.h" 26 #include "sysemu/device_tree.h" 27 28 #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ 29 30 /* 31 * To keep it simple, any event can be mapped to any programmable counters in 32 * QEMU. The generic cycle & instruction count events can also be monitored 33 * using programmable counters. In that case, mcycle & minstret must continue 34 * to provide the correct value as well. Heterogeneous PMU per hart is not 35 * supported yet. Thus, number of counters are same across all harts. 36 */ 37 void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) 38 { 39 uint32_t fdt_event_ctr_map[15] = {}; 40 41 /* 42 * The event encoding is specified in the SBI specification 43 * Event idx is a 20bits wide number encoded as follows: 44 * event_idx[19:16] = type 45 * event_idx[15:0] = code 46 * The code field in cache events are encoded as follows: 47 * event_idx.code[15:3] = cache_id 48 * event_idx.code[2:1] = op_id 49 * event_idx.code[0:0] = result_id 50 */ 51 52 /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ 53 fdt_event_ctr_map[0] = cpu_to_be32(0x00000001); 54 fdt_event_ctr_map[1] = cpu_to_be32(0x00000001); 55 fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0); 56 57 /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ 58 fdt_event_ctr_map[3] = cpu_to_be32(0x00000002); 59 fdt_event_ctr_map[4] = cpu_to_be32(0x00000002); 60 fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2); 61 62 /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ 63 fdt_event_ctr_map[6] = cpu_to_be32(0x00010019); 64 fdt_event_ctr_map[7] = cpu_to_be32(0x00010019); 65 fdt_event_ctr_map[8] = cpu_to_be32(cmask); 66 67 /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ 68 fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B); 69 fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B); 70 fdt_event_ctr_map[11] = cpu_to_be32(cmask); 71 72 /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ 73 fdt_event_ctr_map[12] = cpu_to_be32(0x00010021); 74 fdt_event_ctr_map[13] = cpu_to_be32(0x00010021); 75 fdt_event_ctr_map[14] = cpu_to_be32(cmask); 76 77 /* This a OpenSBI specific DT property documented in OpenSBI docs */ 78 qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", 79 fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); 80 } 81 82 static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) 83 { 84 if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS || 85 !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) { 86 return false; 87 } else { 88 return true; 89 } 90 } 91 92 static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx) 93 { 94 CPURISCVState *env = &cpu->env; 95 96 if (riscv_pmu_counter_valid(cpu, ctr_idx) && 97 !get_field(env->mcountinhibit, BIT(ctr_idx))) { 98 return true; 99 } else { 100 return false; 101 } 102 } 103 104 static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) 105 { 106 CPURISCVState *env = &cpu->env; 107 target_ulong max_val = UINT32_MAX; 108 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 109 bool virt_on = env->virt_enabled; 110 111 /* Privilege mode filtering */ 112 if ((env->priv == PRV_M && 113 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || 114 (env->priv == PRV_S && virt_on && 115 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || 116 (env->priv == PRV_U && virt_on && 117 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) || 118 (env->priv == PRV_S && !virt_on && 119 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) || 120 (env->priv == PRV_U && !virt_on && 121 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) { 122 return 0; 123 } 124 125 /* Handle the overflow scenario */ 126 if (counter->mhpmcounter_val == max_val) { 127 if (counter->mhpmcounterh_val == max_val) { 128 counter->mhpmcounter_val = 0; 129 counter->mhpmcounterh_val = 0; 130 /* Generate interrupt only if OF bit is clear */ 131 if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { 132 env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF; 133 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); 134 } 135 } else { 136 counter->mhpmcounterh_val++; 137 } 138 } else { 139 counter->mhpmcounter_val++; 140 } 141 142 return 0; 143 } 144 145 static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx) 146 { 147 CPURISCVState *env = &cpu->env; 148 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 149 uint64_t max_val = UINT64_MAX; 150 bool virt_on = env->virt_enabled; 151 152 /* Privilege mode filtering */ 153 if ((env->priv == PRV_M && 154 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) || 155 (env->priv == PRV_S && virt_on && 156 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) || 157 (env->priv == PRV_U && virt_on && 158 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) || 159 (env->priv == PRV_S && !virt_on && 160 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) || 161 (env->priv == PRV_U && !virt_on && 162 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { 163 return 0; 164 } 165 166 /* Handle the overflow scenario */ 167 if (counter->mhpmcounter_val == max_val) { 168 counter->mhpmcounter_val = 0; 169 /* Generate interrupt only if OF bit is clear */ 170 if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { 171 env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF; 172 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); 173 } 174 } else { 175 counter->mhpmcounter_val++; 176 } 177 return 0; 178 } 179 180 /* 181 * Information needed to update counters: 182 * new_priv, new_virt: To correctly save starting snapshot for the newly 183 * started mode. Look at array being indexed with newprv. 184 * old_priv, old_virt: To correctly select previous snapshot for old priv 185 * and compute delta. Also to select correct counter 186 * to inc. Look at arrays being indexed with env->priv. 187 * 188 * To avoid the complexity of calling this function, we assume that 189 * env->priv and env->virt_enabled contain old priv and old virt and 190 * new priv and new virt values are passed in as arguments. 191 */ 192 static void riscv_pmu_icount_update_priv(CPURISCVState *env, 193 target_ulong newpriv, bool new_virt) 194 { 195 uint64_t *snapshot_prev, *snapshot_new; 196 uint64_t current_icount; 197 uint64_t *counter_arr; 198 uint64_t delta; 199 200 if (icount_enabled()) { 201 current_icount = icount_get_raw(); 202 } else { 203 current_icount = cpu_get_host_ticks(); 204 } 205 206 if (env->virt_enabled) { 207 counter_arr = env->pmu_fixed_ctrs[1].counter_virt; 208 snapshot_prev = env->pmu_fixed_ctrs[1].counter_virt_prev; 209 } else { 210 counter_arr = env->pmu_fixed_ctrs[1].counter; 211 snapshot_prev = env->pmu_fixed_ctrs[1].counter_prev; 212 } 213 214 if (new_virt) { 215 snapshot_new = env->pmu_fixed_ctrs[1].counter_virt_prev; 216 } else { 217 snapshot_new = env->pmu_fixed_ctrs[1].counter_prev; 218 } 219 220 /* 221 * new_priv can be same as env->priv. So we need to calculate 222 * delta first before updating snapshot_new[new_priv]. 223 */ 224 delta = current_icount - snapshot_prev[env->priv]; 225 snapshot_new[newpriv] = current_icount; 226 227 counter_arr[env->priv] += delta; 228 } 229 230 static void riscv_pmu_cycle_update_priv(CPURISCVState *env, 231 target_ulong newpriv, bool new_virt) 232 { 233 uint64_t *snapshot_prev, *snapshot_new; 234 uint64_t current_ticks; 235 uint64_t *counter_arr; 236 uint64_t delta; 237 238 if (icount_enabled()) { 239 current_ticks = icount_get(); 240 } else { 241 current_ticks = cpu_get_host_ticks(); 242 } 243 244 if (env->virt_enabled) { 245 counter_arr = env->pmu_fixed_ctrs[0].counter_virt; 246 snapshot_prev = env->pmu_fixed_ctrs[0].counter_virt_prev; 247 } else { 248 counter_arr = env->pmu_fixed_ctrs[0].counter; 249 snapshot_prev = env->pmu_fixed_ctrs[0].counter_prev; 250 } 251 252 if (new_virt) { 253 snapshot_new = env->pmu_fixed_ctrs[0].counter_virt_prev; 254 } else { 255 snapshot_new = env->pmu_fixed_ctrs[0].counter_prev; 256 } 257 258 delta = current_ticks - snapshot_prev[env->priv]; 259 snapshot_new[newpriv] = current_ticks; 260 261 counter_arr[env->priv] += delta; 262 } 263 264 void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, 265 bool new_virt) 266 { 267 riscv_pmu_cycle_update_priv(env, newpriv, new_virt); 268 riscv_pmu_icount_update_priv(env, newpriv, new_virt); 269 } 270 271 int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) 272 { 273 uint32_t ctr_idx; 274 int ret; 275 CPURISCVState *env = &cpu->env; 276 gpointer value; 277 278 if (!cpu->cfg.pmu_mask) { 279 return 0; 280 } 281 value = g_hash_table_lookup(cpu->pmu_event_ctr_map, 282 GUINT_TO_POINTER(event_idx)); 283 if (!value) { 284 return -1; 285 } 286 287 ctr_idx = GPOINTER_TO_UINT(value); 288 if (!riscv_pmu_counter_enabled(cpu, ctr_idx) || 289 get_field(env->mcountinhibit, BIT(ctr_idx))) { 290 return -1; 291 } 292 293 if (riscv_cpu_mxl(env) == MXL_RV32) { 294 ret = riscv_pmu_incr_ctr_rv32(cpu, ctr_idx); 295 } else { 296 ret = riscv_pmu_incr_ctr_rv64(cpu, ctr_idx); 297 } 298 299 return ret; 300 } 301 302 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, 303 uint32_t target_ctr) 304 { 305 RISCVCPU *cpu; 306 uint32_t event_idx; 307 uint32_t ctr_idx; 308 309 /* Fixed instret counter */ 310 if (target_ctr == 2) { 311 return true; 312 } 313 314 cpu = env_archcpu(env); 315 if (!cpu->pmu_event_ctr_map) { 316 return false; 317 } 318 319 event_idx = RISCV_PMU_EVENT_HW_INSTRUCTIONS; 320 ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map, 321 GUINT_TO_POINTER(event_idx))); 322 if (!ctr_idx) { 323 return false; 324 } 325 326 return target_ctr == ctr_idx ? true : false; 327 } 328 329 bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr) 330 { 331 RISCVCPU *cpu; 332 uint32_t event_idx; 333 uint32_t ctr_idx; 334 335 /* Fixed mcycle counter */ 336 if (target_ctr == 0) { 337 return true; 338 } 339 340 cpu = env_archcpu(env); 341 if (!cpu->pmu_event_ctr_map) { 342 return false; 343 } 344 345 event_idx = RISCV_PMU_EVENT_HW_CPU_CYCLES; 346 ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map, 347 GUINT_TO_POINTER(event_idx))); 348 349 /* Counter zero is not used for event_ctr_map */ 350 if (!ctr_idx) { 351 return false; 352 } 353 354 return (target_ctr == ctr_idx) ? true : false; 355 } 356 357 static gboolean pmu_remove_event_map(gpointer key, gpointer value, 358 gpointer udata) 359 { 360 return (GPOINTER_TO_UINT(value) == GPOINTER_TO_UINT(udata)) ? true : false; 361 } 362 363 static int64_t pmu_icount_ticks_to_ns(int64_t value) 364 { 365 int64_t ret = 0; 366 367 if (icount_enabled()) { 368 ret = icount_to_ns(value); 369 } else { 370 ret = (NANOSECONDS_PER_SECOND / RISCV_TIMEBASE_FREQ) * value; 371 } 372 373 return ret; 374 } 375 376 int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, 377 uint32_t ctr_idx) 378 { 379 uint32_t event_idx; 380 RISCVCPU *cpu = env_archcpu(env); 381 382 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) { 383 return -1; 384 } 385 386 /* 387 * Expected mhpmevent value is zero for reset case. Remove the current 388 * mapping. 389 */ 390 if (!value) { 391 g_hash_table_foreach_remove(cpu->pmu_event_ctr_map, 392 pmu_remove_event_map, 393 GUINT_TO_POINTER(ctr_idx)); 394 return 0; 395 } 396 397 event_idx = value & MHPMEVENT_IDX_MASK; 398 if (g_hash_table_lookup(cpu->pmu_event_ctr_map, 399 GUINT_TO_POINTER(event_idx))) { 400 return 0; 401 } 402 403 switch (event_idx) { 404 case RISCV_PMU_EVENT_HW_CPU_CYCLES: 405 case RISCV_PMU_EVENT_HW_INSTRUCTIONS: 406 case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS: 407 case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS: 408 case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS: 409 break; 410 default: 411 /* We don't support any raw events right now */ 412 return -1; 413 } 414 g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx), 415 GUINT_TO_POINTER(ctr_idx)); 416 417 return 0; 418 } 419 420 static void pmu_timer_trigger_irq(RISCVCPU *cpu, 421 enum riscv_pmu_event_idx evt_idx) 422 { 423 uint32_t ctr_idx; 424 CPURISCVState *env = &cpu->env; 425 PMUCTRState *counter; 426 target_ulong *mhpmevent_val; 427 uint64_t of_bit_mask; 428 int64_t irq_trigger_at; 429 430 if (evt_idx != RISCV_PMU_EVENT_HW_CPU_CYCLES && 431 evt_idx != RISCV_PMU_EVENT_HW_INSTRUCTIONS) { 432 return; 433 } 434 435 ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map, 436 GUINT_TO_POINTER(evt_idx))); 437 if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) { 438 return; 439 } 440 441 if (riscv_cpu_mxl(env) == MXL_RV32) { 442 mhpmevent_val = &env->mhpmeventh_val[ctr_idx]; 443 of_bit_mask = MHPMEVENTH_BIT_OF; 444 } else { 445 mhpmevent_val = &env->mhpmevent_val[ctr_idx]; 446 of_bit_mask = MHPMEVENT_BIT_OF; 447 } 448 449 counter = &env->pmu_ctrs[ctr_idx]; 450 if (counter->irq_overflow_left > 0) { 451 irq_trigger_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 452 counter->irq_overflow_left; 453 timer_mod_anticipate_ns(cpu->pmu_timer, irq_trigger_at); 454 counter->irq_overflow_left = 0; 455 return; 456 } 457 458 if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) { 459 /* Generate interrupt only if OF bit is clear */ 460 if (!(*mhpmevent_val & of_bit_mask)) { 461 *mhpmevent_val |= of_bit_mask; 462 riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); 463 } 464 } 465 } 466 467 /* Timer callback for instret and cycle counter overflow */ 468 void riscv_pmu_timer_cb(void *priv) 469 { 470 RISCVCPU *cpu = priv; 471 472 /* Timer event was triggered only for these events */ 473 pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES); 474 pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS); 475 } 476 477 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) 478 { 479 uint64_t overflow_delta, overflow_at; 480 int64_t overflow_ns, overflow_left = 0; 481 RISCVCPU *cpu = env_archcpu(env); 482 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 483 484 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) { 485 return -1; 486 } 487 488 if (value) { 489 overflow_delta = UINT64_MAX - value + 1; 490 } else { 491 overflow_delta = UINT64_MAX; 492 } 493 494 /* 495 * QEMU supports only int64_t timers while RISC-V counters are uint64_t. 496 * Compute the leftover and save it so that it can be reprogrammed again 497 * when timer expires. 498 */ 499 if (overflow_delta > INT64_MAX) { 500 overflow_left = overflow_delta - INT64_MAX; 501 } 502 503 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 504 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 505 overflow_ns = pmu_icount_ticks_to_ns((int64_t)overflow_delta); 506 overflow_left = pmu_icount_ticks_to_ns(overflow_left) ; 507 } else { 508 return -1; 509 } 510 overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 511 overflow_ns; 512 513 if (overflow_at > INT64_MAX) { 514 overflow_left += overflow_at - INT64_MAX; 515 counter->irq_overflow_left = overflow_left; 516 overflow_at = INT64_MAX; 517 } 518 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); 519 520 return 0; 521 } 522 523 524 void riscv_pmu_init(RISCVCPU *cpu, Error **errp) 525 { 526 if (cpu->cfg.pmu_mask & (COUNTEREN_CY | COUNTEREN_TM | COUNTEREN_IR)) { 527 error_setg(errp, "\"pmu-mask\" contains invalid bits (0-2) set"); 528 return; 529 } 530 531 if (ctpop32(cpu->cfg.pmu_mask) > (RV_MAX_MHPMCOUNTERS - 3)) { 532 error_setg(errp, "Number of counters exceeds maximum available"); 533 return; 534 } 535 536 cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal); 537 if (!cpu->pmu_event_ctr_map) { 538 error_setg(errp, "Unable to allocate PMU event hash table"); 539 return; 540 } 541 542 cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask; 543 } 544