1 /* 2 * QEMU RISC-V PMP (Physical Memory Protection) 3 * 4 * Author: Daire McNamara, daire.mcnamara@emdalo.com 5 * Ivan Griffin, ivan.griffin@emdalo.com 6 * 7 * This provides a RISC-V Physical Memory Protection implementation 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2 or later, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/log.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "trace.h" 27 #include "exec/cputlb.h" 28 #include "exec/page-protection.h" 29 #include "exec/target_page.h" 30 31 static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, 32 uint8_t val); 33 static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index); 34 35 /* 36 * Convert the PMP permissions to match the truth table in the Smepmp spec. 37 */ 38 static inline uint8_t pmp_get_smepmp_operation(uint8_t cfg) 39 { 40 return ((cfg & PMP_LOCK) >> 4) | ((cfg & PMP_READ) << 2) | 41 (cfg & PMP_WRITE) | ((cfg & PMP_EXEC) >> 2); 42 } 43 44 /* 45 * Accessor method to extract address matching type 'a field' from cfg reg 46 */ 47 static inline uint8_t pmp_get_a_field(uint8_t cfg) 48 { 49 uint8_t a = cfg >> 3; 50 return a & 0x3; 51 } 52 53 /* 54 * Check whether a PMP is locked or not. 55 */ 56 static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index) 57 { 58 if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) { 59 return 1; 60 } 61 62 return 0; 63 } 64 65 /* 66 * Check whether a PMP is locked for writing or not. 67 * (i.e. has LOCK flag and mseccfg.RLB is unset) 68 */ 69 static int pmp_is_readonly(CPURISCVState *env, uint32_t pmp_index) 70 { 71 return pmp_is_locked(env, pmp_index) && !MSECCFG_RLB_ISSET(env); 72 } 73 74 /* 75 * Check whether `val` is an invalid Smepmp config value 76 */ 77 static int pmp_is_invalid_smepmp_cfg(CPURISCVState *env, uint8_t val) 78 { 79 /* No check if mseccfg.MML is not set or if mseccfg.RLB is set */ 80 if (!MSECCFG_MML_ISSET(env) || MSECCFG_RLB_ISSET(env)) { 81 return 0; 82 } 83 84 /* 85 * Adding a rule with executable privileges that either is M-mode-only 86 * or a locked Shared-Region is not possible 87 */ 88 switch (pmp_get_smepmp_operation(val)) { 89 case 0: 90 case 1: 91 case 2: 92 case 3: 93 case 4: 94 case 5: 95 case 6: 96 case 7: 97 case 8: 98 case 12: 99 case 14: 100 case 15: 101 return 0; 102 case 9: 103 case 10: 104 case 11: 105 case 13: 106 return 1; 107 default: 108 g_assert_not_reached(); 109 } 110 } 111 112 /* 113 * Count the number of active rules. 114 */ 115 uint32_t pmp_get_num_rules(CPURISCVState *env) 116 { 117 return env->pmp_state.num_rules; 118 } 119 120 /* 121 * Accessor to get the cfg reg for a specific PMP/HART 122 */ 123 static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index) 124 { 125 uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions; 126 127 if (pmp_index < pmp_regions) { 128 return env->pmp_state.pmp[pmp_index].cfg_reg; 129 } 130 131 return 0; 132 } 133 134 135 /* 136 * Accessor to set the cfg reg for a specific PMP/HART 137 * Bounds checks and relevant lock bit. 138 */ 139 static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) 140 { 141 uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions; 142 143 if (pmp_index < pmp_regions) { 144 if (env->pmp_state.pmp[pmp_index].cfg_reg == val) { 145 /* no change */ 146 return false; 147 } 148 149 if (pmp_is_readonly(env, pmp_index)) { 150 qemu_log_mask(LOG_GUEST_ERROR, 151 "ignoring pmpcfg write - read only\n"); 152 } else if (pmp_is_invalid_smepmp_cfg(env, val)) { 153 qemu_log_mask(LOG_GUEST_ERROR, 154 "ignoring pmpcfg write - invalid\n"); 155 } else { 156 env->pmp_state.pmp[pmp_index].cfg_reg = val; 157 pmp_update_rule_addr(env, pmp_index); 158 return true; 159 } 160 } else { 161 qemu_log_mask(LOG_GUEST_ERROR, 162 "ignoring pmpcfg write - out of bounds\n"); 163 } 164 165 return false; 166 } 167 168 void pmp_unlock_entries(CPURISCVState *env) 169 { 170 uint32_t pmp_num = pmp_get_num_rules(env); 171 int i; 172 173 for (i = 0; i < pmp_num; i++) { 174 env->pmp_state.pmp[i].cfg_reg &= ~(PMP_LOCK | PMP_AMATCH); 175 } 176 } 177 178 static void pmp_decode_napot(hwaddr a, hwaddr *sa, hwaddr *ea) 179 { 180 /* 181 * aaaa...aaa0 8-byte NAPOT range 182 * aaaa...aa01 16-byte NAPOT range 183 * aaaa...a011 32-byte NAPOT range 184 * ... 185 * aa01...1111 2^XLEN-byte NAPOT range 186 * a011...1111 2^(XLEN+1)-byte NAPOT range 187 * 0111...1111 2^(XLEN+2)-byte NAPOT range 188 * 1111...1111 Reserved 189 */ 190 a = (a << 2) | 0x3; 191 *sa = a & (a + 1); 192 *ea = a | (a + 1); 193 } 194 195 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) 196 { 197 uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg; 198 target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg; 199 target_ulong prev_addr = 0u; 200 hwaddr sa = 0u; 201 hwaddr ea = 0u; 202 203 if (pmp_index >= 1u) { 204 prev_addr = env->pmp_state.pmp[pmp_index - 1].addr_reg; 205 } 206 207 switch (pmp_get_a_field(this_cfg)) { 208 case PMP_AMATCH_OFF: 209 sa = 0u; 210 ea = -1; 211 break; 212 213 case PMP_AMATCH_TOR: 214 sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ 215 ea = (this_addr << 2) - 1u; 216 if (sa > ea) { 217 sa = ea = 0u; 218 } 219 break; 220 221 case PMP_AMATCH_NA4: 222 sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ 223 ea = (sa + 4u) - 1u; 224 break; 225 226 case PMP_AMATCH_NAPOT: 227 pmp_decode_napot(this_addr, &sa, &ea); 228 break; 229 230 default: 231 sa = 0u; 232 ea = 0u; 233 break; 234 } 235 236 env->pmp_state.addr[pmp_index].sa = sa; 237 env->pmp_state.addr[pmp_index].ea = ea; 238 } 239 240 void pmp_update_rule_nums(CPURISCVState *env) 241 { 242 int i; 243 uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions; 244 245 env->pmp_state.num_rules = 0; 246 for (i = 0; i < pmp_regions; i++) { 247 const uint8_t a_field = 248 pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); 249 if (PMP_AMATCH_OFF != a_field) { 250 env->pmp_state.num_rules++; 251 } 252 } 253 } 254 255 static int pmp_is_in_range(CPURISCVState *env, int pmp_index, hwaddr addr) 256 { 257 int result = 0; 258 259 if ((addr >= env->pmp_state.addr[pmp_index].sa) && 260 (addr <= env->pmp_state.addr[pmp_index].ea)) { 261 result = 1; 262 } else { 263 result = 0; 264 } 265 266 return result; 267 } 268 269 /* 270 * Check if the address has required RWX privs when no PMP entry is matched. 271 */ 272 static bool pmp_hart_has_privs_default(CPURISCVState *env, pmp_priv_t privs, 273 pmp_priv_t *allowed_privs, 274 target_ulong mode) 275 { 276 bool ret; 277 278 if (MSECCFG_MMWP_ISSET(env)) { 279 /* 280 * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set 281 * so we default to deny all, even for M-mode. 282 */ 283 *allowed_privs = 0; 284 return false; 285 } else if (MSECCFG_MML_ISSET(env)) { 286 /* 287 * The Machine Mode Lockdown (mseccfg.MML) bit is set 288 * so we can only execute code in M-mode with an applicable 289 * rule. Other modes are disabled. 290 */ 291 if (mode == PRV_M && !(privs & PMP_EXEC)) { 292 ret = true; 293 *allowed_privs = PMP_READ | PMP_WRITE; 294 } else { 295 ret = false; 296 *allowed_privs = 0; 297 } 298 299 return ret; 300 } 301 302 if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) { 303 /* 304 * Privileged spec v1.10 states if HW doesn't implement any PMP entry 305 * or no PMP entry matches an M-Mode access, the access succeeds. 306 */ 307 ret = true; 308 *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; 309 } else { 310 /* 311 * Other modes are not allowed to succeed if they don't * match a rule, 312 * but there are rules. We've checked for no rule earlier in this 313 * function. 314 */ 315 ret = false; 316 *allowed_privs = 0; 317 } 318 319 return ret; 320 } 321 322 323 /* 324 * Public Interface 325 */ 326 327 /* 328 * Check if the address has required RWX privs to complete desired operation 329 * Return true if a pmp rule match or default match 330 * Return false if no match 331 */ 332 bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, 333 target_ulong size, pmp_priv_t privs, 334 pmp_priv_t *allowed_privs, target_ulong mode) 335 { 336 int i = 0; 337 int pmp_size = 0; 338 hwaddr s = 0; 339 hwaddr e = 0; 340 uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions; 341 342 /* Short cut if no rules */ 343 if (0 == pmp_get_num_rules(env)) { 344 return pmp_hart_has_privs_default(env, privs, allowed_privs, mode); 345 } 346 347 if (size == 0) { 348 if (riscv_cpu_cfg(env)->mmu) { 349 /* 350 * If size is unknown (0), assume that all bytes 351 * from addr to the end of the page will be accessed. 352 */ 353 pmp_size = -(addr | TARGET_PAGE_MASK); 354 } else { 355 pmp_size = 2 << riscv_cpu_mxl(env); 356 } 357 } else { 358 pmp_size = size; 359 } 360 361 /* 362 * 1.10 draft priv spec states there is an implicit order 363 * from low to high 364 */ 365 for (i = 0; i < pmp_regions; i++) { 366 s = pmp_is_in_range(env, i, addr); 367 e = pmp_is_in_range(env, i, addr + pmp_size - 1); 368 369 /* partially inside */ 370 if ((s + e) == 1) { 371 qemu_log_mask(LOG_GUEST_ERROR, 372 "pmp violation - access is partially inside\n"); 373 *allowed_privs = 0; 374 return false; 375 } 376 377 /* fully inside */ 378 const uint8_t a_field = 379 pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); 380 381 if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) { 382 /* 383 * If the PMP entry is not off and the address is in range, 384 * do the priv check 385 */ 386 if (!MSECCFG_MML_ISSET(env)) { 387 /* 388 * If mseccfg.MML Bit is not set, do pmp priv check 389 * This will always apply to regular PMP. 390 */ 391 *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; 392 if ((mode != PRV_M) || pmp_is_locked(env, i)) { 393 *allowed_privs &= env->pmp_state.pmp[i].cfg_reg; 394 } 395 } else { 396 /* 397 * If mseccfg.MML Bit set, do the enhanced pmp priv check 398 */ 399 const uint8_t smepmp_operation = 400 pmp_get_smepmp_operation(env->pmp_state.pmp[i].cfg_reg); 401 402 if (mode == PRV_M) { 403 switch (smepmp_operation) { 404 case 0: 405 case 1: 406 case 4: 407 case 5: 408 case 6: 409 case 7: 410 case 8: 411 *allowed_privs = 0; 412 break; 413 case 2: 414 case 3: 415 case 14: 416 *allowed_privs = PMP_READ | PMP_WRITE; 417 break; 418 case 9: 419 case 10: 420 *allowed_privs = PMP_EXEC; 421 break; 422 case 11: 423 case 13: 424 *allowed_privs = PMP_READ | PMP_EXEC; 425 break; 426 case 12: 427 case 15: 428 *allowed_privs = PMP_READ; 429 break; 430 default: 431 g_assert_not_reached(); 432 } 433 } else { 434 switch (smepmp_operation) { 435 case 0: 436 case 8: 437 case 9: 438 case 12: 439 case 13: 440 case 14: 441 *allowed_privs = 0; 442 break; 443 case 1: 444 case 10: 445 case 11: 446 *allowed_privs = PMP_EXEC; 447 break; 448 case 2: 449 case 4: 450 case 15: 451 *allowed_privs = PMP_READ; 452 break; 453 case 3: 454 case 6: 455 *allowed_privs = PMP_READ | PMP_WRITE; 456 break; 457 case 5: 458 *allowed_privs = PMP_READ | PMP_EXEC; 459 break; 460 case 7: 461 *allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; 462 break; 463 default: 464 g_assert_not_reached(); 465 } 466 } 467 } 468 469 /* 470 * If matching address range was found, the protection bits 471 * defined with PMP must be used. We shouldn't fallback on 472 * finding default privileges. 473 */ 474 return (privs & *allowed_privs) == privs; 475 } 476 } 477 478 /* No rule matched */ 479 return pmp_hart_has_privs_default(env, privs, allowed_privs, mode); 480 } 481 482 /* 483 * Handle a write to a pmpcfg CSR 484 */ 485 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, 486 target_ulong val) 487 { 488 int i; 489 uint8_t cfg_val; 490 int pmpcfg_nums = 2 << riscv_cpu_mxl(env); 491 bool modified = false; 492 493 trace_pmpcfg_csr_write(env->mhartid, reg_index, val); 494 495 for (i = 0; i < pmpcfg_nums; i++) { 496 cfg_val = (val >> 8 * i) & 0xff; 497 modified |= pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); 498 } 499 500 /* If PMP permission of any addr has been changed, flush TLB pages. */ 501 if (modified) { 502 pmp_update_rule_nums(env); 503 tlb_flush(env_cpu(env)); 504 } 505 } 506 507 508 /* 509 * Handle a read from a pmpcfg CSR 510 */ 511 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) 512 { 513 int i; 514 target_ulong cfg_val = 0; 515 target_ulong val = 0; 516 int pmpcfg_nums = 2 << riscv_cpu_mxl(env); 517 518 for (i = 0; i < pmpcfg_nums; i++) { 519 val = pmp_read_cfg(env, (reg_index * 4) + i); 520 cfg_val |= (val << (i * 8)); 521 } 522 trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val); 523 524 return cfg_val; 525 } 526 527 528 /* 529 * Handle a write to a pmpaddr CSR 530 */ 531 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, 532 target_ulong val) 533 { 534 trace_pmpaddr_csr_write(env->mhartid, addr_index, val); 535 bool is_next_cfg_tor = false; 536 uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions; 537 538 if (addr_index < pmp_regions) { 539 if (env->pmp_state.pmp[addr_index].addr_reg == val) { 540 /* no change */ 541 return; 542 } 543 544 /* 545 * In TOR mode, need to check the lock bit of the next pmp 546 * (if there is a next). 547 */ 548 if (addr_index + 1 < pmp_regions) { 549 uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg; 550 is_next_cfg_tor = PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg); 551 552 if (pmp_is_readonly(env, addr_index + 1) && is_next_cfg_tor) { 553 qemu_log_mask(LOG_GUEST_ERROR, 554 "ignoring pmpaddr write - pmpcfg+1 read only\n"); 555 return; 556 } 557 } 558 559 if (!pmp_is_readonly(env, addr_index)) { 560 env->pmp_state.pmp[addr_index].addr_reg = val; 561 pmp_update_rule_addr(env, addr_index); 562 if (is_next_cfg_tor) { 563 pmp_update_rule_addr(env, addr_index + 1); 564 } 565 tlb_flush(env_cpu(env)); 566 } else { 567 qemu_log_mask(LOG_GUEST_ERROR, 568 "ignoring pmpaddr write - read only\n"); 569 } 570 } else { 571 qemu_log_mask(LOG_GUEST_ERROR, 572 "ignoring pmpaddr write - out of bounds\n"); 573 } 574 } 575 576 577 /* 578 * Handle a read from a pmpaddr CSR 579 */ 580 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) 581 { 582 target_ulong val = 0; 583 uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions; 584 585 if (addr_index < pmp_regions) { 586 val = env->pmp_state.pmp[addr_index].addr_reg; 587 trace_pmpaddr_csr_read(env->mhartid, addr_index, val); 588 } else { 589 qemu_log_mask(LOG_GUEST_ERROR, 590 "ignoring pmpaddr read - out of bounds\n"); 591 } 592 593 return val; 594 } 595 596 /* 597 * Handle a write to a mseccfg CSR 598 */ 599 void mseccfg_csr_write(CPURISCVState *env, target_ulong val) 600 { 601 int i; 602 uint64_t mask = MSECCFG_MMWP | MSECCFG_MML; 603 uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions; 604 /* Update PMM field only if the value is valid according to Zjpm v1.0 */ 605 if (riscv_cpu_cfg(env)->ext_smmpm && 606 riscv_cpu_mxl(env) == MXL_RV64 && 607 get_field(val, MSECCFG_PMM) != PMM_FIELD_RESERVED) { 608 mask |= MSECCFG_PMM; 609 } 610 611 trace_mseccfg_csr_write(env->mhartid, val); 612 613 /* RLB cannot be enabled if it's already 0 and if any regions are locked */ 614 if (!MSECCFG_RLB_ISSET(env)) { 615 for (i = 0; i < pmp_regions; i++) { 616 if (pmp_is_locked(env, i)) { 617 val &= ~MSECCFG_RLB; 618 break; 619 } 620 } 621 } 622 623 if (riscv_cpu_cfg(env)->ext_smepmp) { 624 /* Sticky bits */ 625 val |= (env->mseccfg & mask); 626 if ((val ^ env->mseccfg) & mask) { 627 tlb_flush(env_cpu(env)); 628 } 629 } else { 630 mask |= MSECCFG_RLB; 631 val &= ~(mask); 632 } 633 634 /* M-mode forward cfi to be enabled if cfi extension is implemented */ 635 if (env_archcpu(env)->cfg.ext_zicfilp) { 636 val |= (val & MSECCFG_MLPE); 637 } 638 639 env->mseccfg = val; 640 } 641 642 /* 643 * Handle a read from a mseccfg CSR 644 */ 645 target_ulong mseccfg_csr_read(CPURISCVState *env) 646 { 647 trace_mseccfg_csr_read(env->mhartid, env->mseccfg); 648 return env->mseccfg; 649 } 650 651 /* 652 * Calculate the TLB size. 653 * It's possible that PMP regions only cover partial of the TLB page, and 654 * this may split the page into regions with different permissions. 655 * For example if PMP0 is (0x80000008~0x8000000F, R) and PMP1 is (0x80000000 656 * ~0x80000FFF, RWX), then region 0x80000008~0x8000000F has R permission, and 657 * the other regions in this page have RWX permissions. 658 * A write access to 0x80000000 will match PMP1. However we cannot cache the 659 * translation result in the TLB since this will make the write access to 660 * 0x80000008 bypass the check of PMP0. 661 * To avoid this we return a size of 1 (which means no caching) if the PMP 662 * region only covers partial of the TLB page. 663 */ 664 target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr) 665 { 666 hwaddr pmp_sa; 667 hwaddr pmp_ea; 668 hwaddr tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1); 669 hwaddr tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1; 670 int i; 671 uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions; 672 673 /* 674 * If PMP is not supported or there are no PMP rules, the TLB page will not 675 * be split into regions with different permissions by PMP so we set the 676 * size to TARGET_PAGE_SIZE. 677 */ 678 if (!riscv_cpu_cfg(env)->pmp || !pmp_get_num_rules(env)) { 679 return TARGET_PAGE_SIZE; 680 } 681 682 for (i = 0; i < pmp_regions; i++) { 683 if (pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg) == PMP_AMATCH_OFF) { 684 continue; 685 } 686 687 pmp_sa = env->pmp_state.addr[i].sa; 688 pmp_ea = env->pmp_state.addr[i].ea; 689 690 /* 691 * Only the first PMP entry that covers (whole or partial of) the TLB 692 * page really matters: 693 * If it covers the whole TLB page, set the size to TARGET_PAGE_SIZE, 694 * since the following PMP entries have lower priority and will not 695 * affect the permissions of the page. 696 * If it only covers partial of the TLB page, set the size to 1 since 697 * the allowed permissions of the region may be different from other 698 * region of the page. 699 */ 700 if (pmp_sa <= tlb_sa && pmp_ea >= tlb_ea) { 701 return TARGET_PAGE_SIZE; 702 } else if ((pmp_sa >= tlb_sa && pmp_sa <= tlb_ea) || 703 (pmp_ea >= tlb_sa && pmp_ea <= tlb_ea)) { 704 return 1; 705 } 706 } 707 708 /* 709 * If no PMP entry matches the TLB page, the TLB page will also not be 710 * split into regions with different permissions by PMP so we set the size 711 * to TARGET_PAGE_SIZE. 712 */ 713 return TARGET_PAGE_SIZE; 714 } 715 716 /* 717 * Convert PMP privilege to TLB page privilege. 718 */ 719 int pmp_priv_to_page_prot(pmp_priv_t pmp_priv) 720 { 721 int prot = 0; 722 723 if (pmp_priv & PMP_READ) { 724 prot |= PAGE_READ; 725 } 726 if (pmp_priv & PMP_WRITE) { 727 prot |= PAGE_WRITE; 728 } 729 if (pmp_priv & PMP_EXEC) { 730 prot |= PAGE_EXEC; 731 } 732 733 return prot; 734 } 735