1 /* 2 * RISC-V Emulation Helpers for QEMU. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 #include "exec/helper-proto.h" 26 27 /* Exceptions processing helpers */ 28 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 29 uint32_t exception, uintptr_t pc) 30 { 31 CPUState *cs = env_cpu(env); 32 cs->exception_index = exception; 33 cpu_loop_exit_restore(cs, pc); 34 } 35 36 void helper_raise_exception(CPURISCVState *env, uint32_t exception) 37 { 38 riscv_raise_exception(env, exception, 0); 39 } 40 41 target_ulong helper_csrrw(CPURISCVState *env, target_ulong src, 42 target_ulong csr) 43 { 44 target_ulong val = 0; 45 int ret = riscv_csrrw(env, csr, &val, src, -1); 46 47 if (ret < 0) { 48 riscv_raise_exception(env, -ret, GETPC()); 49 } 50 return val; 51 } 52 53 target_ulong helper_csrrs(CPURISCVState *env, target_ulong src, 54 target_ulong csr, target_ulong rs1_pass) 55 { 56 target_ulong val = 0; 57 int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0); 58 59 if (ret < 0) { 60 riscv_raise_exception(env, -ret, GETPC()); 61 } 62 return val; 63 } 64 65 target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, 66 target_ulong csr, target_ulong rs1_pass) 67 { 68 target_ulong val = 0; 69 int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0); 70 71 if (ret < 0) { 72 riscv_raise_exception(env, -ret, GETPC()); 73 } 74 return val; 75 } 76 77 #ifndef CONFIG_USER_ONLY 78 79 target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) 80 { 81 uint64_t mstatus; 82 target_ulong prev_priv, prev_virt; 83 84 if (!(env->priv >= PRV_S)) { 85 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); 86 } 87 88 target_ulong retpc = env->sepc; 89 if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { 90 riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); 91 } 92 93 if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { 94 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); 95 } 96 97 if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && 98 get_field(env->hstatus, HSTATUS_VTSR)) { 99 riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); 100 } 101 102 mstatus = env->mstatus; 103 104 if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { 105 /* We support Hypervisor extensions and virtulisation is disabled */ 106 target_ulong hstatus = env->hstatus; 107 108 prev_priv = get_field(mstatus, MSTATUS_SPP); 109 prev_virt = get_field(hstatus, HSTATUS_SPV); 110 111 hstatus = set_field(hstatus, HSTATUS_SPV, 0); 112 mstatus = set_field(mstatus, MSTATUS_SPP, 0); 113 mstatus = set_field(mstatus, SSTATUS_SIE, 114 get_field(mstatus, SSTATUS_SPIE)); 115 mstatus = set_field(mstatus, SSTATUS_SPIE, 1); 116 117 env->mstatus = mstatus; 118 env->hstatus = hstatus; 119 120 if (prev_virt) { 121 riscv_cpu_swap_hypervisor_regs(env); 122 } 123 124 riscv_cpu_set_virt_enabled(env, prev_virt); 125 } else { 126 prev_priv = get_field(mstatus, MSTATUS_SPP); 127 128 mstatus = set_field(mstatus, MSTATUS_SIE, 129 get_field(mstatus, MSTATUS_SPIE)); 130 mstatus = set_field(mstatus, MSTATUS_SPIE, 1); 131 mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); 132 env->mstatus = mstatus; 133 } 134 135 riscv_cpu_set_mode(env, prev_priv); 136 137 return retpc; 138 } 139 140 target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) 141 { 142 if (!(env->priv >= PRV_M)) { 143 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); 144 } 145 146 target_ulong retpc = env->mepc; 147 if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { 148 riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); 149 } 150 151 uint64_t mstatus = env->mstatus; 152 target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); 153 target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV); 154 mstatus = set_field(mstatus, MSTATUS_MIE, 155 get_field(mstatus, MSTATUS_MPIE)); 156 mstatus = set_field(mstatus, MSTATUS_MPIE, 1); 157 mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); 158 mstatus = set_field(mstatus, MSTATUS_MPV, 0); 159 env->mstatus = mstatus; 160 riscv_cpu_set_mode(env, prev_priv); 161 162 if (riscv_has_ext(env, RVH)) { 163 if (prev_virt) { 164 riscv_cpu_swap_hypervisor_regs(env); 165 } 166 167 riscv_cpu_set_virt_enabled(env, prev_virt); 168 } 169 170 return retpc; 171 } 172 173 void helper_wfi(CPURISCVState *env) 174 { 175 CPUState *cs = env_cpu(env); 176 177 if ((env->priv == PRV_S && 178 get_field(env->mstatus, MSTATUS_TW)) || 179 riscv_cpu_virt_enabled(env)) { 180 riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); 181 } else { 182 cs->halted = 1; 183 cs->exception_index = EXCP_HLT; 184 cpu_loop_exit(cs); 185 } 186 } 187 188 void helper_tlb_flush(CPURISCVState *env) 189 { 190 CPUState *cs = env_cpu(env); 191 if (!(env->priv >= PRV_S) || 192 (env->priv == PRV_S && 193 get_field(env->mstatus, MSTATUS_TVM))) { 194 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); 195 } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && 196 get_field(env->hstatus, HSTATUS_VTVM)) { 197 riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); 198 } else { 199 tlb_flush(cs); 200 } 201 } 202 203 void helper_hyp_tlb_flush(CPURISCVState *env) 204 { 205 CPUState *cs = env_cpu(env); 206 207 if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) { 208 riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); 209 } 210 211 if (env->priv == PRV_M || 212 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) { 213 tlb_flush(cs); 214 return; 215 } 216 217 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); 218 } 219 220 void helper_hyp_gvma_tlb_flush(CPURISCVState *env) 221 { 222 if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) && 223 get_field(env->mstatus, MSTATUS_TVM)) { 224 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); 225 } 226 227 helper_hyp_tlb_flush(env); 228 } 229 230 target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, 231 target_ulong attrs, target_ulong memop) 232 { 233 if (env->priv == PRV_M || 234 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 235 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 236 get_field(env->hstatus, HSTATUS_HU))) { 237 target_ulong pte; 238 int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK; 239 240 riscv_cpu_set_two_stage_lookup(env, true); 241 242 switch (memop) { 243 case MO_SB: 244 pte = cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); 245 break; 246 case MO_UB: 247 pte = cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC()); 248 break; 249 case MO_TESW: 250 pte = cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC()); 251 break; 252 case MO_TEUW: 253 pte = cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); 254 break; 255 case MO_TESL: 256 pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); 257 break; 258 case MO_TEUL: 259 pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); 260 break; 261 case MO_TEQ: 262 pte = cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC()); 263 break; 264 default: 265 g_assert_not_reached(); 266 } 267 268 riscv_cpu_set_two_stage_lookup(env, false); 269 270 return pte; 271 } 272 273 if (riscv_cpu_virt_enabled(env)) { 274 riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); 275 } else { 276 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); 277 } 278 return 0; 279 } 280 281 void helper_hyp_store(CPURISCVState *env, target_ulong address, 282 target_ulong val, target_ulong attrs, target_ulong memop) 283 { 284 if (env->priv == PRV_M || 285 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 286 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 287 get_field(env->hstatus, HSTATUS_HU))) { 288 int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK; 289 290 riscv_cpu_set_two_stage_lookup(env, true); 291 292 switch (memop) { 293 case MO_SB: 294 case MO_UB: 295 cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC()); 296 break; 297 case MO_TESW: 298 case MO_TEUW: 299 cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC()); 300 break; 301 case MO_TESL: 302 case MO_TEUL: 303 cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC()); 304 break; 305 case MO_TEQ: 306 cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC()); 307 break; 308 default: 309 g_assert_not_reached(); 310 } 311 312 riscv_cpu_set_two_stage_lookup(env, false); 313 314 return; 315 } 316 317 if (riscv_cpu_virt_enabled(env)) { 318 riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); 319 } else { 320 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); 321 } 322 } 323 324 target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, 325 target_ulong attrs, target_ulong memop) 326 { 327 if (env->priv == PRV_M || 328 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 329 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 330 get_field(env->hstatus, HSTATUS_HU))) { 331 target_ulong pte; 332 int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK; 333 334 riscv_cpu_set_two_stage_lookup(env, true); 335 336 switch (memop) { 337 case MO_TEUW: 338 pte = cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); 339 break; 340 case MO_TEUL: 341 pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); 342 break; 343 default: 344 g_assert_not_reached(); 345 } 346 347 riscv_cpu_set_two_stage_lookup(env, false); 348 349 return pte; 350 } 351 352 if (riscv_cpu_virt_enabled(env)) { 353 riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); 354 } else { 355 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); 356 } 357 return 0; 358 } 359 360 #endif /* !CONFIG_USER_ONLY */ 361