xref: /openbmc/qemu/target/riscv/machine.c (revision f7697f0e)
1 /*
2  * RISC-V VMState Description
3  *
4  * Copyright (c) 2020 Huawei Technologies Co., Ltd
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "qemu/error-report.h"
22 #include "sysemu/kvm.h"
23 #include "migration/cpu.h"
24 
25 const VMStateDescription vmstate_riscv_cpu = {
26     .name = "cpu",
27     .version_id = 1,
28     .minimum_version_id = 1,
29     .fields = (VMStateField[]) {
30         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
31         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
32         VMSTATE_UINTTL(env.pc, RISCVCPU),
33         VMSTATE_UINTTL(env.load_res, RISCVCPU),
34         VMSTATE_UINTTL(env.load_val, RISCVCPU),
35         VMSTATE_UINTTL(env.frm, RISCVCPU),
36         VMSTATE_UINTTL(env.badaddr, RISCVCPU),
37         VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
38         VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
39         VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
40         VMSTATE_UINTTL(env.misa, RISCVCPU),
41         VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
42         VMSTATE_UINT32(env.features, RISCVCPU),
43         VMSTATE_UINTTL(env.priv, RISCVCPU),
44         VMSTATE_UINTTL(env.virt, RISCVCPU),
45         VMSTATE_UINTTL(env.resetvec, RISCVCPU),
46         VMSTATE_UINTTL(env.mhartid, RISCVCPU),
47         VMSTATE_UINT64(env.mstatus, RISCVCPU),
48         VMSTATE_UINTTL(env.mip, RISCVCPU),
49         VMSTATE_UINT32(env.miclaim, RISCVCPU),
50         VMSTATE_UINTTL(env.mie, RISCVCPU),
51         VMSTATE_UINTTL(env.mideleg, RISCVCPU),
52         VMSTATE_UINTTL(env.sptbr, RISCVCPU),
53         VMSTATE_UINTTL(env.satp, RISCVCPU),
54         VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
55         VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
56         VMSTATE_UINTTL(env.medeleg, RISCVCPU),
57         VMSTATE_UINTTL(env.stvec, RISCVCPU),
58         VMSTATE_UINTTL(env.sepc, RISCVCPU),
59         VMSTATE_UINTTL(env.scause, RISCVCPU),
60         VMSTATE_UINTTL(env.mtvec, RISCVCPU),
61         VMSTATE_UINTTL(env.mepc, RISCVCPU),
62         VMSTATE_UINTTL(env.mcause, RISCVCPU),
63         VMSTATE_UINTTL(env.mtval, RISCVCPU),
64         VMSTATE_UINTTL(env.scounteren, RISCVCPU),
65         VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
66         VMSTATE_UINTTL(env.sscratch, RISCVCPU),
67         VMSTATE_UINTTL(env.mscratch, RISCVCPU),
68         VMSTATE_UINT64(env.mfromhost, RISCVCPU),
69         VMSTATE_UINT64(env.mtohost, RISCVCPU),
70         VMSTATE_UINT64(env.timecmp, RISCVCPU),
71 
72         VMSTATE_END_OF_LIST()
73     }
74 };
75