1 /* 2 * RISC-V VMState Description 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "qemu/error-report.h" 22 #include "sysemu/kvm.h" 23 #include "migration/cpu.h" 24 25 static bool pmp_needed(void *opaque) 26 { 27 RISCVCPU *cpu = opaque; 28 CPURISCVState *env = &cpu->env; 29 30 return riscv_feature(env, RISCV_FEATURE_PMP); 31 } 32 33 static int pmp_post_load(void *opaque, int version_id) 34 { 35 RISCVCPU *cpu = opaque; 36 CPURISCVState *env = &cpu->env; 37 int i; 38 39 for (i = 0; i < MAX_RISCV_PMPS; i++) { 40 pmp_update_rule_addr(env, i); 41 } 42 pmp_update_rule_nums(env); 43 44 return 0; 45 } 46 47 static const VMStateDescription vmstate_pmp_entry = { 48 .name = "cpu/pmp/entry", 49 .version_id = 1, 50 .minimum_version_id = 1, 51 .fields = (VMStateField[]) { 52 VMSTATE_UINTTL(addr_reg, pmp_entry_t), 53 VMSTATE_UINT8(cfg_reg, pmp_entry_t), 54 VMSTATE_END_OF_LIST() 55 } 56 }; 57 58 static const VMStateDescription vmstate_pmp = { 59 .name = "cpu/pmp", 60 .version_id = 1, 61 .minimum_version_id = 1, 62 .needed = pmp_needed, 63 .post_load = pmp_post_load, 64 .fields = (VMStateField[]) { 65 VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS, 66 0, vmstate_pmp_entry, pmp_entry_t), 67 VMSTATE_END_OF_LIST() 68 } 69 }; 70 71 static bool hyper_needed(void *opaque) 72 { 73 RISCVCPU *cpu = opaque; 74 CPURISCVState *env = &cpu->env; 75 76 return riscv_has_ext(env, RVH); 77 } 78 79 static const VMStateDescription vmstate_hyper = { 80 .name = "cpu/hyper", 81 .version_id = 2, 82 .minimum_version_id = 2, 83 .needed = hyper_needed, 84 .fields = (VMStateField[]) { 85 VMSTATE_UINTTL(env.hstatus, RISCVCPU), 86 VMSTATE_UINTTL(env.hedeleg, RISCVCPU), 87 VMSTATE_UINT64(env.hideleg, RISCVCPU), 88 VMSTATE_UINTTL(env.hcounteren, RISCVCPU), 89 VMSTATE_UINTTL(env.htval, RISCVCPU), 90 VMSTATE_UINTTL(env.htinst, RISCVCPU), 91 VMSTATE_UINTTL(env.hgatp, RISCVCPU), 92 VMSTATE_UINTTL(env.hgeie, RISCVCPU), 93 VMSTATE_UINTTL(env.hgeip, RISCVCPU), 94 VMSTATE_UINT64(env.htimedelta, RISCVCPU), 95 VMSTATE_UINT64(env.vstimecmp, RISCVCPU), 96 97 VMSTATE_UINTTL(env.hvictl, RISCVCPU), 98 VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), 99 100 VMSTATE_UINT64(env.vsstatus, RISCVCPU), 101 VMSTATE_UINTTL(env.vstvec, RISCVCPU), 102 VMSTATE_UINTTL(env.vsscratch, RISCVCPU), 103 VMSTATE_UINTTL(env.vsepc, RISCVCPU), 104 VMSTATE_UINTTL(env.vscause, RISCVCPU), 105 VMSTATE_UINTTL(env.vstval, RISCVCPU), 106 VMSTATE_UINTTL(env.vsatp, RISCVCPU), 107 VMSTATE_UINTTL(env.vsiselect, RISCVCPU), 108 109 VMSTATE_UINTTL(env.mtval2, RISCVCPU), 110 VMSTATE_UINTTL(env.mtinst, RISCVCPU), 111 112 VMSTATE_UINTTL(env.stvec_hs, RISCVCPU), 113 VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU), 114 VMSTATE_UINTTL(env.sepc_hs, RISCVCPU), 115 VMSTATE_UINTTL(env.scause_hs, RISCVCPU), 116 VMSTATE_UINTTL(env.stval_hs, RISCVCPU), 117 VMSTATE_UINTTL(env.satp_hs, RISCVCPU), 118 VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), 119 120 VMSTATE_END_OF_LIST() 121 } 122 }; 123 124 static bool vector_needed(void *opaque) 125 { 126 RISCVCPU *cpu = opaque; 127 CPURISCVState *env = &cpu->env; 128 129 return riscv_has_ext(env, RVV); 130 } 131 132 static const VMStateDescription vmstate_vector = { 133 .name = "cpu/vector", 134 .version_id = 2, 135 .minimum_version_id = 2, 136 .needed = vector_needed, 137 .fields = (VMStateField[]) { 138 VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), 139 VMSTATE_UINTTL(env.vxrm, RISCVCPU), 140 VMSTATE_UINTTL(env.vxsat, RISCVCPU), 141 VMSTATE_UINTTL(env.vl, RISCVCPU), 142 VMSTATE_UINTTL(env.vstart, RISCVCPU), 143 VMSTATE_UINTTL(env.vtype, RISCVCPU), 144 VMSTATE_BOOL(env.vill, RISCVCPU), 145 VMSTATE_END_OF_LIST() 146 } 147 }; 148 149 static bool pointermasking_needed(void *opaque) 150 { 151 RISCVCPU *cpu = opaque; 152 CPURISCVState *env = &cpu->env; 153 154 return riscv_has_ext(env, RVJ); 155 } 156 157 static const VMStateDescription vmstate_pointermasking = { 158 .name = "cpu/pointer_masking", 159 .version_id = 1, 160 .minimum_version_id = 1, 161 .needed = pointermasking_needed, 162 .fields = (VMStateField[]) { 163 VMSTATE_UINTTL(env.mmte, RISCVCPU), 164 VMSTATE_UINTTL(env.mpmmask, RISCVCPU), 165 VMSTATE_UINTTL(env.mpmbase, RISCVCPU), 166 VMSTATE_UINTTL(env.spmmask, RISCVCPU), 167 VMSTATE_UINTTL(env.spmbase, RISCVCPU), 168 VMSTATE_UINTTL(env.upmmask, RISCVCPU), 169 VMSTATE_UINTTL(env.upmbase, RISCVCPU), 170 171 VMSTATE_END_OF_LIST() 172 } 173 }; 174 175 static bool rv128_needed(void *opaque) 176 { 177 RISCVCPU *cpu = opaque; 178 CPURISCVState *env = &cpu->env; 179 180 return env->misa_mxl_max == MXL_RV128; 181 } 182 183 static const VMStateDescription vmstate_rv128 = { 184 .name = "cpu/rv128", 185 .version_id = 1, 186 .minimum_version_id = 1, 187 .needed = rv128_needed, 188 .fields = (VMStateField[]) { 189 VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32), 190 VMSTATE_UINT64(env.mscratchh, RISCVCPU), 191 VMSTATE_UINT64(env.sscratchh, RISCVCPU), 192 VMSTATE_END_OF_LIST() 193 } 194 }; 195 196 static bool kvmtimer_needed(void *opaque) 197 { 198 return kvm_enabled(); 199 } 200 201 static int cpu_post_load(void *opaque, int version_id) 202 { 203 RISCVCPU *cpu = opaque; 204 CPURISCVState *env = &cpu->env; 205 206 env->kvm_timer_dirty = true; 207 return 0; 208 } 209 210 static const VMStateDescription vmstate_kvmtimer = { 211 .name = "cpu/kvmtimer", 212 .version_id = 1, 213 .minimum_version_id = 1, 214 .needed = kvmtimer_needed, 215 .post_load = cpu_post_load, 216 .fields = (VMStateField[]) { 217 VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), 218 VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), 219 VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), 220 VMSTATE_END_OF_LIST() 221 } 222 }; 223 224 static bool debug_needed(void *opaque) 225 { 226 RISCVCPU *cpu = opaque; 227 CPURISCVState *env = &cpu->env; 228 229 return riscv_feature(env, RISCV_FEATURE_DEBUG); 230 } 231 232 static const VMStateDescription vmstate_debug = { 233 .name = "cpu/debug", 234 .version_id = 2, 235 .minimum_version_id = 2, 236 .needed = debug_needed, 237 .fields = (VMStateField[]) { 238 VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), 239 VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), 240 VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), 241 VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), 242 VMSTATE_END_OF_LIST() 243 } 244 }; 245 246 static int riscv_cpu_post_load(void *opaque, int version_id) 247 { 248 RISCVCPU *cpu = opaque; 249 CPURISCVState *env = &cpu->env; 250 251 env->xl = cpu_recompute_xl(env); 252 riscv_cpu_update_mask(env); 253 return 0; 254 } 255 256 static bool envcfg_needed(void *opaque) 257 { 258 RISCVCPU *cpu = opaque; 259 CPURISCVState *env = &cpu->env; 260 261 return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0); 262 } 263 264 static const VMStateDescription vmstate_envcfg = { 265 .name = "cpu/envcfg", 266 .version_id = 1, 267 .minimum_version_id = 1, 268 .needed = envcfg_needed, 269 .fields = (VMStateField[]) { 270 VMSTATE_UINT64(env.menvcfg, RISCVCPU), 271 VMSTATE_UINTTL(env.senvcfg, RISCVCPU), 272 VMSTATE_UINT64(env.henvcfg, RISCVCPU), 273 VMSTATE_END_OF_LIST() 274 } 275 }; 276 277 static bool pmu_needed(void *opaque) 278 { 279 RISCVCPU *cpu = opaque; 280 281 return cpu->cfg.pmu_num; 282 } 283 284 static const VMStateDescription vmstate_pmu_ctr_state = { 285 .name = "cpu/pmu", 286 .version_id = 1, 287 .minimum_version_id = 1, 288 .needed = pmu_needed, 289 .fields = (VMStateField[]) { 290 VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState), 291 VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState), 292 VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState), 293 VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState), 294 VMSTATE_BOOL(started, PMUCTRState), 295 VMSTATE_END_OF_LIST() 296 } 297 }; 298 299 const VMStateDescription vmstate_riscv_cpu = { 300 .name = "cpu", 301 .version_id = 5, 302 .minimum_version_id = 5, 303 .post_load = riscv_cpu_post_load, 304 .fields = (VMStateField[]) { 305 VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), 306 VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), 307 VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64), 308 VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64), 309 VMSTATE_UINTTL(env.pc, RISCVCPU), 310 VMSTATE_UINTTL(env.load_res, RISCVCPU), 311 VMSTATE_UINTTL(env.load_val, RISCVCPU), 312 VMSTATE_UINTTL(env.frm, RISCVCPU), 313 VMSTATE_UINTTL(env.badaddr, RISCVCPU), 314 VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), 315 VMSTATE_UINTTL(env.priv_ver, RISCVCPU), 316 VMSTATE_UINTTL(env.vext_ver, RISCVCPU), 317 VMSTATE_UINT32(env.misa_mxl, RISCVCPU), 318 VMSTATE_UINT32(env.misa_ext, RISCVCPU), 319 VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), 320 VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), 321 VMSTATE_UINT32(env.features, RISCVCPU), 322 VMSTATE_UINTTL(env.priv, RISCVCPU), 323 VMSTATE_UINTTL(env.virt, RISCVCPU), 324 VMSTATE_UINT64(env.resetvec, RISCVCPU), 325 VMSTATE_UINTTL(env.mhartid, RISCVCPU), 326 VMSTATE_UINT64(env.mstatus, RISCVCPU), 327 VMSTATE_UINT64(env.mip, RISCVCPU), 328 VMSTATE_UINT64(env.miclaim, RISCVCPU), 329 VMSTATE_UINT64(env.mie, RISCVCPU), 330 VMSTATE_UINT64(env.mideleg, RISCVCPU), 331 VMSTATE_UINTTL(env.satp, RISCVCPU), 332 VMSTATE_UINTTL(env.stval, RISCVCPU), 333 VMSTATE_UINTTL(env.medeleg, RISCVCPU), 334 VMSTATE_UINTTL(env.stvec, RISCVCPU), 335 VMSTATE_UINTTL(env.sepc, RISCVCPU), 336 VMSTATE_UINTTL(env.scause, RISCVCPU), 337 VMSTATE_UINTTL(env.mtvec, RISCVCPU), 338 VMSTATE_UINTTL(env.mepc, RISCVCPU), 339 VMSTATE_UINTTL(env.mcause, RISCVCPU), 340 VMSTATE_UINTTL(env.mtval, RISCVCPU), 341 VMSTATE_UINTTL(env.miselect, RISCVCPU), 342 VMSTATE_UINTTL(env.siselect, RISCVCPU), 343 VMSTATE_UINTTL(env.scounteren, RISCVCPU), 344 VMSTATE_UINTTL(env.mcounteren, RISCVCPU), 345 VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), 346 VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0, 347 vmstate_pmu_ctr_state, PMUCTRState), 348 VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS), 349 VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS), 350 VMSTATE_UINTTL(env.sscratch, RISCVCPU), 351 VMSTATE_UINTTL(env.mscratch, RISCVCPU), 352 VMSTATE_UINT64(env.mfromhost, RISCVCPU), 353 VMSTATE_UINT64(env.mtohost, RISCVCPU), 354 VMSTATE_UINT64(env.stimecmp, RISCVCPU), 355 356 VMSTATE_END_OF_LIST() 357 }, 358 .subsections = (const VMStateDescription * []) { 359 &vmstate_pmp, 360 &vmstate_hyper, 361 &vmstate_vector, 362 &vmstate_pointermasking, 363 &vmstate_rv128, 364 &vmstate_kvmtimer, 365 &vmstate_envcfg, 366 &vmstate_debug, 367 NULL 368 } 369 }; 370