1 /* 2 * RISC-V VMState Description 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "qemu/error-report.h" 22 #include "sysemu/kvm.h" 23 #include "migration/cpu.h" 24 25 static bool pmp_needed(void *opaque) 26 { 27 RISCVCPU *cpu = opaque; 28 CPURISCVState *env = &cpu->env; 29 30 return riscv_feature(env, RISCV_FEATURE_PMP); 31 } 32 33 static int pmp_post_load(void *opaque, int version_id) 34 { 35 RISCVCPU *cpu = opaque; 36 CPURISCVState *env = &cpu->env; 37 int i; 38 39 for (i = 0; i < MAX_RISCV_PMPS; i++) { 40 pmp_update_rule_addr(env, i); 41 } 42 pmp_update_rule_nums(env); 43 44 return 0; 45 } 46 47 static const VMStateDescription vmstate_pmp_entry = { 48 .name = "cpu/pmp/entry", 49 .version_id = 1, 50 .minimum_version_id = 1, 51 .fields = (VMStateField[]) { 52 VMSTATE_UINTTL(addr_reg, pmp_entry_t), 53 VMSTATE_UINT8(cfg_reg, pmp_entry_t), 54 VMSTATE_END_OF_LIST() 55 } 56 }; 57 58 static const VMStateDescription vmstate_pmp = { 59 .name = "cpu/pmp", 60 .version_id = 1, 61 .minimum_version_id = 1, 62 .needed = pmp_needed, 63 .post_load = pmp_post_load, 64 .fields = (VMStateField[]) { 65 VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS, 66 0, vmstate_pmp_entry, pmp_entry_t), 67 VMSTATE_END_OF_LIST() 68 } 69 }; 70 71 static bool hyper_needed(void *opaque) 72 { 73 RISCVCPU *cpu = opaque; 74 CPURISCVState *env = &cpu->env; 75 76 return riscv_has_ext(env, RVH); 77 } 78 79 static const VMStateDescription vmstate_hyper = { 80 .name = "cpu/hyper", 81 .version_id = 2, 82 .minimum_version_id = 2, 83 .needed = hyper_needed, 84 .fields = (VMStateField[]) { 85 VMSTATE_UINTTL(env.hstatus, RISCVCPU), 86 VMSTATE_UINTTL(env.hedeleg, RISCVCPU), 87 VMSTATE_UINT64(env.hideleg, RISCVCPU), 88 VMSTATE_UINTTL(env.hcounteren, RISCVCPU), 89 VMSTATE_UINTTL(env.htval, RISCVCPU), 90 VMSTATE_UINTTL(env.htinst, RISCVCPU), 91 VMSTATE_UINTTL(env.hgatp, RISCVCPU), 92 VMSTATE_UINTTL(env.hgeie, RISCVCPU), 93 VMSTATE_UINTTL(env.hgeip, RISCVCPU), 94 VMSTATE_UINT64(env.htimedelta, RISCVCPU), 95 VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), 96 97 VMSTATE_UINT64(env.vsstatus, RISCVCPU), 98 VMSTATE_UINTTL(env.vstvec, RISCVCPU), 99 VMSTATE_UINTTL(env.vsscratch, RISCVCPU), 100 VMSTATE_UINTTL(env.vsepc, RISCVCPU), 101 VMSTATE_UINTTL(env.vscause, RISCVCPU), 102 VMSTATE_UINTTL(env.vstval, RISCVCPU), 103 VMSTATE_UINTTL(env.vsatp, RISCVCPU), 104 105 VMSTATE_UINTTL(env.mtval2, RISCVCPU), 106 VMSTATE_UINTTL(env.mtinst, RISCVCPU), 107 108 VMSTATE_UINTTL(env.stvec_hs, RISCVCPU), 109 VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU), 110 VMSTATE_UINTTL(env.sepc_hs, RISCVCPU), 111 VMSTATE_UINTTL(env.scause_hs, RISCVCPU), 112 VMSTATE_UINTTL(env.stval_hs, RISCVCPU), 113 VMSTATE_UINTTL(env.satp_hs, RISCVCPU), 114 VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), 115 116 VMSTATE_END_OF_LIST() 117 } 118 }; 119 120 static bool vector_needed(void *opaque) 121 { 122 RISCVCPU *cpu = opaque; 123 CPURISCVState *env = &cpu->env; 124 125 return riscv_has_ext(env, RVV); 126 } 127 128 static const VMStateDescription vmstate_vector = { 129 .name = "cpu/vector", 130 .version_id = 2, 131 .minimum_version_id = 2, 132 .needed = vector_needed, 133 .fields = (VMStateField[]) { 134 VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), 135 VMSTATE_UINTTL(env.vxrm, RISCVCPU), 136 VMSTATE_UINTTL(env.vxsat, RISCVCPU), 137 VMSTATE_UINTTL(env.vl, RISCVCPU), 138 VMSTATE_UINTTL(env.vstart, RISCVCPU), 139 VMSTATE_UINTTL(env.vtype, RISCVCPU), 140 VMSTATE_BOOL(env.vill, RISCVCPU), 141 VMSTATE_END_OF_LIST() 142 } 143 }; 144 145 static bool pointermasking_needed(void *opaque) 146 { 147 RISCVCPU *cpu = opaque; 148 CPURISCVState *env = &cpu->env; 149 150 return riscv_has_ext(env, RVJ); 151 } 152 153 static const VMStateDescription vmstate_pointermasking = { 154 .name = "cpu/pointer_masking", 155 .version_id = 1, 156 .minimum_version_id = 1, 157 .needed = pointermasking_needed, 158 .fields = (VMStateField[]) { 159 VMSTATE_UINTTL(env.mmte, RISCVCPU), 160 VMSTATE_UINTTL(env.mpmmask, RISCVCPU), 161 VMSTATE_UINTTL(env.mpmbase, RISCVCPU), 162 VMSTATE_UINTTL(env.spmmask, RISCVCPU), 163 VMSTATE_UINTTL(env.spmbase, RISCVCPU), 164 VMSTATE_UINTTL(env.upmmask, RISCVCPU), 165 VMSTATE_UINTTL(env.upmbase, RISCVCPU), 166 167 VMSTATE_END_OF_LIST() 168 } 169 }; 170 171 static bool rv128_needed(void *opaque) 172 { 173 RISCVCPU *cpu = opaque; 174 CPURISCVState *env = &cpu->env; 175 176 return env->misa_mxl_max == MXL_RV128; 177 } 178 179 static const VMStateDescription vmstate_rv128 = { 180 .name = "cpu/rv128", 181 .version_id = 1, 182 .minimum_version_id = 1, 183 .needed = rv128_needed, 184 .fields = (VMStateField[]) { 185 VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32), 186 VMSTATE_UINT64(env.mscratchh, RISCVCPU), 187 VMSTATE_UINT64(env.sscratchh, RISCVCPU), 188 VMSTATE_END_OF_LIST() 189 } 190 }; 191 192 static bool kvmtimer_needed(void *opaque) 193 { 194 return kvm_enabled(); 195 } 196 197 static int cpu_post_load(void *opaque, int version_id) 198 { 199 RISCVCPU *cpu = opaque; 200 CPURISCVState *env = &cpu->env; 201 202 env->kvm_timer_dirty = true; 203 return 0; 204 } 205 206 static const VMStateDescription vmstate_kvmtimer = { 207 .name = "cpu/kvmtimer", 208 .version_id = 1, 209 .minimum_version_id = 1, 210 .needed = kvmtimer_needed, 211 .post_load = cpu_post_load, 212 .fields = (VMStateField[]) { 213 VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), 214 VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), 215 VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), 216 217 VMSTATE_END_OF_LIST() 218 } 219 }; 220 221 static int riscv_cpu_post_load(void *opaque, int version_id) 222 { 223 RISCVCPU *cpu = opaque; 224 CPURISCVState *env = &cpu->env; 225 226 env->xl = cpu_recompute_xl(env); 227 riscv_cpu_update_mask(env); 228 return 0; 229 } 230 231 const VMStateDescription vmstate_riscv_cpu = { 232 .name = "cpu", 233 .version_id = 3, 234 .minimum_version_id = 3, 235 .post_load = riscv_cpu_post_load, 236 .fields = (VMStateField[]) { 237 VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), 238 VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), 239 VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64), 240 VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64), 241 VMSTATE_UINTTL(env.pc, RISCVCPU), 242 VMSTATE_UINTTL(env.load_res, RISCVCPU), 243 VMSTATE_UINTTL(env.load_val, RISCVCPU), 244 VMSTATE_UINTTL(env.frm, RISCVCPU), 245 VMSTATE_UINTTL(env.badaddr, RISCVCPU), 246 VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), 247 VMSTATE_UINTTL(env.priv_ver, RISCVCPU), 248 VMSTATE_UINTTL(env.vext_ver, RISCVCPU), 249 VMSTATE_UINT32(env.misa_mxl, RISCVCPU), 250 VMSTATE_UINT32(env.misa_ext, RISCVCPU), 251 VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), 252 VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), 253 VMSTATE_UINT32(env.features, RISCVCPU), 254 VMSTATE_UINTTL(env.priv, RISCVCPU), 255 VMSTATE_UINTTL(env.virt, RISCVCPU), 256 VMSTATE_UINTTL(env.resetvec, RISCVCPU), 257 VMSTATE_UINTTL(env.mhartid, RISCVCPU), 258 VMSTATE_UINT64(env.mstatus, RISCVCPU), 259 VMSTATE_UINT64(env.mip, RISCVCPU), 260 VMSTATE_UINT64(env.miclaim, RISCVCPU), 261 VMSTATE_UINT64(env.mie, RISCVCPU), 262 VMSTATE_UINT64(env.mideleg, RISCVCPU), 263 VMSTATE_UINTTL(env.satp, RISCVCPU), 264 VMSTATE_UINTTL(env.stval, RISCVCPU), 265 VMSTATE_UINTTL(env.medeleg, RISCVCPU), 266 VMSTATE_UINTTL(env.stvec, RISCVCPU), 267 VMSTATE_UINTTL(env.sepc, RISCVCPU), 268 VMSTATE_UINTTL(env.scause, RISCVCPU), 269 VMSTATE_UINTTL(env.mtvec, RISCVCPU), 270 VMSTATE_UINTTL(env.mepc, RISCVCPU), 271 VMSTATE_UINTTL(env.mcause, RISCVCPU), 272 VMSTATE_UINTTL(env.mtval, RISCVCPU), 273 VMSTATE_UINTTL(env.scounteren, RISCVCPU), 274 VMSTATE_UINTTL(env.mcounteren, RISCVCPU), 275 VMSTATE_UINTTL(env.sscratch, RISCVCPU), 276 VMSTATE_UINTTL(env.mscratch, RISCVCPU), 277 VMSTATE_UINT64(env.mfromhost, RISCVCPU), 278 VMSTATE_UINT64(env.mtohost, RISCVCPU), 279 VMSTATE_UINT64(env.timecmp, RISCVCPU), 280 281 VMSTATE_END_OF_LIST() 282 }, 283 .subsections = (const VMStateDescription * []) { 284 &vmstate_pmp, 285 &vmstate_hyper, 286 &vmstate_vector, 287 &vmstate_pointermasking, 288 &vmstate_rv128, 289 &vmstate_kvmtimer, 290 NULL 291 } 292 }; 293