1 /* 2 * RISC-V VMState Description 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "qemu/error-report.h" 22 #include "sysemu/kvm.h" 23 #include "migration/cpu.h" 24 #include "sysemu/cpu-timers.h" 25 #include "debug.h" 26 27 static bool pmp_needed(void *opaque) 28 { 29 RISCVCPU *cpu = opaque; 30 31 return cpu->cfg.pmp; 32 } 33 34 static int pmp_post_load(void *opaque, int version_id) 35 { 36 RISCVCPU *cpu = opaque; 37 CPURISCVState *env = &cpu->env; 38 int i; 39 40 for (i = 0; i < MAX_RISCV_PMPS; i++) { 41 pmp_update_rule_addr(env, i); 42 } 43 pmp_update_rule_nums(env); 44 45 return 0; 46 } 47 48 static const VMStateDescription vmstate_pmp_entry = { 49 .name = "cpu/pmp/entry", 50 .version_id = 1, 51 .minimum_version_id = 1, 52 .fields = (VMStateField[]) { 53 VMSTATE_UINTTL(addr_reg, pmp_entry_t), 54 VMSTATE_UINT8(cfg_reg, pmp_entry_t), 55 VMSTATE_END_OF_LIST() 56 } 57 }; 58 59 static const VMStateDescription vmstate_pmp = { 60 .name = "cpu/pmp", 61 .version_id = 1, 62 .minimum_version_id = 1, 63 .needed = pmp_needed, 64 .post_load = pmp_post_load, 65 .fields = (VMStateField[]) { 66 VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS, 67 0, vmstate_pmp_entry, pmp_entry_t), 68 VMSTATE_END_OF_LIST() 69 } 70 }; 71 72 static bool hyper_needed(void *opaque) 73 { 74 RISCVCPU *cpu = opaque; 75 CPURISCVState *env = &cpu->env; 76 77 return riscv_has_ext(env, RVH); 78 } 79 80 static const VMStateDescription vmstate_hyper = { 81 .name = "cpu/hyper", 82 .version_id = 2, 83 .minimum_version_id = 2, 84 .needed = hyper_needed, 85 .fields = (VMStateField[]) { 86 VMSTATE_UINTTL(env.hstatus, RISCVCPU), 87 VMSTATE_UINTTL(env.hedeleg, RISCVCPU), 88 VMSTATE_UINT64(env.hideleg, RISCVCPU), 89 VMSTATE_UINTTL(env.hcounteren, RISCVCPU), 90 VMSTATE_UINTTL(env.htval, RISCVCPU), 91 VMSTATE_UINTTL(env.htinst, RISCVCPU), 92 VMSTATE_UINTTL(env.hgatp, RISCVCPU), 93 VMSTATE_UINTTL(env.hgeie, RISCVCPU), 94 VMSTATE_UINTTL(env.hgeip, RISCVCPU), 95 VMSTATE_UINT64(env.htimedelta, RISCVCPU), 96 VMSTATE_UINT64(env.vstimecmp, RISCVCPU), 97 98 VMSTATE_UINTTL(env.hvictl, RISCVCPU), 99 VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), 100 101 VMSTATE_UINT64(env.vsstatus, RISCVCPU), 102 VMSTATE_UINTTL(env.vstvec, RISCVCPU), 103 VMSTATE_UINTTL(env.vsscratch, RISCVCPU), 104 VMSTATE_UINTTL(env.vsepc, RISCVCPU), 105 VMSTATE_UINTTL(env.vscause, RISCVCPU), 106 VMSTATE_UINTTL(env.vstval, RISCVCPU), 107 VMSTATE_UINTTL(env.vsatp, RISCVCPU), 108 VMSTATE_UINTTL(env.vsiselect, RISCVCPU), 109 110 VMSTATE_UINTTL(env.mtval2, RISCVCPU), 111 VMSTATE_UINTTL(env.mtinst, RISCVCPU), 112 113 VMSTATE_UINTTL(env.stvec_hs, RISCVCPU), 114 VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU), 115 VMSTATE_UINTTL(env.sepc_hs, RISCVCPU), 116 VMSTATE_UINTTL(env.scause_hs, RISCVCPU), 117 VMSTATE_UINTTL(env.stval_hs, RISCVCPU), 118 VMSTATE_UINTTL(env.satp_hs, RISCVCPU), 119 VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), 120 121 VMSTATE_END_OF_LIST() 122 } 123 }; 124 125 static bool vector_needed(void *opaque) 126 { 127 RISCVCPU *cpu = opaque; 128 CPURISCVState *env = &cpu->env; 129 130 return riscv_has_ext(env, RVV); 131 } 132 133 static const VMStateDescription vmstate_vector = { 134 .name = "cpu/vector", 135 .version_id = 2, 136 .minimum_version_id = 2, 137 .needed = vector_needed, 138 .fields = (VMStateField[]) { 139 VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), 140 VMSTATE_UINTTL(env.vxrm, RISCVCPU), 141 VMSTATE_UINTTL(env.vxsat, RISCVCPU), 142 VMSTATE_UINTTL(env.vl, RISCVCPU), 143 VMSTATE_UINTTL(env.vstart, RISCVCPU), 144 VMSTATE_UINTTL(env.vtype, RISCVCPU), 145 VMSTATE_BOOL(env.vill, RISCVCPU), 146 VMSTATE_END_OF_LIST() 147 } 148 }; 149 150 static bool pointermasking_needed(void *opaque) 151 { 152 RISCVCPU *cpu = opaque; 153 CPURISCVState *env = &cpu->env; 154 155 return riscv_has_ext(env, RVJ); 156 } 157 158 static const VMStateDescription vmstate_pointermasking = { 159 .name = "cpu/pointer_masking", 160 .version_id = 1, 161 .minimum_version_id = 1, 162 .needed = pointermasking_needed, 163 .fields = (VMStateField[]) { 164 VMSTATE_UINTTL(env.mmte, RISCVCPU), 165 VMSTATE_UINTTL(env.mpmmask, RISCVCPU), 166 VMSTATE_UINTTL(env.mpmbase, RISCVCPU), 167 VMSTATE_UINTTL(env.spmmask, RISCVCPU), 168 VMSTATE_UINTTL(env.spmbase, RISCVCPU), 169 VMSTATE_UINTTL(env.upmmask, RISCVCPU), 170 VMSTATE_UINTTL(env.upmbase, RISCVCPU), 171 172 VMSTATE_END_OF_LIST() 173 } 174 }; 175 176 static bool rv128_needed(void *opaque) 177 { 178 RISCVCPU *cpu = opaque; 179 CPURISCVState *env = &cpu->env; 180 181 return env->misa_mxl_max == MXL_RV128; 182 } 183 184 static const VMStateDescription vmstate_rv128 = { 185 .name = "cpu/rv128", 186 .version_id = 1, 187 .minimum_version_id = 1, 188 .needed = rv128_needed, 189 .fields = (VMStateField[]) { 190 VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32), 191 VMSTATE_UINT64(env.mscratchh, RISCVCPU), 192 VMSTATE_UINT64(env.sscratchh, RISCVCPU), 193 VMSTATE_END_OF_LIST() 194 } 195 }; 196 197 static bool kvmtimer_needed(void *opaque) 198 { 199 return kvm_enabled(); 200 } 201 202 static int cpu_post_load(void *opaque, int version_id) 203 { 204 RISCVCPU *cpu = opaque; 205 CPURISCVState *env = &cpu->env; 206 207 env->kvm_timer_dirty = true; 208 return 0; 209 } 210 211 static const VMStateDescription vmstate_kvmtimer = { 212 .name = "cpu/kvmtimer", 213 .version_id = 1, 214 .minimum_version_id = 1, 215 .needed = kvmtimer_needed, 216 .post_load = cpu_post_load, 217 .fields = (VMStateField[]) { 218 VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), 219 VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), 220 VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), 221 VMSTATE_END_OF_LIST() 222 } 223 }; 224 225 static bool debug_needed(void *opaque) 226 { 227 RISCVCPU *cpu = opaque; 228 229 return cpu->cfg.debug; 230 } 231 232 static int debug_post_load(void *opaque, int version_id) 233 { 234 RISCVCPU *cpu = opaque; 235 CPURISCVState *env = &cpu->env; 236 237 if (icount_enabled()) { 238 env->itrigger_enabled = riscv_itrigger_enabled(env); 239 } 240 241 return 0; 242 } 243 244 static const VMStateDescription vmstate_debug = { 245 .name = "cpu/debug", 246 .version_id = 2, 247 .minimum_version_id = 2, 248 .needed = debug_needed, 249 .post_load = debug_post_load, 250 .fields = (VMStateField[]) { 251 VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), 252 VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), 253 VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), 254 VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), 255 VMSTATE_END_OF_LIST() 256 } 257 }; 258 259 static int riscv_cpu_post_load(void *opaque, int version_id) 260 { 261 RISCVCPU *cpu = opaque; 262 CPURISCVState *env = &cpu->env; 263 264 env->xl = cpu_recompute_xl(env); 265 riscv_cpu_update_mask(env); 266 return 0; 267 } 268 269 static bool smstateen_needed(void *opaque) 270 { 271 RISCVCPU *cpu = opaque; 272 273 return cpu->cfg.ext_smstateen; 274 } 275 276 static const VMStateDescription vmstate_smstateen = { 277 .name = "cpu/smtateen", 278 .version_id = 1, 279 .minimum_version_id = 1, 280 .needed = smstateen_needed, 281 .fields = (VMStateField[]) { 282 VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4), 283 VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4), 284 VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4), 285 VMSTATE_END_OF_LIST() 286 } 287 }; 288 289 static bool envcfg_needed(void *opaque) 290 { 291 RISCVCPU *cpu = opaque; 292 CPURISCVState *env = &cpu->env; 293 294 return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0); 295 } 296 297 static const VMStateDescription vmstate_envcfg = { 298 .name = "cpu/envcfg", 299 .version_id = 1, 300 .minimum_version_id = 1, 301 .needed = envcfg_needed, 302 .fields = (VMStateField[]) { 303 VMSTATE_UINT64(env.menvcfg, RISCVCPU), 304 VMSTATE_UINTTL(env.senvcfg, RISCVCPU), 305 VMSTATE_UINT64(env.henvcfg, RISCVCPU), 306 VMSTATE_END_OF_LIST() 307 } 308 }; 309 310 static bool pmu_needed(void *opaque) 311 { 312 RISCVCPU *cpu = opaque; 313 314 return cpu->cfg.pmu_num; 315 } 316 317 static const VMStateDescription vmstate_pmu_ctr_state = { 318 .name = "cpu/pmu", 319 .version_id = 1, 320 .minimum_version_id = 1, 321 .needed = pmu_needed, 322 .fields = (VMStateField[]) { 323 VMSTATE_UINTTL(mhpmcounter_val, PMUCTRState), 324 VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState), 325 VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState), 326 VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState), 327 VMSTATE_BOOL(started, PMUCTRState), 328 VMSTATE_END_OF_LIST() 329 } 330 }; 331 332 static bool jvt_needed(void *opaque) 333 { 334 RISCVCPU *cpu = opaque; 335 336 return cpu->cfg.ext_zcmt; 337 } 338 339 static const VMStateDescription vmstate_jvt = { 340 .name = "cpu/jvt", 341 .version_id = 1, 342 .minimum_version_id = 1, 343 .needed = jvt_needed, 344 .fields = (VMStateField[]) { 345 VMSTATE_UINTTL(env.jvt, RISCVCPU), 346 VMSTATE_END_OF_LIST() 347 } 348 }; 349 350 const VMStateDescription vmstate_riscv_cpu = { 351 .name = "cpu", 352 .version_id = 8, 353 .minimum_version_id = 8, 354 .post_load = riscv_cpu_post_load, 355 .fields = (VMStateField[]) { 356 VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), 357 VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), 358 VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64), 359 VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64), 360 VMSTATE_UINTTL(env.pc, RISCVCPU), 361 VMSTATE_UINTTL(env.load_res, RISCVCPU), 362 VMSTATE_UINTTL(env.load_val, RISCVCPU), 363 VMSTATE_UINTTL(env.frm, RISCVCPU), 364 VMSTATE_UINTTL(env.badaddr, RISCVCPU), 365 VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), 366 VMSTATE_UINTTL(env.priv_ver, RISCVCPU), 367 VMSTATE_UINTTL(env.vext_ver, RISCVCPU), 368 VMSTATE_UINT32(env.misa_mxl, RISCVCPU), 369 VMSTATE_UINT32(env.misa_ext, RISCVCPU), 370 VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), 371 VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), 372 VMSTATE_UINTTL(env.priv, RISCVCPU), 373 VMSTATE_BOOL(env.virt_enabled, RISCVCPU), 374 VMSTATE_UINT64(env.resetvec, RISCVCPU), 375 VMSTATE_UINTTL(env.mhartid, RISCVCPU), 376 VMSTATE_UINT64(env.mstatus, RISCVCPU), 377 VMSTATE_UINT64(env.mip, RISCVCPU), 378 VMSTATE_UINT64(env.miclaim, RISCVCPU), 379 VMSTATE_UINT64(env.mie, RISCVCPU), 380 VMSTATE_UINT64(env.mideleg, RISCVCPU), 381 VMSTATE_UINTTL(env.satp, RISCVCPU), 382 VMSTATE_UINTTL(env.stval, RISCVCPU), 383 VMSTATE_UINTTL(env.medeleg, RISCVCPU), 384 VMSTATE_UINTTL(env.stvec, RISCVCPU), 385 VMSTATE_UINTTL(env.sepc, RISCVCPU), 386 VMSTATE_UINTTL(env.scause, RISCVCPU), 387 VMSTATE_UINTTL(env.mtvec, RISCVCPU), 388 VMSTATE_UINTTL(env.mepc, RISCVCPU), 389 VMSTATE_UINTTL(env.mcause, RISCVCPU), 390 VMSTATE_UINTTL(env.mtval, RISCVCPU), 391 VMSTATE_UINTTL(env.miselect, RISCVCPU), 392 VMSTATE_UINTTL(env.siselect, RISCVCPU), 393 VMSTATE_UINTTL(env.scounteren, RISCVCPU), 394 VMSTATE_UINTTL(env.mcounteren, RISCVCPU), 395 VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), 396 VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0, 397 vmstate_pmu_ctr_state, PMUCTRState), 398 VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS), 399 VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS), 400 VMSTATE_UINTTL(env.sscratch, RISCVCPU), 401 VMSTATE_UINTTL(env.mscratch, RISCVCPU), 402 VMSTATE_UINT64(env.stimecmp, RISCVCPU), 403 404 VMSTATE_END_OF_LIST() 405 }, 406 .subsections = (const VMStateDescription * []) { 407 &vmstate_pmp, 408 &vmstate_hyper, 409 &vmstate_vector, 410 &vmstate_pointermasking, 411 &vmstate_rv128, 412 &vmstate_kvmtimer, 413 &vmstate_envcfg, 414 &vmstate_debug, 415 &vmstate_smstateen, 416 &vmstate_jvt, 417 NULL 418 } 419 }; 420