1 /* 2 * RISC-V VMState Description 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "qemu/error-report.h" 22 #include "sysemu/kvm.h" 23 #include "migration/cpu.h" 24 25 static bool pmp_needed(void *opaque) 26 { 27 RISCVCPU *cpu = opaque; 28 CPURISCVState *env = &cpu->env; 29 30 return riscv_feature(env, RISCV_FEATURE_PMP); 31 } 32 33 static int pmp_post_load(void *opaque, int version_id) 34 { 35 RISCVCPU *cpu = opaque; 36 CPURISCVState *env = &cpu->env; 37 int i; 38 39 for (i = 0; i < MAX_RISCV_PMPS; i++) { 40 pmp_update_rule_addr(env, i); 41 } 42 pmp_update_rule_nums(env); 43 44 return 0; 45 } 46 47 static const VMStateDescription vmstate_pmp_entry = { 48 .name = "cpu/pmp/entry", 49 .version_id = 1, 50 .minimum_version_id = 1, 51 .fields = (VMStateField[]) { 52 VMSTATE_UINTTL(addr_reg, pmp_entry_t), 53 VMSTATE_UINT8(cfg_reg, pmp_entry_t), 54 VMSTATE_END_OF_LIST() 55 } 56 }; 57 58 static const VMStateDescription vmstate_pmp = { 59 .name = "cpu/pmp", 60 .version_id = 1, 61 .minimum_version_id = 1, 62 .needed = pmp_needed, 63 .post_load = pmp_post_load, 64 .fields = (VMStateField[]) { 65 VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS, 66 0, vmstate_pmp_entry, pmp_entry_t), 67 VMSTATE_END_OF_LIST() 68 } 69 }; 70 71 const VMStateDescription vmstate_riscv_cpu = { 72 .name = "cpu", 73 .version_id = 1, 74 .minimum_version_id = 1, 75 .fields = (VMStateField[]) { 76 VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), 77 VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), 78 VMSTATE_UINTTL(env.pc, RISCVCPU), 79 VMSTATE_UINTTL(env.load_res, RISCVCPU), 80 VMSTATE_UINTTL(env.load_val, RISCVCPU), 81 VMSTATE_UINTTL(env.frm, RISCVCPU), 82 VMSTATE_UINTTL(env.badaddr, RISCVCPU), 83 VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), 84 VMSTATE_UINTTL(env.priv_ver, RISCVCPU), 85 VMSTATE_UINTTL(env.vext_ver, RISCVCPU), 86 VMSTATE_UINTTL(env.misa, RISCVCPU), 87 VMSTATE_UINTTL(env.misa_mask, RISCVCPU), 88 VMSTATE_UINT32(env.features, RISCVCPU), 89 VMSTATE_UINTTL(env.priv, RISCVCPU), 90 VMSTATE_UINTTL(env.virt, RISCVCPU), 91 VMSTATE_UINTTL(env.resetvec, RISCVCPU), 92 VMSTATE_UINTTL(env.mhartid, RISCVCPU), 93 VMSTATE_UINT64(env.mstatus, RISCVCPU), 94 VMSTATE_UINTTL(env.mip, RISCVCPU), 95 VMSTATE_UINT32(env.miclaim, RISCVCPU), 96 VMSTATE_UINTTL(env.mie, RISCVCPU), 97 VMSTATE_UINTTL(env.mideleg, RISCVCPU), 98 VMSTATE_UINTTL(env.sptbr, RISCVCPU), 99 VMSTATE_UINTTL(env.satp, RISCVCPU), 100 VMSTATE_UINTTL(env.sbadaddr, RISCVCPU), 101 VMSTATE_UINTTL(env.mbadaddr, RISCVCPU), 102 VMSTATE_UINTTL(env.medeleg, RISCVCPU), 103 VMSTATE_UINTTL(env.stvec, RISCVCPU), 104 VMSTATE_UINTTL(env.sepc, RISCVCPU), 105 VMSTATE_UINTTL(env.scause, RISCVCPU), 106 VMSTATE_UINTTL(env.mtvec, RISCVCPU), 107 VMSTATE_UINTTL(env.mepc, RISCVCPU), 108 VMSTATE_UINTTL(env.mcause, RISCVCPU), 109 VMSTATE_UINTTL(env.mtval, RISCVCPU), 110 VMSTATE_UINTTL(env.scounteren, RISCVCPU), 111 VMSTATE_UINTTL(env.mcounteren, RISCVCPU), 112 VMSTATE_UINTTL(env.sscratch, RISCVCPU), 113 VMSTATE_UINTTL(env.mscratch, RISCVCPU), 114 VMSTATE_UINT64(env.mfromhost, RISCVCPU), 115 VMSTATE_UINT64(env.mtohost, RISCVCPU), 116 VMSTATE_UINT64(env.timecmp, RISCVCPU), 117 118 VMSTATE_END_OF_LIST() 119 }, 120 .subsections = (const VMStateDescription * []) { 121 &vmstate_pmp, 122 NULL 123 } 124 }; 125