1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/kvm.h" 32 #include "sysemu/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "hw/core/accel-cpu.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "exec/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/migration.h" 48 #include "sysemu/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 #define RISCV_CORE_REG(env, name) \ 90 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 91 KVM_REG_RISCV_CORE_REG(name)) 92 93 #define RISCV_CSR_REG(env, name) \ 94 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 95 KVM_REG_RISCV_CSR_REG(name)) 96 97 #define RISCV_CONFIG_REG(env, name) \ 98 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 99 KVM_REG_RISCV_CONFIG_REG(name)) 100 101 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 102 KVM_REG_RISCV_TIMER_REG(name)) 103 104 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 105 106 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 107 108 #define RISCV_VECTOR_CSR_REG(env, name) \ 109 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ 110 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 111 112 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 113 do { \ 114 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 115 if (_ret) { \ 116 return _ret; \ 117 } \ 118 } while (0) 119 120 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 121 do { \ 122 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 123 if (_ret) { \ 124 return _ret; \ 125 } \ 126 } while (0) 127 128 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 129 do { \ 130 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 131 if (ret) { \ 132 abort(); \ 133 } \ 134 } while (0) 135 136 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 137 do { \ 138 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 139 if (ret) { \ 140 abort(); \ 141 } \ 142 } while (0) 143 144 typedef struct KVMCPUConfig { 145 const char *name; 146 const char *description; 147 target_ulong offset; 148 int kvm_reg_id; 149 bool user_set; 150 bool supported; 151 } KVMCPUConfig; 152 153 #define KVM_MISA_CFG(_bit, _reg_id) \ 154 {.offset = _bit, .kvm_reg_id = _reg_id} 155 156 /* KVM ISA extensions */ 157 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 158 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 159 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 160 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 161 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 162 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 163 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 164 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 165 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 166 }; 167 168 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 169 const char *name, 170 void *opaque, Error **errp) 171 { 172 KVMCPUConfig *misa_ext_cfg = opaque; 173 target_ulong misa_bit = misa_ext_cfg->offset; 174 RISCVCPU *cpu = RISCV_CPU(obj); 175 CPURISCVState *env = &cpu->env; 176 bool value = env->misa_ext_mask & misa_bit; 177 178 visit_type_bool(v, name, &value, errp); 179 } 180 181 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 182 const char *name, 183 void *opaque, Error **errp) 184 { 185 KVMCPUConfig *misa_ext_cfg = opaque; 186 target_ulong misa_bit = misa_ext_cfg->offset; 187 RISCVCPU *cpu = RISCV_CPU(obj); 188 CPURISCVState *env = &cpu->env; 189 bool value, host_bit; 190 191 if (!visit_type_bool(v, name, &value, errp)) { 192 return; 193 } 194 195 host_bit = env->misa_ext_mask & misa_bit; 196 197 if (value == host_bit) { 198 return; 199 } 200 201 if (!value) { 202 misa_ext_cfg->user_set = true; 203 return; 204 } 205 206 /* 207 * Forbid users to enable extensions that aren't 208 * available in the hart. 209 */ 210 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 211 "enabled in the host", misa_ext_cfg->name); 212 } 213 214 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 215 { 216 CPURISCVState *env = &cpu->env; 217 uint64_t id, reg; 218 int i, ret; 219 220 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 221 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 222 target_ulong misa_bit = misa_cfg->offset; 223 224 if (!misa_cfg->user_set) { 225 continue; 226 } 227 228 /* If we're here we're going to disable the MISA bit */ 229 reg = 0; 230 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 231 misa_cfg->kvm_reg_id); 232 ret = kvm_set_one_reg(cs, id, ®); 233 if (ret != 0) { 234 /* 235 * We're not checking for -EINVAL because if the bit is about 236 * to be disabled, it means that it was already enabled by 237 * KVM. We determined that by fetching the 'isa' register 238 * during init() time. Any error at this point is worth 239 * aborting. 240 */ 241 error_report("Unable to set KVM reg %s, error %d", 242 misa_cfg->name, ret); 243 exit(EXIT_FAILURE); 244 } 245 env->misa_ext &= ~misa_bit; 246 } 247 } 248 249 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 250 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 251 .kvm_reg_id = _reg_id} 252 253 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 254 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 255 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 256 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 257 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 258 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 259 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 260 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 261 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 262 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 263 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 264 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 265 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 266 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 267 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 268 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 269 }; 270 271 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 272 { 273 return (void *)&cpu->cfg + kvmcfg->offset; 274 } 275 276 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 277 uint32_t val) 278 { 279 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 280 281 *ext_enabled = val; 282 } 283 284 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 285 KVMCPUConfig *multi_ext) 286 { 287 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 288 289 return *ext_enabled; 290 } 291 292 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 293 const char *name, 294 void *opaque, Error **errp) 295 { 296 KVMCPUConfig *multi_ext_cfg = opaque; 297 RISCVCPU *cpu = RISCV_CPU(obj); 298 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 299 300 visit_type_bool(v, name, &value, errp); 301 } 302 303 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 304 const char *name, 305 void *opaque, Error **errp) 306 { 307 KVMCPUConfig *multi_ext_cfg = opaque; 308 RISCVCPU *cpu = RISCV_CPU(obj); 309 bool value, host_val; 310 311 if (!visit_type_bool(v, name, &value, errp)) { 312 return; 313 } 314 315 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 316 317 /* 318 * Ignore if the user is setting the same value 319 * as the host. 320 */ 321 if (value == host_val) { 322 return; 323 } 324 325 if (!multi_ext_cfg->supported) { 326 /* 327 * Error out if the user is trying to enable an 328 * extension that KVM doesn't support. Ignore 329 * option otherwise. 330 */ 331 if (value) { 332 error_setg(errp, "KVM does not support disabling extension %s", 333 multi_ext_cfg->name); 334 } 335 336 return; 337 } 338 339 multi_ext_cfg->user_set = true; 340 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 341 } 342 343 static KVMCPUConfig kvm_cbom_blocksize = { 344 .name = "cbom_blocksize", 345 .offset = CPU_CFG_OFFSET(cbom_blocksize), 346 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 347 }; 348 349 static KVMCPUConfig kvm_cboz_blocksize = { 350 .name = "cboz_blocksize", 351 .offset = CPU_CFG_OFFSET(cboz_blocksize), 352 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 353 }; 354 355 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 356 const char *name, 357 void *opaque, Error **errp) 358 { 359 KVMCPUConfig *cbomz_cfg = opaque; 360 RISCVCPU *cpu = RISCV_CPU(obj); 361 uint16_t value, *host_val; 362 363 if (!visit_type_uint16(v, name, &value, errp)) { 364 return; 365 } 366 367 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 368 369 if (value != *host_val) { 370 error_report("Unable to set %s to a different value than " 371 "the host (%u)", 372 cbomz_cfg->name, *host_val); 373 exit(EXIT_FAILURE); 374 } 375 376 cbomz_cfg->user_set = true; 377 } 378 379 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 380 { 381 CPURISCVState *env = &cpu->env; 382 uint64_t id, reg; 383 int i, ret; 384 385 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 386 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 387 388 if (!multi_ext_cfg->user_set) { 389 continue; 390 } 391 392 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 393 multi_ext_cfg->kvm_reg_id); 394 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 395 ret = kvm_set_one_reg(cs, id, ®); 396 if (ret != 0) { 397 error_report("Unable to %s extension %s in KVM, error %d", 398 reg ? "enable" : "disable", 399 multi_ext_cfg->name, ret); 400 exit(EXIT_FAILURE); 401 } 402 } 403 } 404 405 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 406 const char *name, 407 void *opaque, Error **errp) 408 { 409 bool value = false; 410 411 visit_type_bool(v, name, &value, errp); 412 } 413 414 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 415 const char *name, 416 void *opaque, Error **errp) 417 { 418 const char *propname = opaque; 419 bool value; 420 421 if (!visit_type_bool(v, name, &value, errp)) { 422 return; 423 } 424 425 if (value) { 426 error_setg(errp, "'%s' is not available with KVM", 427 propname); 428 } 429 } 430 431 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 432 { 433 /* Check if KVM created the property already */ 434 if (object_property_find(obj, prop_name)) { 435 return; 436 } 437 438 /* 439 * Set the default to disabled for every extension 440 * unknown to KVM and error out if the user attempts 441 * to enable any of them. 442 */ 443 object_property_add(obj, prop_name, "bool", 444 cpu_get_cfg_unavailable, 445 cpu_set_cfg_unavailable, 446 NULL, (void *)prop_name); 447 } 448 449 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 450 const RISCVCPUMultiExtConfig *array) 451 { 452 const RISCVCPUMultiExtConfig *prop; 453 454 g_assert(array); 455 456 for (prop = array; prop && prop->name; prop++) { 457 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 458 } 459 } 460 461 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 462 { 463 int i; 464 465 riscv_add_satp_mode_properties(cpu_obj); 466 467 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 468 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 469 int bit = misa_cfg->offset; 470 471 misa_cfg->name = riscv_get_misa_ext_name(bit); 472 misa_cfg->description = riscv_get_misa_ext_description(bit); 473 474 object_property_add(cpu_obj, misa_cfg->name, "bool", 475 kvm_cpu_get_misa_ext_cfg, 476 kvm_cpu_set_misa_ext_cfg, 477 NULL, misa_cfg); 478 object_property_set_description(cpu_obj, misa_cfg->name, 479 misa_cfg->description); 480 } 481 482 for (i = 0; misa_bits[i] != 0; i++) { 483 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 484 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 485 } 486 487 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 488 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 489 490 object_property_add(cpu_obj, multi_cfg->name, "bool", 491 kvm_cpu_get_multi_ext_cfg, 492 kvm_cpu_set_multi_ext_cfg, 493 NULL, multi_cfg); 494 } 495 496 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 497 NULL, kvm_cpu_set_cbomz_blksize, 498 NULL, &kvm_cbom_blocksize); 499 500 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 501 NULL, kvm_cpu_set_cbomz_blksize, 502 NULL, &kvm_cboz_blocksize); 503 504 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 505 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 506 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 507 508 /* We don't have the needed KVM support for profiles */ 509 for (i = 0; riscv_profiles[i] != NULL; i++) { 510 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 511 } 512 } 513 514 static int kvm_riscv_get_regs_core(CPUState *cs) 515 { 516 int ret = 0; 517 int i; 518 target_ulong reg; 519 CPURISCVState *env = &RISCV_CPU(cs)->env; 520 521 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 522 if (ret) { 523 return ret; 524 } 525 env->pc = reg; 526 527 for (i = 1; i < 32; i++) { 528 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 529 ret = kvm_get_one_reg(cs, id, ®); 530 if (ret) { 531 return ret; 532 } 533 env->gpr[i] = reg; 534 } 535 536 return ret; 537 } 538 539 static int kvm_riscv_put_regs_core(CPUState *cs) 540 { 541 int ret = 0; 542 int i; 543 target_ulong reg; 544 CPURISCVState *env = &RISCV_CPU(cs)->env; 545 546 reg = env->pc; 547 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 548 if (ret) { 549 return ret; 550 } 551 552 for (i = 1; i < 32; i++) { 553 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 554 reg = env->gpr[i]; 555 ret = kvm_set_one_reg(cs, id, ®); 556 if (ret) { 557 return ret; 558 } 559 } 560 561 return ret; 562 } 563 564 static int kvm_riscv_get_regs_csr(CPUState *cs) 565 { 566 CPURISCVState *env = &RISCV_CPU(cs)->env; 567 568 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 569 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 570 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 571 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 572 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 573 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 574 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 575 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 576 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 577 578 return 0; 579 } 580 581 static int kvm_riscv_put_regs_csr(CPUState *cs) 582 { 583 CPURISCVState *env = &RISCV_CPU(cs)->env; 584 585 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 586 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 587 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 588 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 589 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 590 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 591 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 592 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 593 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 594 595 return 0; 596 } 597 598 static int kvm_riscv_get_regs_fp(CPUState *cs) 599 { 600 int ret = 0; 601 int i; 602 CPURISCVState *env = &RISCV_CPU(cs)->env; 603 604 if (riscv_has_ext(env, RVD)) { 605 uint64_t reg; 606 for (i = 0; i < 32; i++) { 607 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 608 if (ret) { 609 return ret; 610 } 611 env->fpr[i] = reg; 612 } 613 return ret; 614 } 615 616 if (riscv_has_ext(env, RVF)) { 617 uint32_t reg; 618 for (i = 0; i < 32; i++) { 619 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 620 if (ret) { 621 return ret; 622 } 623 env->fpr[i] = reg; 624 } 625 return ret; 626 } 627 628 return ret; 629 } 630 631 static int kvm_riscv_put_regs_fp(CPUState *cs) 632 { 633 int ret = 0; 634 int i; 635 CPURISCVState *env = &RISCV_CPU(cs)->env; 636 637 if (riscv_has_ext(env, RVD)) { 638 uint64_t reg; 639 for (i = 0; i < 32; i++) { 640 reg = env->fpr[i]; 641 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 642 if (ret) { 643 return ret; 644 } 645 } 646 return ret; 647 } 648 649 if (riscv_has_ext(env, RVF)) { 650 uint32_t reg; 651 for (i = 0; i < 32; i++) { 652 reg = env->fpr[i]; 653 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 654 if (ret) { 655 return ret; 656 } 657 } 658 return ret; 659 } 660 661 return ret; 662 } 663 664 static void kvm_riscv_get_regs_timer(CPUState *cs) 665 { 666 CPURISCVState *env = &RISCV_CPU(cs)->env; 667 668 if (env->kvm_timer_dirty) { 669 return; 670 } 671 672 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 673 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 674 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 675 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 676 677 env->kvm_timer_dirty = true; 678 } 679 680 static void kvm_riscv_put_regs_timer(CPUState *cs) 681 { 682 uint64_t reg; 683 CPURISCVState *env = &RISCV_CPU(cs)->env; 684 685 if (!env->kvm_timer_dirty) { 686 return; 687 } 688 689 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 690 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 691 692 /* 693 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 694 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 695 * doesn't matter that adaping in QEMU now. 696 * TODO If KVM changes, adapt here. 697 */ 698 if (env->kvm_timer_state) { 699 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 700 } 701 702 /* 703 * For now, migration will not work between Hosts with different timer 704 * frequency. Therefore, we should check whether they are the same here 705 * during the migration. 706 */ 707 if (migration_is_running(migrate_get_current()->state)) { 708 KVM_RISCV_GET_TIMER(cs, frequency, reg); 709 if (reg != env->kvm_timer_frequency) { 710 error_report("Dst Hosts timer frequency != Src Hosts"); 711 } 712 } 713 714 env->kvm_timer_dirty = false; 715 } 716 717 static int kvm_riscv_get_regs_vector(CPUState *cs) 718 { 719 CPURISCVState *env = &RISCV_CPU(cs)->env; 720 target_ulong reg; 721 int ret = 0; 722 723 if (!riscv_has_ext(env, RVV)) { 724 return 0; 725 } 726 727 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 728 if (ret) { 729 return ret; 730 } 731 env->vstart = reg; 732 733 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 734 if (ret) { 735 return ret; 736 } 737 env->vl = reg; 738 739 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 740 if (ret) { 741 return ret; 742 } 743 env->vtype = reg; 744 745 return 0; 746 } 747 748 static int kvm_riscv_put_regs_vector(CPUState *cs) 749 { 750 CPURISCVState *env = &RISCV_CPU(cs)->env; 751 target_ulong reg; 752 int ret = 0; 753 754 if (!riscv_has_ext(env, RVV)) { 755 return 0; 756 } 757 758 reg = env->vstart; 759 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 760 if (ret) { 761 return ret; 762 } 763 764 reg = env->vl; 765 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 766 if (ret) { 767 return ret; 768 } 769 770 reg = env->vtype; 771 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 772 773 return ret; 774 } 775 776 typedef struct KVMScratchCPU { 777 int kvmfd; 778 int vmfd; 779 int cpufd; 780 } KVMScratchCPU; 781 782 /* 783 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 784 * from target/arm/kvm.c. 785 */ 786 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 787 { 788 int kvmfd = -1, vmfd = -1, cpufd = -1; 789 790 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 791 if (kvmfd < 0) { 792 goto err; 793 } 794 do { 795 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 796 } while (vmfd == -1 && errno == EINTR); 797 if (vmfd < 0) { 798 goto err; 799 } 800 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 801 if (cpufd < 0) { 802 goto err; 803 } 804 805 scratch->kvmfd = kvmfd; 806 scratch->vmfd = vmfd; 807 scratch->cpufd = cpufd; 808 809 return true; 810 811 err: 812 if (cpufd >= 0) { 813 close(cpufd); 814 } 815 if (vmfd >= 0) { 816 close(vmfd); 817 } 818 if (kvmfd >= 0) { 819 close(kvmfd); 820 } 821 822 return false; 823 } 824 825 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 826 { 827 close(scratch->cpufd); 828 close(scratch->vmfd); 829 close(scratch->kvmfd); 830 } 831 832 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 833 { 834 CPURISCVState *env = &cpu->env; 835 struct kvm_one_reg reg; 836 int ret; 837 838 reg.id = RISCV_CONFIG_REG(env, mvendorid); 839 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 840 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 841 if (ret != 0) { 842 error_report("Unable to retrieve mvendorid from host, error %d", ret); 843 } 844 845 reg.id = RISCV_CONFIG_REG(env, marchid); 846 reg.addr = (uint64_t)&cpu->cfg.marchid; 847 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 848 if (ret != 0) { 849 error_report("Unable to retrieve marchid from host, error %d", ret); 850 } 851 852 reg.id = RISCV_CONFIG_REG(env, mimpid); 853 reg.addr = (uint64_t)&cpu->cfg.mimpid; 854 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 855 if (ret != 0) { 856 error_report("Unable to retrieve mimpid from host, error %d", ret); 857 } 858 } 859 860 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 861 KVMScratchCPU *kvmcpu) 862 { 863 CPURISCVState *env = &cpu->env; 864 struct kvm_one_reg reg; 865 int ret; 866 867 reg.id = RISCV_CONFIG_REG(env, isa); 868 reg.addr = (uint64_t)&env->misa_ext_mask; 869 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 870 871 if (ret) { 872 error_report("Unable to fetch ISA register from KVM, " 873 "error %d", ret); 874 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 875 exit(EXIT_FAILURE); 876 } 877 878 env->misa_ext = env->misa_ext_mask; 879 } 880 881 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 882 KVMCPUConfig *cbomz_cfg) 883 { 884 CPURISCVState *env = &cpu->env; 885 struct kvm_one_reg reg; 886 int ret; 887 888 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 889 cbomz_cfg->kvm_reg_id); 890 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 891 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 892 if (ret != 0) { 893 error_report("Unable to read KVM reg %s, error %d", 894 cbomz_cfg->name, ret); 895 exit(EXIT_FAILURE); 896 } 897 } 898 899 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 900 KVMScratchCPU *kvmcpu) 901 { 902 CPURISCVState *env = &cpu->env; 903 uint64_t val; 904 int i, ret; 905 906 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 907 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 908 struct kvm_one_reg reg; 909 910 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 911 multi_ext_cfg->kvm_reg_id); 912 reg.addr = (uint64_t)&val; 913 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 914 if (ret != 0) { 915 if (errno == EINVAL) { 916 /* Silently default to 'false' if KVM does not support it. */ 917 multi_ext_cfg->supported = false; 918 val = false; 919 } else { 920 error_report("Unable to read ISA_EXT KVM register %s: %s", 921 multi_ext_cfg->name, strerror(errno)); 922 exit(EXIT_FAILURE); 923 } 924 } else { 925 multi_ext_cfg->supported = true; 926 } 927 928 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 929 } 930 931 if (cpu->cfg.ext_zicbom) { 932 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 933 } 934 935 if (cpu->cfg.ext_zicboz) { 936 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 937 } 938 } 939 940 static int uint64_cmp(const void *a, const void *b) 941 { 942 uint64_t val1 = *(const uint64_t *)a; 943 uint64_t val2 = *(const uint64_t *)b; 944 945 if (val1 < val2) { 946 return -1; 947 } 948 949 if (val1 > val2) { 950 return 1; 951 } 952 953 return 0; 954 } 955 956 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 957 { 958 KVMCPUConfig *multi_ext_cfg; 959 struct kvm_one_reg reg; 960 struct kvm_reg_list rl_struct; 961 struct kvm_reg_list *reglist; 962 uint64_t val, reg_id, *reg_search; 963 int i, ret; 964 965 rl_struct.n = 0; 966 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 967 968 /* 969 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 970 * (EINVAL). Use read_legacy() in this case. 971 */ 972 if (errno == EINVAL) { 973 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 974 } else if (errno != E2BIG) { 975 /* 976 * E2BIG is an expected error message for the API since we 977 * don't know the number of registers. The right amount will 978 * be written in rl_struct.n. 979 * 980 * Error out if we get any other errno. 981 */ 982 error_report("Error when accessing get-reg-list: %s", 983 strerror(errno)); 984 exit(EXIT_FAILURE); 985 } 986 987 reglist = g_malloc(sizeof(struct kvm_reg_list) + 988 rl_struct.n * sizeof(uint64_t)); 989 reglist->n = rl_struct.n; 990 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 991 if (ret) { 992 error_report("Error when reading KVM_GET_REG_LIST: %s", 993 strerror(errno)); 994 exit(EXIT_FAILURE); 995 } 996 997 /* sort reglist to use bsearch() */ 998 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 999 1000 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1001 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1002 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 1003 multi_ext_cfg->kvm_reg_id); 1004 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1005 sizeof(uint64_t), uint64_cmp); 1006 if (!reg_search) { 1007 continue; 1008 } 1009 1010 reg.id = reg_id; 1011 reg.addr = (uint64_t)&val; 1012 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1013 if (ret != 0) { 1014 error_report("Unable to read ISA_EXT KVM register %s: %s", 1015 multi_ext_cfg->name, strerror(errno)); 1016 exit(EXIT_FAILURE); 1017 } 1018 1019 multi_ext_cfg->supported = true; 1020 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1021 } 1022 1023 if (cpu->cfg.ext_zicbom) { 1024 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1025 } 1026 1027 if (cpu->cfg.ext_zicboz) { 1028 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1029 } 1030 } 1031 1032 static void riscv_init_kvm_registers(Object *cpu_obj) 1033 { 1034 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1035 KVMScratchCPU kvmcpu; 1036 1037 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1038 return; 1039 } 1040 1041 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1042 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1043 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1044 1045 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1046 } 1047 1048 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1049 KVM_CAP_LAST_INFO 1050 }; 1051 1052 int kvm_arch_get_registers(CPUState *cs) 1053 { 1054 int ret = 0; 1055 1056 ret = kvm_riscv_get_regs_core(cs); 1057 if (ret) { 1058 return ret; 1059 } 1060 1061 ret = kvm_riscv_get_regs_csr(cs); 1062 if (ret) { 1063 return ret; 1064 } 1065 1066 ret = kvm_riscv_get_regs_fp(cs); 1067 if (ret) { 1068 return ret; 1069 } 1070 1071 ret = kvm_riscv_get_regs_vector(cs); 1072 if (ret) { 1073 return ret; 1074 } 1075 1076 return ret; 1077 } 1078 1079 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1080 { 1081 if (cap_has_mp_state) { 1082 struct kvm_mp_state mp_state = { 1083 .mp_state = state 1084 }; 1085 1086 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1087 if (ret) { 1088 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1089 __func__, ret, strerror(-ret)); 1090 return -1; 1091 } 1092 } 1093 1094 return 0; 1095 } 1096 1097 int kvm_arch_put_registers(CPUState *cs, int level) 1098 { 1099 int ret = 0; 1100 1101 ret = kvm_riscv_put_regs_core(cs); 1102 if (ret) { 1103 return ret; 1104 } 1105 1106 ret = kvm_riscv_put_regs_csr(cs); 1107 if (ret) { 1108 return ret; 1109 } 1110 1111 ret = kvm_riscv_put_regs_fp(cs); 1112 if (ret) { 1113 return ret; 1114 } 1115 1116 ret = kvm_riscv_put_regs_vector(cs); 1117 if (ret) { 1118 return ret; 1119 } 1120 1121 if (KVM_PUT_RESET_STATE == level) { 1122 RISCVCPU *cpu = RISCV_CPU(cs); 1123 if (cs->cpu_index == 0) { 1124 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1125 } else { 1126 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1127 } 1128 if (ret) { 1129 return ret; 1130 } 1131 } 1132 1133 return ret; 1134 } 1135 1136 int kvm_arch_release_virq_post(int virq) 1137 { 1138 return 0; 1139 } 1140 1141 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1142 uint64_t address, uint32_t data, PCIDevice *dev) 1143 { 1144 return 0; 1145 } 1146 1147 int kvm_arch_destroy_vcpu(CPUState *cs) 1148 { 1149 return 0; 1150 } 1151 1152 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1153 { 1154 return cpu->cpu_index; 1155 } 1156 1157 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1158 RunState state) 1159 { 1160 CPUState *cs = opaque; 1161 1162 if (running) { 1163 kvm_riscv_put_regs_timer(cs); 1164 } else { 1165 kvm_riscv_get_regs_timer(cs); 1166 } 1167 } 1168 1169 void kvm_arch_init_irq_routing(KVMState *s) 1170 { 1171 } 1172 1173 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1174 { 1175 CPURISCVState *env = &cpu->env; 1176 target_ulong reg; 1177 uint64_t id; 1178 int ret; 1179 1180 id = RISCV_CONFIG_REG(env, mvendorid); 1181 /* 1182 * cfg.mvendorid is an uint32 but a target_ulong will 1183 * be written. Assign it to a target_ulong var to avoid 1184 * writing pieces of other cpu->cfg fields in the reg. 1185 */ 1186 reg = cpu->cfg.mvendorid; 1187 ret = kvm_set_one_reg(cs, id, ®); 1188 if (ret != 0) { 1189 return ret; 1190 } 1191 1192 id = RISCV_CONFIG_REG(env, marchid); 1193 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1194 if (ret != 0) { 1195 return ret; 1196 } 1197 1198 id = RISCV_CONFIG_REG(env, mimpid); 1199 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1200 1201 return ret; 1202 } 1203 1204 int kvm_arch_init_vcpu(CPUState *cs) 1205 { 1206 int ret = 0; 1207 RISCVCPU *cpu = RISCV_CPU(cs); 1208 1209 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1210 1211 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1212 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1213 if (ret != 0) { 1214 return ret; 1215 } 1216 } 1217 1218 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1219 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1220 1221 return ret; 1222 } 1223 1224 int kvm_arch_msi_data_to_gsi(uint32_t data) 1225 { 1226 abort(); 1227 } 1228 1229 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1230 int vector, PCIDevice *dev) 1231 { 1232 return 0; 1233 } 1234 1235 int kvm_arch_get_default_type(MachineState *ms) 1236 { 1237 return 0; 1238 } 1239 1240 int kvm_arch_init(MachineState *ms, KVMState *s) 1241 { 1242 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1243 return 0; 1244 } 1245 1246 int kvm_arch_irqchip_create(KVMState *s) 1247 { 1248 if (kvm_kernel_irqchip_split()) { 1249 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1250 exit(1); 1251 } 1252 1253 /* 1254 * We can create the VAIA using the newer device control API. 1255 */ 1256 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1257 } 1258 1259 int kvm_arch_process_async_events(CPUState *cs) 1260 { 1261 return 0; 1262 } 1263 1264 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1265 { 1266 } 1267 1268 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1269 { 1270 return MEMTXATTRS_UNSPECIFIED; 1271 } 1272 1273 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1274 { 1275 return true; 1276 } 1277 1278 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1279 { 1280 int ret = 0; 1281 unsigned char ch; 1282 switch (run->riscv_sbi.extension_id) { 1283 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1284 ch = run->riscv_sbi.args[0]; 1285 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1286 break; 1287 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1288 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1289 if (ret == sizeof(ch)) { 1290 run->riscv_sbi.ret[0] = ch; 1291 } else { 1292 run->riscv_sbi.ret[0] = -1; 1293 } 1294 ret = 0; 1295 break; 1296 default: 1297 qemu_log_mask(LOG_UNIMP, 1298 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1299 __func__, run->riscv_sbi.extension_id); 1300 ret = -1; 1301 break; 1302 } 1303 return ret; 1304 } 1305 1306 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1307 { 1308 int ret = 0; 1309 switch (run->exit_reason) { 1310 case KVM_EXIT_RISCV_SBI: 1311 ret = kvm_riscv_handle_sbi(cs, run); 1312 break; 1313 default: 1314 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1315 __func__, run->exit_reason); 1316 ret = -1; 1317 break; 1318 } 1319 return ret; 1320 } 1321 1322 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1323 { 1324 CPURISCVState *env = &cpu->env; 1325 int i; 1326 1327 if (!kvm_enabled()) { 1328 return; 1329 } 1330 for (i = 0; i < 32; i++) { 1331 env->gpr[i] = 0; 1332 } 1333 env->pc = cpu->env.kernel_addr; 1334 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1335 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1336 env->satp = 0; 1337 env->mie = 0; 1338 env->stvec = 0; 1339 env->sscratch = 0; 1340 env->sepc = 0; 1341 env->scause = 0; 1342 env->stval = 0; 1343 env->mip = 0; 1344 } 1345 1346 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1347 { 1348 int ret; 1349 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1350 1351 if (irq != IRQ_S_EXT) { 1352 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1353 abort(); 1354 } 1355 1356 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1357 if (ret < 0) { 1358 perror("Set irq failed"); 1359 abort(); 1360 } 1361 } 1362 1363 bool kvm_arch_cpu_check_are_resettable(void) 1364 { 1365 return true; 1366 } 1367 1368 static int aia_mode; 1369 1370 static const char *kvm_aia_mode_str(uint64_t mode) 1371 { 1372 switch (mode) { 1373 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1374 return "emul"; 1375 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1376 return "hwaccel"; 1377 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1378 default: 1379 return "auto"; 1380 }; 1381 } 1382 1383 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1384 { 1385 return g_strdup(kvm_aia_mode_str(aia_mode)); 1386 } 1387 1388 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1389 { 1390 if (!strcmp(val, "emul")) { 1391 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1392 } else if (!strcmp(val, "hwaccel")) { 1393 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1394 } else if (!strcmp(val, "auto")) { 1395 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1396 } else { 1397 error_setg(errp, "Invalid KVM AIA mode"); 1398 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1399 } 1400 } 1401 1402 void kvm_arch_accel_class_init(ObjectClass *oc) 1403 { 1404 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1405 riscv_set_kvm_aia); 1406 object_class_property_set_description(oc, "riscv-aia", 1407 "Set KVM AIA mode. Valid values are " 1408 "emul, hwaccel, and auto. Default " 1409 "is auto."); 1410 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1411 "auto"); 1412 } 1413 1414 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1415 uint64_t aia_irq_num, uint64_t aia_msi_num, 1416 uint64_t aplic_base, uint64_t imsic_base, 1417 uint64_t guest_num) 1418 { 1419 int ret, i; 1420 int aia_fd = -1; 1421 uint64_t default_aia_mode; 1422 uint64_t socket_count = riscv_socket_count(machine); 1423 uint64_t max_hart_per_socket = 0; 1424 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1425 uint64_t socket_bits, hart_bits, guest_bits; 1426 1427 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1428 1429 if (aia_fd < 0) { 1430 error_report("Unable to create in-kernel irqchip"); 1431 exit(1); 1432 } 1433 1434 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1435 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1436 &default_aia_mode, false, NULL); 1437 if (ret < 0) { 1438 error_report("KVM AIA: failed to get current KVM AIA mode"); 1439 exit(1); 1440 } 1441 qemu_log("KVM AIA: default mode is %s\n", 1442 kvm_aia_mode_str(default_aia_mode)); 1443 1444 if (default_aia_mode != aia_mode) { 1445 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1446 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1447 &aia_mode, true, NULL); 1448 if (ret < 0) 1449 warn_report("KVM AIA: failed to set KVM AIA mode"); 1450 else 1451 qemu_log("KVM AIA: set current mode to %s\n", 1452 kvm_aia_mode_str(aia_mode)); 1453 } 1454 1455 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1456 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1457 &aia_irq_num, true, NULL); 1458 if (ret < 0) { 1459 error_report("KVM AIA: failed to set number of input irq lines"); 1460 exit(1); 1461 } 1462 1463 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1464 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1465 &aia_msi_num, true, NULL); 1466 if (ret < 0) { 1467 error_report("KVM AIA: failed to set number of msi"); 1468 exit(1); 1469 } 1470 1471 1472 if (socket_count > 1) { 1473 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1474 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1475 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1476 &socket_bits, true, NULL); 1477 if (ret < 0) { 1478 error_report("KVM AIA: failed to set group_bits"); 1479 exit(1); 1480 } 1481 1482 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1483 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1484 &group_shift, true, NULL); 1485 if (ret < 0) { 1486 error_report("KVM AIA: failed to set group_shift"); 1487 exit(1); 1488 } 1489 } 1490 1491 guest_bits = guest_num == 0 ? 0 : 1492 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1493 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1494 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1495 &guest_bits, true, NULL); 1496 if (ret < 0) { 1497 error_report("KVM AIA: failed to set guest_bits"); 1498 exit(1); 1499 } 1500 1501 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1502 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1503 &aplic_base, true, NULL); 1504 if (ret < 0) { 1505 error_report("KVM AIA: failed to set the base address of APLIC"); 1506 exit(1); 1507 } 1508 1509 for (socket = 0; socket < socket_count; socket++) { 1510 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1511 hart_count = riscv_socket_hart_count(machine, socket); 1512 base_hart = riscv_socket_first_hartid(machine, socket); 1513 1514 if (max_hart_per_socket < hart_count) { 1515 max_hart_per_socket = hart_count; 1516 } 1517 1518 for (i = 0; i < hart_count; i++) { 1519 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1520 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1521 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1522 &imsic_addr, true, NULL); 1523 if (ret < 0) { 1524 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1525 exit(1); 1526 } 1527 } 1528 } 1529 1530 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1531 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1532 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1533 &hart_bits, true, NULL); 1534 if (ret < 0) { 1535 error_report("KVM AIA: failed to set hart_bits"); 1536 exit(1); 1537 } 1538 1539 if (kvm_has_gsi_routing()) { 1540 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1541 /* KVM AIA only has one APLIC instance */ 1542 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1543 } 1544 kvm_gsi_routing_allowed = true; 1545 kvm_irqchip_commit_routes(kvm_state); 1546 } 1547 1548 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1549 KVM_DEV_RISCV_AIA_CTRL_INIT, 1550 NULL, true, NULL); 1551 if (ret < 0) { 1552 error_report("KVM AIA: initialized fail"); 1553 exit(1); 1554 } 1555 1556 kvm_msi_via_irqfd_allowed = true; 1557 } 1558 1559 static void kvm_cpu_instance_init(CPUState *cs) 1560 { 1561 Object *obj = OBJECT(RISCV_CPU(cs)); 1562 DeviceState *dev = DEVICE(obj); 1563 1564 riscv_init_kvm_registers(obj); 1565 1566 kvm_riscv_add_cpu_user_properties(obj); 1567 1568 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1569 /* Check if we have a specific KVM handler for the option */ 1570 if (object_property_find(obj, prop->name)) { 1571 continue; 1572 } 1573 qdev_property_add_static(dev, prop); 1574 } 1575 } 1576 1577 /* 1578 * We'll get here via the following path: 1579 * 1580 * riscv_cpu_realize() 1581 * -> cpu_exec_realizefn() 1582 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1583 */ 1584 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1585 { 1586 RISCVCPU *cpu = RISCV_CPU(cs); 1587 int ret; 1588 1589 if (riscv_has_ext(&cpu->env, RVV)) { 1590 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1591 if (ret) { 1592 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1593 strerrorname_np(errno)); 1594 return false; 1595 } 1596 } 1597 1598 return true; 1599 } 1600 1601 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1602 { 1603 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1604 1605 acc->cpu_instance_init = kvm_cpu_instance_init; 1606 acc->cpu_target_realize = kvm_cpu_realize; 1607 } 1608 1609 static const TypeInfo kvm_cpu_accel_type_info = { 1610 .name = ACCEL_CPU_NAME("kvm"), 1611 1612 .parent = TYPE_ACCEL_CPU, 1613 .class_init = kvm_cpu_accel_class_init, 1614 .abstract = true, 1615 }; 1616 static void kvm_cpu_accel_register_types(void) 1617 { 1618 type_register_static(&kvm_cpu_accel_type_info); 1619 } 1620 type_init(kvm_cpu_accel_register_types); 1621 1622 static void riscv_host_cpu_init(Object *obj) 1623 { 1624 CPURISCVState *env = &RISCV_CPU(obj)->env; 1625 1626 #if defined(TARGET_RISCV32) 1627 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1628 #elif defined(TARGET_RISCV64) 1629 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1630 #endif 1631 } 1632 1633 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1634 { 1635 .name = TYPE_RISCV_CPU_HOST, 1636 .parent = TYPE_RISCV_CPU, 1637 .instance_init = riscv_host_cpu_init, 1638 } 1639 }; 1640 1641 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1642