1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ 76 KVM_REG_RISCV_CORE_REG(name)) 77 78 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ 79 KVM_REG_RISCV_CSR_REG(name)) 80 81 #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ 82 KVM_REG_RISCV_TIMER_REG(name)) 83 84 #define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) 85 86 #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) 87 88 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 89 do { \ 90 int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 91 if (ret) { \ 92 return ret; \ 93 } \ 94 } while (0) 95 96 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 97 do { \ 98 int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 99 if (ret) { \ 100 return ret; \ 101 } \ 102 } while (0) 103 104 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ 105 do { \ 106 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 107 if (ret) { \ 108 abort(); \ 109 } \ 110 } while (0) 111 112 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ 113 do { \ 114 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 115 if (ret) { \ 116 abort(); \ 117 } \ 118 } while (0) 119 120 typedef struct KVMCPUConfig { 121 const char *name; 122 const char *description; 123 target_ulong offset; 124 int kvm_reg_id; 125 bool user_set; 126 bool supported; 127 } KVMCPUConfig; 128 129 #define KVM_MISA_CFG(_bit, _reg_id) \ 130 {.offset = _bit, .kvm_reg_id = _reg_id} 131 132 /* KVM ISA extensions */ 133 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 134 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 135 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 136 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 137 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 138 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 139 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 140 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 141 }; 142 143 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 144 const char *name, 145 void *opaque, Error **errp) 146 { 147 KVMCPUConfig *misa_ext_cfg = opaque; 148 target_ulong misa_bit = misa_ext_cfg->offset; 149 RISCVCPU *cpu = RISCV_CPU(obj); 150 CPURISCVState *env = &cpu->env; 151 bool value, host_bit; 152 153 if (!visit_type_bool(v, name, &value, errp)) { 154 return; 155 } 156 157 host_bit = env->misa_ext_mask & misa_bit; 158 159 if (value == host_bit) { 160 return; 161 } 162 163 if (!value) { 164 misa_ext_cfg->user_set = true; 165 return; 166 } 167 168 /* 169 * Forbid users to enable extensions that aren't 170 * available in the hart. 171 */ 172 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 173 "enabled in the host", misa_ext_cfg->name); 174 } 175 176 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 177 { 178 CPURISCVState *env = &cpu->env; 179 uint64_t id, reg; 180 int i, ret; 181 182 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 183 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 184 target_ulong misa_bit = misa_cfg->offset; 185 186 if (!misa_cfg->user_set) { 187 continue; 188 } 189 190 /* If we're here we're going to disable the MISA bit */ 191 reg = 0; 192 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 193 misa_cfg->kvm_reg_id); 194 ret = kvm_set_one_reg(cs, id, ®); 195 if (ret != 0) { 196 /* 197 * We're not checking for -EINVAL because if the bit is about 198 * to be disabled, it means that it was already enabled by 199 * KVM. We determined that by fetching the 'isa' register 200 * during init() time. Any error at this point is worth 201 * aborting. 202 */ 203 error_report("Unable to set KVM reg %s, error %d", 204 misa_cfg->name, ret); 205 exit(EXIT_FAILURE); 206 } 207 env->misa_ext &= ~misa_bit; 208 } 209 } 210 211 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 212 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 213 .kvm_reg_id = _reg_id} 214 215 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 216 KVM_EXT_CFG("zicbom", ext_icbom, KVM_RISCV_ISA_EXT_ZICBOM), 217 KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ), 218 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 219 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 220 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 221 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 222 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 223 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 224 }; 225 226 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 227 { 228 return (void *)&cpu->cfg + kvmcfg->offset; 229 } 230 231 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 232 uint32_t val) 233 { 234 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 235 236 *ext_enabled = val; 237 } 238 239 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 240 KVMCPUConfig *multi_ext) 241 { 242 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 243 244 return *ext_enabled; 245 } 246 247 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 248 const char *name, 249 void *opaque, Error **errp) 250 { 251 KVMCPUConfig *multi_ext_cfg = opaque; 252 RISCVCPU *cpu = RISCV_CPU(obj); 253 bool value, host_val; 254 255 if (!visit_type_bool(v, name, &value, errp)) { 256 return; 257 } 258 259 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 260 261 /* 262 * Ignore if the user is setting the same value 263 * as the host. 264 */ 265 if (value == host_val) { 266 return; 267 } 268 269 if (!multi_ext_cfg->supported) { 270 /* 271 * Error out if the user is trying to enable an 272 * extension that KVM doesn't support. Ignore 273 * option otherwise. 274 */ 275 if (value) { 276 error_setg(errp, "KVM does not support disabling extension %s", 277 multi_ext_cfg->name); 278 } 279 280 return; 281 } 282 283 multi_ext_cfg->user_set = true; 284 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 285 } 286 287 static KVMCPUConfig kvm_cbom_blocksize = { 288 .name = "cbom_blocksize", 289 .offset = CPU_CFG_OFFSET(cbom_blocksize), 290 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 291 }; 292 293 static KVMCPUConfig kvm_cboz_blocksize = { 294 .name = "cboz_blocksize", 295 .offset = CPU_CFG_OFFSET(cboz_blocksize), 296 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 297 }; 298 299 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 300 const char *name, 301 void *opaque, Error **errp) 302 { 303 KVMCPUConfig *cbomz_cfg = opaque; 304 RISCVCPU *cpu = RISCV_CPU(obj); 305 uint16_t value, *host_val; 306 307 if (!visit_type_uint16(v, name, &value, errp)) { 308 return; 309 } 310 311 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 312 313 if (value != *host_val) { 314 error_report("Unable to set %s to a different value than " 315 "the host (%u)", 316 cbomz_cfg->name, *host_val); 317 exit(EXIT_FAILURE); 318 } 319 320 cbomz_cfg->user_set = true; 321 } 322 323 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 324 { 325 CPURISCVState *env = &cpu->env; 326 uint64_t id, reg; 327 int i, ret; 328 329 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 330 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 331 332 if (!multi_ext_cfg->user_set) { 333 continue; 334 } 335 336 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 337 multi_ext_cfg->kvm_reg_id); 338 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 339 ret = kvm_set_one_reg(cs, id, ®); 340 if (ret != 0) { 341 error_report("Unable to %s extension %s in KVM, error %d", 342 reg ? "enable" : "disable", 343 multi_ext_cfg->name, ret); 344 exit(EXIT_FAILURE); 345 } 346 } 347 } 348 349 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 350 const char *name, 351 void *opaque, Error **errp) 352 { 353 const char *propname = opaque; 354 bool value; 355 356 if (!visit_type_bool(v, name, &value, errp)) { 357 return; 358 } 359 360 if (value) { 361 error_setg(errp, "extension %s is not available with KVM", 362 propname); 363 } 364 } 365 366 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 367 { 368 /* Check if KVM created the property already */ 369 if (object_property_find(obj, prop_name)) { 370 return; 371 } 372 373 /* 374 * Set the default to disabled for every extension 375 * unknown to KVM and error out if the user attempts 376 * to enable any of them. 377 */ 378 object_property_add(obj, prop_name, "bool", 379 NULL, cpu_set_cfg_unavailable, 380 NULL, (void *)prop_name); 381 } 382 383 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 384 const RISCVCPUMultiExtConfig *array) 385 { 386 const RISCVCPUMultiExtConfig *prop; 387 388 g_assert(array); 389 390 for (prop = array; prop && prop->name; prop++) { 391 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 392 } 393 } 394 395 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 396 { 397 int i; 398 399 riscv_add_satp_mode_properties(cpu_obj); 400 401 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 402 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 403 int bit = misa_cfg->offset; 404 405 misa_cfg->name = riscv_get_misa_ext_name(bit); 406 misa_cfg->description = riscv_get_misa_ext_description(bit); 407 408 object_property_add(cpu_obj, misa_cfg->name, "bool", 409 NULL, 410 kvm_cpu_set_misa_ext_cfg, 411 NULL, misa_cfg); 412 object_property_set_description(cpu_obj, misa_cfg->name, 413 misa_cfg->description); 414 } 415 416 for (i = 0; misa_bits[i] != 0; i++) { 417 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 418 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 419 } 420 421 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 422 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 423 424 object_property_add(cpu_obj, multi_cfg->name, "bool", 425 NULL, 426 kvm_cpu_set_multi_ext_cfg, 427 NULL, multi_cfg); 428 } 429 430 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 431 NULL, kvm_cpu_set_cbomz_blksize, 432 NULL, &kvm_cbom_blocksize); 433 434 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 435 NULL, kvm_cpu_set_cbomz_blksize, 436 NULL, &kvm_cboz_blocksize); 437 438 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 439 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 440 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 441 } 442 443 static int kvm_riscv_get_regs_core(CPUState *cs) 444 { 445 int ret = 0; 446 int i; 447 target_ulong reg; 448 CPURISCVState *env = &RISCV_CPU(cs)->env; 449 450 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 451 if (ret) { 452 return ret; 453 } 454 env->pc = reg; 455 456 for (i = 1; i < 32; i++) { 457 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 458 ret = kvm_get_one_reg(cs, id, ®); 459 if (ret) { 460 return ret; 461 } 462 env->gpr[i] = reg; 463 } 464 465 return ret; 466 } 467 468 static int kvm_riscv_put_regs_core(CPUState *cs) 469 { 470 int ret = 0; 471 int i; 472 target_ulong reg; 473 CPURISCVState *env = &RISCV_CPU(cs)->env; 474 475 reg = env->pc; 476 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 477 if (ret) { 478 return ret; 479 } 480 481 for (i = 1; i < 32; i++) { 482 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 483 reg = env->gpr[i]; 484 ret = kvm_set_one_reg(cs, id, ®); 485 if (ret) { 486 return ret; 487 } 488 } 489 490 return ret; 491 } 492 493 static int kvm_riscv_get_regs_csr(CPUState *cs) 494 { 495 int ret = 0; 496 CPURISCVState *env = &RISCV_CPU(cs)->env; 497 498 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 499 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 500 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 501 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 502 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 503 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 504 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 505 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 506 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 507 return ret; 508 } 509 510 static int kvm_riscv_put_regs_csr(CPUState *cs) 511 { 512 int ret = 0; 513 CPURISCVState *env = &RISCV_CPU(cs)->env; 514 515 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 516 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 517 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 518 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 519 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 520 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 521 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 522 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 523 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 524 525 return ret; 526 } 527 528 static int kvm_riscv_get_regs_fp(CPUState *cs) 529 { 530 int ret = 0; 531 int i; 532 CPURISCVState *env = &RISCV_CPU(cs)->env; 533 534 if (riscv_has_ext(env, RVD)) { 535 uint64_t reg; 536 for (i = 0; i < 32; i++) { 537 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 538 if (ret) { 539 return ret; 540 } 541 env->fpr[i] = reg; 542 } 543 return ret; 544 } 545 546 if (riscv_has_ext(env, RVF)) { 547 uint32_t reg; 548 for (i = 0; i < 32; i++) { 549 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 550 if (ret) { 551 return ret; 552 } 553 env->fpr[i] = reg; 554 } 555 return ret; 556 } 557 558 return ret; 559 } 560 561 static int kvm_riscv_put_regs_fp(CPUState *cs) 562 { 563 int ret = 0; 564 int i; 565 CPURISCVState *env = &RISCV_CPU(cs)->env; 566 567 if (riscv_has_ext(env, RVD)) { 568 uint64_t reg; 569 for (i = 0; i < 32; i++) { 570 reg = env->fpr[i]; 571 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 572 if (ret) { 573 return ret; 574 } 575 } 576 return ret; 577 } 578 579 if (riscv_has_ext(env, RVF)) { 580 uint32_t reg; 581 for (i = 0; i < 32; i++) { 582 reg = env->fpr[i]; 583 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 584 if (ret) { 585 return ret; 586 } 587 } 588 return ret; 589 } 590 591 return ret; 592 } 593 594 static void kvm_riscv_get_regs_timer(CPUState *cs) 595 { 596 CPURISCVState *env = &RISCV_CPU(cs)->env; 597 598 if (env->kvm_timer_dirty) { 599 return; 600 } 601 602 KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); 603 KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); 604 KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); 605 KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); 606 607 env->kvm_timer_dirty = true; 608 } 609 610 static void kvm_riscv_put_regs_timer(CPUState *cs) 611 { 612 uint64_t reg; 613 CPURISCVState *env = &RISCV_CPU(cs)->env; 614 615 if (!env->kvm_timer_dirty) { 616 return; 617 } 618 619 KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); 620 KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); 621 622 /* 623 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 624 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 625 * doesn't matter that adaping in QEMU now. 626 * TODO If KVM changes, adapt here. 627 */ 628 if (env->kvm_timer_state) { 629 KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); 630 } 631 632 /* 633 * For now, migration will not work between Hosts with different timer 634 * frequency. Therefore, we should check whether they are the same here 635 * during the migration. 636 */ 637 if (migration_is_running(migrate_get_current()->state)) { 638 KVM_RISCV_GET_TIMER(cs, env, frequency, reg); 639 if (reg != env->kvm_timer_frequency) { 640 error_report("Dst Hosts timer frequency != Src Hosts"); 641 } 642 } 643 644 env->kvm_timer_dirty = false; 645 } 646 647 typedef struct KVMScratchCPU { 648 int kvmfd; 649 int vmfd; 650 int cpufd; 651 } KVMScratchCPU; 652 653 /* 654 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 655 * from target/arm/kvm.c. 656 */ 657 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 658 { 659 int kvmfd = -1, vmfd = -1, cpufd = -1; 660 661 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 662 if (kvmfd < 0) { 663 goto err; 664 } 665 do { 666 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 667 } while (vmfd == -1 && errno == EINTR); 668 if (vmfd < 0) { 669 goto err; 670 } 671 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 672 if (cpufd < 0) { 673 goto err; 674 } 675 676 scratch->kvmfd = kvmfd; 677 scratch->vmfd = vmfd; 678 scratch->cpufd = cpufd; 679 680 return true; 681 682 err: 683 if (cpufd >= 0) { 684 close(cpufd); 685 } 686 if (vmfd >= 0) { 687 close(vmfd); 688 } 689 if (kvmfd >= 0) { 690 close(kvmfd); 691 } 692 693 return false; 694 } 695 696 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 697 { 698 close(scratch->cpufd); 699 close(scratch->vmfd); 700 close(scratch->kvmfd); 701 } 702 703 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 704 { 705 CPURISCVState *env = &cpu->env; 706 struct kvm_one_reg reg; 707 int ret; 708 709 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 710 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 711 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 712 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 713 if (ret != 0) { 714 error_report("Unable to retrieve mvendorid from host, error %d", ret); 715 } 716 717 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 718 KVM_REG_RISCV_CONFIG_REG(marchid)); 719 reg.addr = (uint64_t)&cpu->cfg.marchid; 720 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 721 if (ret != 0) { 722 error_report("Unable to retrieve marchid from host, error %d", ret); 723 } 724 725 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 726 KVM_REG_RISCV_CONFIG_REG(mimpid)); 727 reg.addr = (uint64_t)&cpu->cfg.mimpid; 728 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 729 if (ret != 0) { 730 error_report("Unable to retrieve mimpid from host, error %d", ret); 731 } 732 } 733 734 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 735 KVMScratchCPU *kvmcpu) 736 { 737 CPURISCVState *env = &cpu->env; 738 struct kvm_one_reg reg; 739 int ret; 740 741 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 742 KVM_REG_RISCV_CONFIG_REG(isa)); 743 reg.addr = (uint64_t)&env->misa_ext_mask; 744 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 745 746 if (ret) { 747 error_report("Unable to fetch ISA register from KVM, " 748 "error %d", ret); 749 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 750 exit(EXIT_FAILURE); 751 } 752 753 env->misa_ext = env->misa_ext_mask; 754 } 755 756 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 757 KVMCPUConfig *cbomz_cfg) 758 { 759 CPURISCVState *env = &cpu->env; 760 struct kvm_one_reg reg; 761 int ret; 762 763 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 764 cbomz_cfg->kvm_reg_id); 765 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 766 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 767 if (ret != 0) { 768 error_report("Unable to read KVM reg %s, error %d", 769 cbomz_cfg->name, ret); 770 exit(EXIT_FAILURE); 771 } 772 } 773 774 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 775 KVMScratchCPU *kvmcpu) 776 { 777 CPURISCVState *env = &cpu->env; 778 uint64_t val; 779 int i, ret; 780 781 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 782 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 783 struct kvm_one_reg reg; 784 785 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 786 multi_ext_cfg->kvm_reg_id); 787 reg.addr = (uint64_t)&val; 788 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 789 if (ret != 0) { 790 if (errno == EINVAL) { 791 /* Silently default to 'false' if KVM does not support it. */ 792 multi_ext_cfg->supported = false; 793 val = false; 794 } else { 795 error_report("Unable to read ISA_EXT KVM register %s, " 796 "error code: %s", multi_ext_cfg->name, 797 strerrorname_np(errno)); 798 exit(EXIT_FAILURE); 799 } 800 } else { 801 multi_ext_cfg->supported = true; 802 } 803 804 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 805 } 806 807 if (cpu->cfg.ext_icbom) { 808 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 809 } 810 811 if (cpu->cfg.ext_icboz) { 812 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 813 } 814 } 815 816 static int uint64_cmp(const void *a, const void *b) 817 { 818 uint64_t val1 = *(const uint64_t *)a; 819 uint64_t val2 = *(const uint64_t *)b; 820 821 if (val1 < val2) { 822 return -1; 823 } 824 825 if (val1 > val2) { 826 return 1; 827 } 828 829 return 0; 830 } 831 832 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 833 { 834 KVMCPUConfig *multi_ext_cfg; 835 struct kvm_one_reg reg; 836 struct kvm_reg_list rl_struct; 837 struct kvm_reg_list *reglist; 838 uint64_t val, reg_id, *reg_search; 839 int i, ret; 840 841 rl_struct.n = 0; 842 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 843 844 /* 845 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 846 * (EINVAL). Use read_legacy() in this case. 847 */ 848 if (errno == EINVAL) { 849 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 850 } else if (errno != E2BIG) { 851 /* 852 * E2BIG is an expected error message for the API since we 853 * don't know the number of registers. The right amount will 854 * be written in rl_struct.n. 855 * 856 * Error out if we get any other errno. 857 */ 858 error_report("Error when accessing get-reg-list, code: %s", 859 strerrorname_np(errno)); 860 exit(EXIT_FAILURE); 861 } 862 863 reglist = g_malloc(sizeof(struct kvm_reg_list) + 864 rl_struct.n * sizeof(uint64_t)); 865 reglist->n = rl_struct.n; 866 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 867 if (ret) { 868 error_report("Error when reading KVM_GET_REG_LIST, code %s ", 869 strerrorname_np(errno)); 870 exit(EXIT_FAILURE); 871 } 872 873 /* sort reglist to use bsearch() */ 874 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 875 876 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 877 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 878 reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, 879 multi_ext_cfg->kvm_reg_id); 880 reg_search = bsearch(®_id, reglist->reg, reglist->n, 881 sizeof(uint64_t), uint64_cmp); 882 if (!reg_search) { 883 continue; 884 } 885 886 reg.id = reg_id; 887 reg.addr = (uint64_t)&val; 888 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 889 if (ret != 0) { 890 error_report("Unable to read ISA_EXT KVM register %s, " 891 "error code: %s", multi_ext_cfg->name, 892 strerrorname_np(errno)); 893 exit(EXIT_FAILURE); 894 } 895 896 multi_ext_cfg->supported = true; 897 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 898 } 899 900 if (cpu->cfg.ext_icbom) { 901 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 902 } 903 904 if (cpu->cfg.ext_icboz) { 905 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 906 } 907 } 908 909 static void riscv_init_kvm_registers(Object *cpu_obj) 910 { 911 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 912 KVMScratchCPU kvmcpu; 913 914 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 915 return; 916 } 917 918 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 919 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 920 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 921 922 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 923 } 924 925 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 926 KVM_CAP_LAST_INFO 927 }; 928 929 int kvm_arch_get_registers(CPUState *cs) 930 { 931 int ret = 0; 932 933 ret = kvm_riscv_get_regs_core(cs); 934 if (ret) { 935 return ret; 936 } 937 938 ret = kvm_riscv_get_regs_csr(cs); 939 if (ret) { 940 return ret; 941 } 942 943 ret = kvm_riscv_get_regs_fp(cs); 944 if (ret) { 945 return ret; 946 } 947 948 return ret; 949 } 950 951 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 952 { 953 if (cap_has_mp_state) { 954 struct kvm_mp_state mp_state = { 955 .mp_state = state 956 }; 957 958 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 959 if (ret) { 960 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 961 __func__, ret, strerror(-ret)); 962 return -1; 963 } 964 } 965 966 return 0; 967 } 968 969 int kvm_arch_put_registers(CPUState *cs, int level) 970 { 971 int ret = 0; 972 973 ret = kvm_riscv_put_regs_core(cs); 974 if (ret) { 975 return ret; 976 } 977 978 ret = kvm_riscv_put_regs_csr(cs); 979 if (ret) { 980 return ret; 981 } 982 983 ret = kvm_riscv_put_regs_fp(cs); 984 if (ret) { 985 return ret; 986 } 987 988 if (KVM_PUT_RESET_STATE == level) { 989 RISCVCPU *cpu = RISCV_CPU(cs); 990 if (cs->cpu_index == 0) { 991 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 992 } else { 993 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 994 } 995 if (ret) { 996 return ret; 997 } 998 } 999 1000 return ret; 1001 } 1002 1003 int kvm_arch_release_virq_post(int virq) 1004 { 1005 return 0; 1006 } 1007 1008 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1009 uint64_t address, uint32_t data, PCIDevice *dev) 1010 { 1011 return 0; 1012 } 1013 1014 int kvm_arch_destroy_vcpu(CPUState *cs) 1015 { 1016 return 0; 1017 } 1018 1019 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1020 { 1021 return cpu->cpu_index; 1022 } 1023 1024 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1025 RunState state) 1026 { 1027 CPUState *cs = opaque; 1028 1029 if (running) { 1030 kvm_riscv_put_regs_timer(cs); 1031 } else { 1032 kvm_riscv_get_regs_timer(cs); 1033 } 1034 } 1035 1036 void kvm_arch_init_irq_routing(KVMState *s) 1037 { 1038 } 1039 1040 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1041 { 1042 CPURISCVState *env = &cpu->env; 1043 target_ulong reg; 1044 uint64_t id; 1045 int ret; 1046 1047 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1048 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 1049 /* 1050 * cfg.mvendorid is an uint32 but a target_ulong will 1051 * be written. Assign it to a target_ulong var to avoid 1052 * writing pieces of other cpu->cfg fields in the reg. 1053 */ 1054 reg = cpu->cfg.mvendorid; 1055 ret = kvm_set_one_reg(cs, id, ®); 1056 if (ret != 0) { 1057 return ret; 1058 } 1059 1060 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1061 KVM_REG_RISCV_CONFIG_REG(marchid)); 1062 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1063 if (ret != 0) { 1064 return ret; 1065 } 1066 1067 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1068 KVM_REG_RISCV_CONFIG_REG(mimpid)); 1069 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1070 1071 return ret; 1072 } 1073 1074 int kvm_arch_init_vcpu(CPUState *cs) 1075 { 1076 int ret = 0; 1077 RISCVCPU *cpu = RISCV_CPU(cs); 1078 1079 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1080 1081 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1082 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1083 if (ret != 0) { 1084 return ret; 1085 } 1086 } 1087 1088 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1089 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1090 1091 return ret; 1092 } 1093 1094 int kvm_arch_msi_data_to_gsi(uint32_t data) 1095 { 1096 abort(); 1097 } 1098 1099 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1100 int vector, PCIDevice *dev) 1101 { 1102 return 0; 1103 } 1104 1105 int kvm_arch_get_default_type(MachineState *ms) 1106 { 1107 return 0; 1108 } 1109 1110 int kvm_arch_init(MachineState *ms, KVMState *s) 1111 { 1112 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1113 return 0; 1114 } 1115 1116 int kvm_arch_irqchip_create(KVMState *s) 1117 { 1118 if (kvm_kernel_irqchip_split()) { 1119 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1120 exit(1); 1121 } 1122 1123 /* 1124 * We can create the VAIA using the newer device control API. 1125 */ 1126 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1127 } 1128 1129 int kvm_arch_process_async_events(CPUState *cs) 1130 { 1131 return 0; 1132 } 1133 1134 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1135 { 1136 } 1137 1138 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1139 { 1140 return MEMTXATTRS_UNSPECIFIED; 1141 } 1142 1143 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1144 { 1145 return true; 1146 } 1147 1148 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1149 { 1150 int ret = 0; 1151 unsigned char ch; 1152 switch (run->riscv_sbi.extension_id) { 1153 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1154 ch = run->riscv_sbi.args[0]; 1155 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1156 break; 1157 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1158 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1159 if (ret == sizeof(ch)) { 1160 run->riscv_sbi.ret[0] = ch; 1161 } else { 1162 run->riscv_sbi.ret[0] = -1; 1163 } 1164 ret = 0; 1165 break; 1166 default: 1167 qemu_log_mask(LOG_UNIMP, 1168 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1169 __func__, run->riscv_sbi.extension_id); 1170 ret = -1; 1171 break; 1172 } 1173 return ret; 1174 } 1175 1176 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1177 { 1178 int ret = 0; 1179 switch (run->exit_reason) { 1180 case KVM_EXIT_RISCV_SBI: 1181 ret = kvm_riscv_handle_sbi(cs, run); 1182 break; 1183 default: 1184 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1185 __func__, run->exit_reason); 1186 ret = -1; 1187 break; 1188 } 1189 return ret; 1190 } 1191 1192 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1193 { 1194 CPURISCVState *env = &cpu->env; 1195 int i; 1196 1197 if (!kvm_enabled()) { 1198 return; 1199 } 1200 for (i = 0; i < 32; i++) { 1201 env->gpr[i] = 0; 1202 } 1203 env->pc = cpu->env.kernel_addr; 1204 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1205 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1206 env->satp = 0; 1207 env->mie = 0; 1208 env->stvec = 0; 1209 env->sscratch = 0; 1210 env->sepc = 0; 1211 env->scause = 0; 1212 env->stval = 0; 1213 env->mip = 0; 1214 } 1215 1216 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1217 { 1218 int ret; 1219 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1220 1221 if (irq != IRQ_S_EXT) { 1222 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1223 abort(); 1224 } 1225 1226 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1227 if (ret < 0) { 1228 perror("Set irq failed"); 1229 abort(); 1230 } 1231 } 1232 1233 bool kvm_arch_cpu_check_are_resettable(void) 1234 { 1235 return true; 1236 } 1237 1238 static int aia_mode; 1239 1240 static const char *kvm_aia_mode_str(uint64_t mode) 1241 { 1242 switch (mode) { 1243 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1244 return "emul"; 1245 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1246 return "hwaccel"; 1247 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1248 default: 1249 return "auto"; 1250 }; 1251 } 1252 1253 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1254 { 1255 return g_strdup(kvm_aia_mode_str(aia_mode)); 1256 } 1257 1258 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1259 { 1260 if (!strcmp(val, "emul")) { 1261 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1262 } else if (!strcmp(val, "hwaccel")) { 1263 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1264 } else if (!strcmp(val, "auto")) { 1265 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1266 } else { 1267 error_setg(errp, "Invalid KVM AIA mode"); 1268 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1269 } 1270 } 1271 1272 void kvm_arch_accel_class_init(ObjectClass *oc) 1273 { 1274 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1275 riscv_set_kvm_aia); 1276 object_class_property_set_description(oc, "riscv-aia", 1277 "Set KVM AIA mode. Valid values are " 1278 "emul, hwaccel, and auto. Default " 1279 "is auto."); 1280 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1281 "auto"); 1282 } 1283 1284 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1285 uint64_t aia_irq_num, uint64_t aia_msi_num, 1286 uint64_t aplic_base, uint64_t imsic_base, 1287 uint64_t guest_num) 1288 { 1289 int ret, i; 1290 int aia_fd = -1; 1291 uint64_t default_aia_mode; 1292 uint64_t socket_count = riscv_socket_count(machine); 1293 uint64_t max_hart_per_socket = 0; 1294 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1295 uint64_t socket_bits, hart_bits, guest_bits; 1296 1297 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1298 1299 if (aia_fd < 0) { 1300 error_report("Unable to create in-kernel irqchip"); 1301 exit(1); 1302 } 1303 1304 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1305 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1306 &default_aia_mode, false, NULL); 1307 if (ret < 0) { 1308 error_report("KVM AIA: failed to get current KVM AIA mode"); 1309 exit(1); 1310 } 1311 qemu_log("KVM AIA: default mode is %s\n", 1312 kvm_aia_mode_str(default_aia_mode)); 1313 1314 if (default_aia_mode != aia_mode) { 1315 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1316 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1317 &aia_mode, true, NULL); 1318 if (ret < 0) 1319 warn_report("KVM AIA: failed to set KVM AIA mode"); 1320 else 1321 qemu_log("KVM AIA: set current mode to %s\n", 1322 kvm_aia_mode_str(aia_mode)); 1323 } 1324 1325 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1326 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1327 &aia_irq_num, true, NULL); 1328 if (ret < 0) { 1329 error_report("KVM AIA: failed to set number of input irq lines"); 1330 exit(1); 1331 } 1332 1333 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1334 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1335 &aia_msi_num, true, NULL); 1336 if (ret < 0) { 1337 error_report("KVM AIA: failed to set number of msi"); 1338 exit(1); 1339 } 1340 1341 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1342 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1343 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1344 &socket_bits, true, NULL); 1345 if (ret < 0) { 1346 error_report("KVM AIA: failed to set group_bits"); 1347 exit(1); 1348 } 1349 1350 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1351 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1352 &group_shift, true, NULL); 1353 if (ret < 0) { 1354 error_report("KVM AIA: failed to set group_shift"); 1355 exit(1); 1356 } 1357 1358 guest_bits = guest_num == 0 ? 0 : 1359 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1360 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1361 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1362 &guest_bits, true, NULL); 1363 if (ret < 0) { 1364 error_report("KVM AIA: failed to set guest_bits"); 1365 exit(1); 1366 } 1367 1368 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1369 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1370 &aplic_base, true, NULL); 1371 if (ret < 0) { 1372 error_report("KVM AIA: failed to set the base address of APLIC"); 1373 exit(1); 1374 } 1375 1376 for (socket = 0; socket < socket_count; socket++) { 1377 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1378 hart_count = riscv_socket_hart_count(machine, socket); 1379 base_hart = riscv_socket_first_hartid(machine, socket); 1380 1381 if (max_hart_per_socket < hart_count) { 1382 max_hart_per_socket = hart_count; 1383 } 1384 1385 for (i = 0; i < hart_count; i++) { 1386 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1387 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1388 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1389 &imsic_addr, true, NULL); 1390 if (ret < 0) { 1391 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1392 exit(1); 1393 } 1394 } 1395 } 1396 1397 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1398 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1399 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1400 &hart_bits, true, NULL); 1401 if (ret < 0) { 1402 error_report("KVM AIA: failed to set hart_bits"); 1403 exit(1); 1404 } 1405 1406 if (kvm_has_gsi_routing()) { 1407 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1408 /* KVM AIA only has one APLIC instance */ 1409 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1410 } 1411 kvm_gsi_routing_allowed = true; 1412 kvm_irqchip_commit_routes(kvm_state); 1413 } 1414 1415 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1416 KVM_DEV_RISCV_AIA_CTRL_INIT, 1417 NULL, true, NULL); 1418 if (ret < 0) { 1419 error_report("KVM AIA: initialized fail"); 1420 exit(1); 1421 } 1422 1423 kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); 1424 } 1425 1426 static void kvm_cpu_instance_init(CPUState *cs) 1427 { 1428 Object *obj = OBJECT(RISCV_CPU(cs)); 1429 DeviceState *dev = DEVICE(obj); 1430 1431 riscv_init_kvm_registers(obj); 1432 1433 kvm_riscv_add_cpu_user_properties(obj); 1434 1435 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1436 /* Check if we have a specific KVM handler for the option */ 1437 if (object_property_find(obj, prop->name)) { 1438 continue; 1439 } 1440 qdev_property_add_static(dev, prop); 1441 } 1442 } 1443 1444 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1445 { 1446 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1447 1448 acc->cpu_instance_init = kvm_cpu_instance_init; 1449 } 1450 1451 static const TypeInfo kvm_cpu_accel_type_info = { 1452 .name = ACCEL_CPU_NAME("kvm"), 1453 1454 .parent = TYPE_ACCEL_CPU, 1455 .class_init = kvm_cpu_accel_class_init, 1456 .abstract = true, 1457 }; 1458 static void kvm_cpu_accel_register_types(void) 1459 { 1460 type_register_static(&kvm_cpu_accel_type_info); 1461 } 1462 type_init(kvm_cpu_accel_register_types); 1463 1464 static void riscv_host_cpu_init(Object *obj) 1465 { 1466 CPURISCVState *env = &RISCV_CPU(obj)->env; 1467 1468 #if defined(TARGET_RISCV32) 1469 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1470 #elif defined(TARGET_RISCV64) 1471 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1472 #endif 1473 } 1474 1475 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1476 { 1477 .name = TYPE_RISCV_CPU_HOST, 1478 .parent = TYPE_RISCV_CPU, 1479 .instance_init = riscv_host_cpu_init, 1480 } 1481 }; 1482 1483 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1484