1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/kvm.h" 32 #include "sysemu/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "hw/core/accel-cpu.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "exec/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/migration.h" 48 #include "sysemu/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 #define RISCV_CORE_REG(env, name) \ 90 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 91 KVM_REG_RISCV_CORE_REG(name)) 92 93 #define RISCV_CSR_REG(env, name) \ 94 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 95 KVM_REG_RISCV_CSR_REG(name)) 96 97 #define RISCV_CONFIG_REG(env, name) \ 98 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 99 KVM_REG_RISCV_CONFIG_REG(name)) 100 101 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 102 KVM_REG_RISCV_TIMER_REG(name)) 103 104 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 105 106 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 107 108 #define RISCV_VECTOR_CSR_REG(env, name) \ 109 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ 110 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 111 112 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 113 do { \ 114 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 115 if (_ret) { \ 116 return _ret; \ 117 } \ 118 } while (0) 119 120 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 121 do { \ 122 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 123 if (_ret) { \ 124 return _ret; \ 125 } \ 126 } while (0) 127 128 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 129 do { \ 130 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 131 if (ret) { \ 132 abort(); \ 133 } \ 134 } while (0) 135 136 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 137 do { \ 138 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 139 if (ret) { \ 140 abort(); \ 141 } \ 142 } while (0) 143 144 typedef struct KVMCPUConfig { 145 const char *name; 146 const char *description; 147 target_ulong offset; 148 int kvm_reg_id; 149 bool user_set; 150 bool supported; 151 } KVMCPUConfig; 152 153 #define KVM_MISA_CFG(_bit, _reg_id) \ 154 {.offset = _bit, .kvm_reg_id = _reg_id} 155 156 /* KVM ISA extensions */ 157 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 158 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 159 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 160 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 161 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 162 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 163 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 164 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 165 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 166 }; 167 168 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 169 const char *name, 170 void *opaque, Error **errp) 171 { 172 KVMCPUConfig *misa_ext_cfg = opaque; 173 target_ulong misa_bit = misa_ext_cfg->offset; 174 RISCVCPU *cpu = RISCV_CPU(obj); 175 CPURISCVState *env = &cpu->env; 176 bool value = env->misa_ext_mask & misa_bit; 177 178 visit_type_bool(v, name, &value, errp); 179 } 180 181 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 182 const char *name, 183 void *opaque, Error **errp) 184 { 185 KVMCPUConfig *misa_ext_cfg = opaque; 186 target_ulong misa_bit = misa_ext_cfg->offset; 187 RISCVCPU *cpu = RISCV_CPU(obj); 188 CPURISCVState *env = &cpu->env; 189 bool value, host_bit; 190 191 if (!visit_type_bool(v, name, &value, errp)) { 192 return; 193 } 194 195 host_bit = env->misa_ext_mask & misa_bit; 196 197 if (value == host_bit) { 198 return; 199 } 200 201 if (!value) { 202 misa_ext_cfg->user_set = true; 203 return; 204 } 205 206 /* 207 * Forbid users to enable extensions that aren't 208 * available in the hart. 209 */ 210 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 211 "enabled in the host", misa_ext_cfg->name); 212 } 213 214 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 215 { 216 CPURISCVState *env = &cpu->env; 217 uint64_t id, reg; 218 int i, ret; 219 220 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 221 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 222 target_ulong misa_bit = misa_cfg->offset; 223 224 if (!misa_cfg->user_set) { 225 continue; 226 } 227 228 /* If we're here we're going to disable the MISA bit */ 229 reg = 0; 230 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 231 misa_cfg->kvm_reg_id); 232 ret = kvm_set_one_reg(cs, id, ®); 233 if (ret != 0) { 234 /* 235 * We're not checking for -EINVAL because if the bit is about 236 * to be disabled, it means that it was already enabled by 237 * KVM. We determined that by fetching the 'isa' register 238 * during init() time. Any error at this point is worth 239 * aborting. 240 */ 241 error_report("Unable to set KVM reg %s, error %d", 242 misa_cfg->name, ret); 243 exit(EXIT_FAILURE); 244 } 245 env->misa_ext &= ~misa_bit; 246 } 247 } 248 249 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 250 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 251 .kvm_reg_id = _reg_id} 252 253 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 254 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 255 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 256 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 257 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 258 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 259 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 260 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 261 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 262 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 263 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 264 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 265 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 266 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 267 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 268 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 269 }; 270 271 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 272 { 273 return (void *)&cpu->cfg + kvmcfg->offset; 274 } 275 276 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 277 uint32_t val) 278 { 279 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 280 281 *ext_enabled = val; 282 } 283 284 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 285 KVMCPUConfig *multi_ext) 286 { 287 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 288 289 return *ext_enabled; 290 } 291 292 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 293 const char *name, 294 void *opaque, Error **errp) 295 { 296 KVMCPUConfig *multi_ext_cfg = opaque; 297 RISCVCPU *cpu = RISCV_CPU(obj); 298 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 299 300 visit_type_bool(v, name, &value, errp); 301 } 302 303 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 304 const char *name, 305 void *opaque, Error **errp) 306 { 307 KVMCPUConfig *multi_ext_cfg = opaque; 308 RISCVCPU *cpu = RISCV_CPU(obj); 309 bool value, host_val; 310 311 if (!visit_type_bool(v, name, &value, errp)) { 312 return; 313 } 314 315 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 316 317 /* 318 * Ignore if the user is setting the same value 319 * as the host. 320 */ 321 if (value == host_val) { 322 return; 323 } 324 325 if (!multi_ext_cfg->supported) { 326 /* 327 * Error out if the user is trying to enable an 328 * extension that KVM doesn't support. Ignore 329 * option otherwise. 330 */ 331 if (value) { 332 error_setg(errp, "KVM does not support disabling extension %s", 333 multi_ext_cfg->name); 334 } 335 336 return; 337 } 338 339 multi_ext_cfg->user_set = true; 340 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 341 } 342 343 static KVMCPUConfig kvm_cbom_blocksize = { 344 .name = "cbom_blocksize", 345 .offset = CPU_CFG_OFFSET(cbom_blocksize), 346 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 347 }; 348 349 static KVMCPUConfig kvm_cboz_blocksize = { 350 .name = "cboz_blocksize", 351 .offset = CPU_CFG_OFFSET(cboz_blocksize), 352 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 353 }; 354 355 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 356 const char *name, 357 void *opaque, Error **errp) 358 { 359 KVMCPUConfig *cbomz_cfg = opaque; 360 RISCVCPU *cpu = RISCV_CPU(obj); 361 uint16_t value, *host_val; 362 363 if (!visit_type_uint16(v, name, &value, errp)) { 364 return; 365 } 366 367 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 368 369 if (value != *host_val) { 370 error_report("Unable to set %s to a different value than " 371 "the host (%u)", 372 cbomz_cfg->name, *host_val); 373 exit(EXIT_FAILURE); 374 } 375 376 cbomz_cfg->user_set = true; 377 } 378 379 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 380 { 381 CPURISCVState *env = &cpu->env; 382 uint64_t id, reg; 383 int i, ret; 384 385 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 386 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 387 388 if (!multi_ext_cfg->user_set) { 389 continue; 390 } 391 392 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 393 multi_ext_cfg->kvm_reg_id); 394 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 395 ret = kvm_set_one_reg(cs, id, ®); 396 if (ret != 0) { 397 error_report("Unable to %s extension %s in KVM, error %d", 398 reg ? "enable" : "disable", 399 multi_ext_cfg->name, ret); 400 exit(EXIT_FAILURE); 401 } 402 } 403 } 404 405 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 406 const char *name, 407 void *opaque, Error **errp) 408 { 409 bool value = false; 410 411 visit_type_bool(v, name, &value, errp); 412 } 413 414 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 415 const char *name, 416 void *opaque, Error **errp) 417 { 418 const char *propname = opaque; 419 bool value; 420 421 if (!visit_type_bool(v, name, &value, errp)) { 422 return; 423 } 424 425 if (value) { 426 error_setg(errp, "'%s' is not available with KVM", 427 propname); 428 } 429 } 430 431 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 432 { 433 /* Check if KVM created the property already */ 434 if (object_property_find(obj, prop_name)) { 435 return; 436 } 437 438 /* 439 * Set the default to disabled for every extension 440 * unknown to KVM and error out if the user attempts 441 * to enable any of them. 442 */ 443 object_property_add(obj, prop_name, "bool", 444 cpu_get_cfg_unavailable, 445 cpu_set_cfg_unavailable, 446 NULL, (void *)prop_name); 447 } 448 449 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 450 const RISCVCPUMultiExtConfig *array) 451 { 452 const RISCVCPUMultiExtConfig *prop; 453 454 g_assert(array); 455 456 for (prop = array; prop && prop->name; prop++) { 457 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 458 } 459 } 460 461 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 462 { 463 int i; 464 465 riscv_add_satp_mode_properties(cpu_obj); 466 467 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 468 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 469 int bit = misa_cfg->offset; 470 471 misa_cfg->name = riscv_get_misa_ext_name(bit); 472 misa_cfg->description = riscv_get_misa_ext_description(bit); 473 474 object_property_add(cpu_obj, misa_cfg->name, "bool", 475 kvm_cpu_get_misa_ext_cfg, 476 kvm_cpu_set_misa_ext_cfg, 477 NULL, misa_cfg); 478 object_property_set_description(cpu_obj, misa_cfg->name, 479 misa_cfg->description); 480 } 481 482 for (i = 0; misa_bits[i] != 0; i++) { 483 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 484 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 485 } 486 487 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 488 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 489 490 object_property_add(cpu_obj, multi_cfg->name, "bool", 491 kvm_cpu_get_multi_ext_cfg, 492 kvm_cpu_set_multi_ext_cfg, 493 NULL, multi_cfg); 494 } 495 496 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 497 NULL, kvm_cpu_set_cbomz_blksize, 498 NULL, &kvm_cboz_blocksize); 499 500 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 501 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 502 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 503 504 /* We don't have the needed KVM support for profiles */ 505 for (i = 0; riscv_profiles[i] != NULL; i++) { 506 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 507 } 508 } 509 510 static int kvm_riscv_get_regs_core(CPUState *cs) 511 { 512 int ret = 0; 513 int i; 514 target_ulong reg; 515 CPURISCVState *env = &RISCV_CPU(cs)->env; 516 517 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 518 if (ret) { 519 return ret; 520 } 521 env->pc = reg; 522 523 for (i = 1; i < 32; i++) { 524 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 525 ret = kvm_get_one_reg(cs, id, ®); 526 if (ret) { 527 return ret; 528 } 529 env->gpr[i] = reg; 530 } 531 532 return ret; 533 } 534 535 static int kvm_riscv_put_regs_core(CPUState *cs) 536 { 537 int ret = 0; 538 int i; 539 target_ulong reg; 540 CPURISCVState *env = &RISCV_CPU(cs)->env; 541 542 reg = env->pc; 543 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 544 if (ret) { 545 return ret; 546 } 547 548 for (i = 1; i < 32; i++) { 549 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 550 reg = env->gpr[i]; 551 ret = kvm_set_one_reg(cs, id, ®); 552 if (ret) { 553 return ret; 554 } 555 } 556 557 return ret; 558 } 559 560 static int kvm_riscv_get_regs_csr(CPUState *cs) 561 { 562 CPURISCVState *env = &RISCV_CPU(cs)->env; 563 564 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 565 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 566 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 567 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 568 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 569 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 570 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 571 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 572 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 573 574 return 0; 575 } 576 577 static int kvm_riscv_put_regs_csr(CPUState *cs) 578 { 579 CPURISCVState *env = &RISCV_CPU(cs)->env; 580 581 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 582 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 583 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 584 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 585 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 586 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 587 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 588 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 589 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 590 591 return 0; 592 } 593 594 static int kvm_riscv_get_regs_fp(CPUState *cs) 595 { 596 int ret = 0; 597 int i; 598 CPURISCVState *env = &RISCV_CPU(cs)->env; 599 600 if (riscv_has_ext(env, RVD)) { 601 uint64_t reg; 602 for (i = 0; i < 32; i++) { 603 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 604 if (ret) { 605 return ret; 606 } 607 env->fpr[i] = reg; 608 } 609 return ret; 610 } 611 612 if (riscv_has_ext(env, RVF)) { 613 uint32_t reg; 614 for (i = 0; i < 32; i++) { 615 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 616 if (ret) { 617 return ret; 618 } 619 env->fpr[i] = reg; 620 } 621 return ret; 622 } 623 624 return ret; 625 } 626 627 static int kvm_riscv_put_regs_fp(CPUState *cs) 628 { 629 int ret = 0; 630 int i; 631 CPURISCVState *env = &RISCV_CPU(cs)->env; 632 633 if (riscv_has_ext(env, RVD)) { 634 uint64_t reg; 635 for (i = 0; i < 32; i++) { 636 reg = env->fpr[i]; 637 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 638 if (ret) { 639 return ret; 640 } 641 } 642 return ret; 643 } 644 645 if (riscv_has_ext(env, RVF)) { 646 uint32_t reg; 647 for (i = 0; i < 32; i++) { 648 reg = env->fpr[i]; 649 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 650 if (ret) { 651 return ret; 652 } 653 } 654 return ret; 655 } 656 657 return ret; 658 } 659 660 static void kvm_riscv_get_regs_timer(CPUState *cs) 661 { 662 CPURISCVState *env = &RISCV_CPU(cs)->env; 663 664 if (env->kvm_timer_dirty) { 665 return; 666 } 667 668 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 669 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 670 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 671 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 672 673 env->kvm_timer_dirty = true; 674 } 675 676 static void kvm_riscv_put_regs_timer(CPUState *cs) 677 { 678 uint64_t reg; 679 CPURISCVState *env = &RISCV_CPU(cs)->env; 680 681 if (!env->kvm_timer_dirty) { 682 return; 683 } 684 685 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 686 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 687 688 /* 689 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 690 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 691 * doesn't matter that adaping in QEMU now. 692 * TODO If KVM changes, adapt here. 693 */ 694 if (env->kvm_timer_state) { 695 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 696 } 697 698 /* 699 * For now, migration will not work between Hosts with different timer 700 * frequency. Therefore, we should check whether they are the same here 701 * during the migration. 702 */ 703 if (migration_is_running(migrate_get_current()->state)) { 704 KVM_RISCV_GET_TIMER(cs, frequency, reg); 705 if (reg != env->kvm_timer_frequency) { 706 error_report("Dst Hosts timer frequency != Src Hosts"); 707 } 708 } 709 710 env->kvm_timer_dirty = false; 711 } 712 713 static int kvm_riscv_get_regs_vector(CPUState *cs) 714 { 715 CPURISCVState *env = &RISCV_CPU(cs)->env; 716 target_ulong reg; 717 int ret = 0; 718 719 if (!riscv_has_ext(env, RVV)) { 720 return 0; 721 } 722 723 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 724 if (ret) { 725 return ret; 726 } 727 env->vstart = reg; 728 729 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 730 if (ret) { 731 return ret; 732 } 733 env->vl = reg; 734 735 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 736 if (ret) { 737 return ret; 738 } 739 env->vtype = reg; 740 741 return 0; 742 } 743 744 static int kvm_riscv_put_regs_vector(CPUState *cs) 745 { 746 CPURISCVState *env = &RISCV_CPU(cs)->env; 747 target_ulong reg; 748 int ret = 0; 749 750 if (!riscv_has_ext(env, RVV)) { 751 return 0; 752 } 753 754 reg = env->vstart; 755 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 756 if (ret) { 757 return ret; 758 } 759 760 reg = env->vl; 761 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 762 if (ret) { 763 return ret; 764 } 765 766 reg = env->vtype; 767 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 768 769 return ret; 770 } 771 772 typedef struct KVMScratchCPU { 773 int kvmfd; 774 int vmfd; 775 int cpufd; 776 } KVMScratchCPU; 777 778 /* 779 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 780 * from target/arm/kvm.c. 781 */ 782 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 783 { 784 int kvmfd = -1, vmfd = -1, cpufd = -1; 785 786 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 787 if (kvmfd < 0) { 788 goto err; 789 } 790 do { 791 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 792 } while (vmfd == -1 && errno == EINTR); 793 if (vmfd < 0) { 794 goto err; 795 } 796 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 797 if (cpufd < 0) { 798 goto err; 799 } 800 801 scratch->kvmfd = kvmfd; 802 scratch->vmfd = vmfd; 803 scratch->cpufd = cpufd; 804 805 return true; 806 807 err: 808 if (cpufd >= 0) { 809 close(cpufd); 810 } 811 if (vmfd >= 0) { 812 close(vmfd); 813 } 814 if (kvmfd >= 0) { 815 close(kvmfd); 816 } 817 818 return false; 819 } 820 821 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 822 { 823 close(scratch->cpufd); 824 close(scratch->vmfd); 825 close(scratch->kvmfd); 826 } 827 828 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 829 { 830 CPURISCVState *env = &cpu->env; 831 struct kvm_one_reg reg; 832 int ret; 833 834 reg.id = RISCV_CONFIG_REG(env, mvendorid); 835 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 836 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 837 if (ret != 0) { 838 error_report("Unable to retrieve mvendorid from host, error %d", ret); 839 } 840 841 reg.id = RISCV_CONFIG_REG(env, marchid); 842 reg.addr = (uint64_t)&cpu->cfg.marchid; 843 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 844 if (ret != 0) { 845 error_report("Unable to retrieve marchid from host, error %d", ret); 846 } 847 848 reg.id = RISCV_CONFIG_REG(env, mimpid); 849 reg.addr = (uint64_t)&cpu->cfg.mimpid; 850 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 851 if (ret != 0) { 852 error_report("Unable to retrieve mimpid from host, error %d", ret); 853 } 854 } 855 856 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 857 KVMScratchCPU *kvmcpu) 858 { 859 CPURISCVState *env = &cpu->env; 860 struct kvm_one_reg reg; 861 int ret; 862 863 reg.id = RISCV_CONFIG_REG(env, isa); 864 reg.addr = (uint64_t)&env->misa_ext_mask; 865 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 866 867 if (ret) { 868 error_report("Unable to fetch ISA register from KVM, " 869 "error %d", ret); 870 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 871 exit(EXIT_FAILURE); 872 } 873 874 env->misa_ext = env->misa_ext_mask; 875 } 876 877 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 878 KVMCPUConfig *cbomz_cfg) 879 { 880 CPURISCVState *env = &cpu->env; 881 struct kvm_one_reg reg; 882 int ret; 883 884 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 885 cbomz_cfg->kvm_reg_id); 886 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 887 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 888 if (ret != 0) { 889 error_report("Unable to read KVM reg %s, error %d", 890 cbomz_cfg->name, ret); 891 exit(EXIT_FAILURE); 892 } 893 } 894 895 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 896 KVMScratchCPU *kvmcpu) 897 { 898 CPURISCVState *env = &cpu->env; 899 uint64_t val; 900 int i, ret; 901 902 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 903 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 904 struct kvm_one_reg reg; 905 906 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 907 multi_ext_cfg->kvm_reg_id); 908 reg.addr = (uint64_t)&val; 909 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 910 if (ret != 0) { 911 if (errno == EINVAL) { 912 /* Silently default to 'false' if KVM does not support it. */ 913 multi_ext_cfg->supported = false; 914 val = false; 915 } else { 916 error_report("Unable to read ISA_EXT KVM register %s: %s", 917 multi_ext_cfg->name, strerror(errno)); 918 exit(EXIT_FAILURE); 919 } 920 } else { 921 multi_ext_cfg->supported = true; 922 } 923 924 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 925 } 926 927 if (cpu->cfg.ext_zicbom) { 928 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 929 } 930 931 if (cpu->cfg.ext_zicboz) { 932 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 933 } 934 } 935 936 static int uint64_cmp(const void *a, const void *b) 937 { 938 uint64_t val1 = *(const uint64_t *)a; 939 uint64_t val2 = *(const uint64_t *)b; 940 941 if (val1 < val2) { 942 return -1; 943 } 944 945 if (val1 > val2) { 946 return 1; 947 } 948 949 return 0; 950 } 951 952 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 953 { 954 KVMCPUConfig *multi_ext_cfg; 955 struct kvm_one_reg reg; 956 struct kvm_reg_list rl_struct; 957 struct kvm_reg_list *reglist; 958 uint64_t val, reg_id, *reg_search; 959 int i, ret; 960 961 rl_struct.n = 0; 962 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 963 964 /* 965 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 966 * (EINVAL). Use read_legacy() in this case. 967 */ 968 if (errno == EINVAL) { 969 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 970 } else if (errno != E2BIG) { 971 /* 972 * E2BIG is an expected error message for the API since we 973 * don't know the number of registers. The right amount will 974 * be written in rl_struct.n. 975 * 976 * Error out if we get any other errno. 977 */ 978 error_report("Error when accessing get-reg-list: %s", 979 strerror(errno)); 980 exit(EXIT_FAILURE); 981 } 982 983 reglist = g_malloc(sizeof(struct kvm_reg_list) + 984 rl_struct.n * sizeof(uint64_t)); 985 reglist->n = rl_struct.n; 986 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 987 if (ret) { 988 error_report("Error when reading KVM_GET_REG_LIST: %s", 989 strerror(errno)); 990 exit(EXIT_FAILURE); 991 } 992 993 /* sort reglist to use bsearch() */ 994 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 995 996 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 997 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 998 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 999 multi_ext_cfg->kvm_reg_id); 1000 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1001 sizeof(uint64_t), uint64_cmp); 1002 if (!reg_search) { 1003 continue; 1004 } 1005 1006 reg.id = reg_id; 1007 reg.addr = (uint64_t)&val; 1008 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1009 if (ret != 0) { 1010 error_report("Unable to read ISA_EXT KVM register %s: %s", 1011 multi_ext_cfg->name, strerror(errno)); 1012 exit(EXIT_FAILURE); 1013 } 1014 1015 multi_ext_cfg->supported = true; 1016 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1017 } 1018 1019 if (cpu->cfg.ext_zicbom) { 1020 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1021 } 1022 1023 if (cpu->cfg.ext_zicboz) { 1024 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1025 } 1026 } 1027 1028 static void riscv_init_kvm_registers(Object *cpu_obj) 1029 { 1030 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1031 KVMScratchCPU kvmcpu; 1032 1033 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1034 return; 1035 } 1036 1037 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1038 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1039 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1040 1041 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1042 } 1043 1044 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1045 KVM_CAP_LAST_INFO 1046 }; 1047 1048 int kvm_arch_get_registers(CPUState *cs) 1049 { 1050 int ret = 0; 1051 1052 ret = kvm_riscv_get_regs_core(cs); 1053 if (ret) { 1054 return ret; 1055 } 1056 1057 ret = kvm_riscv_get_regs_csr(cs); 1058 if (ret) { 1059 return ret; 1060 } 1061 1062 ret = kvm_riscv_get_regs_fp(cs); 1063 if (ret) { 1064 return ret; 1065 } 1066 1067 ret = kvm_riscv_get_regs_vector(cs); 1068 if (ret) { 1069 return ret; 1070 } 1071 1072 return ret; 1073 } 1074 1075 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1076 { 1077 if (cap_has_mp_state) { 1078 struct kvm_mp_state mp_state = { 1079 .mp_state = state 1080 }; 1081 1082 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1083 if (ret) { 1084 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1085 __func__, ret, strerror(-ret)); 1086 return -1; 1087 } 1088 } 1089 1090 return 0; 1091 } 1092 1093 int kvm_arch_put_registers(CPUState *cs, int level) 1094 { 1095 int ret = 0; 1096 1097 ret = kvm_riscv_put_regs_core(cs); 1098 if (ret) { 1099 return ret; 1100 } 1101 1102 ret = kvm_riscv_put_regs_csr(cs); 1103 if (ret) { 1104 return ret; 1105 } 1106 1107 ret = kvm_riscv_put_regs_fp(cs); 1108 if (ret) { 1109 return ret; 1110 } 1111 1112 ret = kvm_riscv_put_regs_vector(cs); 1113 if (ret) { 1114 return ret; 1115 } 1116 1117 if (KVM_PUT_RESET_STATE == level) { 1118 RISCVCPU *cpu = RISCV_CPU(cs); 1119 if (cs->cpu_index == 0) { 1120 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1121 } else { 1122 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1123 } 1124 if (ret) { 1125 return ret; 1126 } 1127 } 1128 1129 return ret; 1130 } 1131 1132 int kvm_arch_release_virq_post(int virq) 1133 { 1134 return 0; 1135 } 1136 1137 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1138 uint64_t address, uint32_t data, PCIDevice *dev) 1139 { 1140 return 0; 1141 } 1142 1143 int kvm_arch_destroy_vcpu(CPUState *cs) 1144 { 1145 return 0; 1146 } 1147 1148 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1149 { 1150 return cpu->cpu_index; 1151 } 1152 1153 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1154 RunState state) 1155 { 1156 CPUState *cs = opaque; 1157 1158 if (running) { 1159 kvm_riscv_put_regs_timer(cs); 1160 } else { 1161 kvm_riscv_get_regs_timer(cs); 1162 } 1163 } 1164 1165 void kvm_arch_init_irq_routing(KVMState *s) 1166 { 1167 } 1168 1169 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1170 { 1171 CPURISCVState *env = &cpu->env; 1172 target_ulong reg; 1173 uint64_t id; 1174 int ret; 1175 1176 id = RISCV_CONFIG_REG(env, mvendorid); 1177 /* 1178 * cfg.mvendorid is an uint32 but a target_ulong will 1179 * be written. Assign it to a target_ulong var to avoid 1180 * writing pieces of other cpu->cfg fields in the reg. 1181 */ 1182 reg = cpu->cfg.mvendorid; 1183 ret = kvm_set_one_reg(cs, id, ®); 1184 if (ret != 0) { 1185 return ret; 1186 } 1187 1188 id = RISCV_CONFIG_REG(env, marchid); 1189 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1190 if (ret != 0) { 1191 return ret; 1192 } 1193 1194 id = RISCV_CONFIG_REG(env, mimpid); 1195 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1196 1197 return ret; 1198 } 1199 1200 int kvm_arch_init_vcpu(CPUState *cs) 1201 { 1202 int ret = 0; 1203 RISCVCPU *cpu = RISCV_CPU(cs); 1204 1205 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1206 1207 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1208 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1209 if (ret != 0) { 1210 return ret; 1211 } 1212 } 1213 1214 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1215 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1216 1217 return ret; 1218 } 1219 1220 int kvm_arch_msi_data_to_gsi(uint32_t data) 1221 { 1222 abort(); 1223 } 1224 1225 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1226 int vector, PCIDevice *dev) 1227 { 1228 return 0; 1229 } 1230 1231 int kvm_arch_get_default_type(MachineState *ms) 1232 { 1233 return 0; 1234 } 1235 1236 int kvm_arch_init(MachineState *ms, KVMState *s) 1237 { 1238 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1239 return 0; 1240 } 1241 1242 int kvm_arch_irqchip_create(KVMState *s) 1243 { 1244 if (kvm_kernel_irqchip_split()) { 1245 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1246 exit(1); 1247 } 1248 1249 /* 1250 * We can create the VAIA using the newer device control API. 1251 */ 1252 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1253 } 1254 1255 int kvm_arch_process_async_events(CPUState *cs) 1256 { 1257 return 0; 1258 } 1259 1260 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1261 { 1262 } 1263 1264 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1265 { 1266 return MEMTXATTRS_UNSPECIFIED; 1267 } 1268 1269 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1270 { 1271 return true; 1272 } 1273 1274 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1275 { 1276 int ret = 0; 1277 unsigned char ch; 1278 switch (run->riscv_sbi.extension_id) { 1279 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1280 ch = run->riscv_sbi.args[0]; 1281 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1282 break; 1283 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1284 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1285 if (ret == sizeof(ch)) { 1286 run->riscv_sbi.ret[0] = ch; 1287 } else { 1288 run->riscv_sbi.ret[0] = -1; 1289 } 1290 ret = 0; 1291 break; 1292 default: 1293 qemu_log_mask(LOG_UNIMP, 1294 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1295 __func__, run->riscv_sbi.extension_id); 1296 ret = -1; 1297 break; 1298 } 1299 return ret; 1300 } 1301 1302 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1303 { 1304 int ret = 0; 1305 switch (run->exit_reason) { 1306 case KVM_EXIT_RISCV_SBI: 1307 ret = kvm_riscv_handle_sbi(cs, run); 1308 break; 1309 default: 1310 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1311 __func__, run->exit_reason); 1312 ret = -1; 1313 break; 1314 } 1315 return ret; 1316 } 1317 1318 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1319 { 1320 CPURISCVState *env = &cpu->env; 1321 int i; 1322 1323 if (!kvm_enabled()) { 1324 return; 1325 } 1326 for (i = 0; i < 32; i++) { 1327 env->gpr[i] = 0; 1328 } 1329 env->pc = cpu->env.kernel_addr; 1330 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1331 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1332 env->satp = 0; 1333 env->mie = 0; 1334 env->stvec = 0; 1335 env->sscratch = 0; 1336 env->sepc = 0; 1337 env->scause = 0; 1338 env->stval = 0; 1339 env->mip = 0; 1340 } 1341 1342 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1343 { 1344 int ret; 1345 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1346 1347 if (irq != IRQ_S_EXT) { 1348 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1349 abort(); 1350 } 1351 1352 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1353 if (ret < 0) { 1354 perror("Set irq failed"); 1355 abort(); 1356 } 1357 } 1358 1359 bool kvm_arch_cpu_check_are_resettable(void) 1360 { 1361 return true; 1362 } 1363 1364 static int aia_mode; 1365 1366 static const char *kvm_aia_mode_str(uint64_t mode) 1367 { 1368 switch (mode) { 1369 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1370 return "emul"; 1371 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1372 return "hwaccel"; 1373 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1374 default: 1375 return "auto"; 1376 }; 1377 } 1378 1379 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1380 { 1381 return g_strdup(kvm_aia_mode_str(aia_mode)); 1382 } 1383 1384 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1385 { 1386 if (!strcmp(val, "emul")) { 1387 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1388 } else if (!strcmp(val, "hwaccel")) { 1389 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1390 } else if (!strcmp(val, "auto")) { 1391 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1392 } else { 1393 error_setg(errp, "Invalid KVM AIA mode"); 1394 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1395 } 1396 } 1397 1398 void kvm_arch_accel_class_init(ObjectClass *oc) 1399 { 1400 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1401 riscv_set_kvm_aia); 1402 object_class_property_set_description(oc, "riscv-aia", 1403 "Set KVM AIA mode. Valid values are " 1404 "emul, hwaccel, and auto. Default " 1405 "is auto."); 1406 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1407 "auto"); 1408 } 1409 1410 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1411 uint64_t aia_irq_num, uint64_t aia_msi_num, 1412 uint64_t aplic_base, uint64_t imsic_base, 1413 uint64_t guest_num) 1414 { 1415 int ret, i; 1416 int aia_fd = -1; 1417 uint64_t default_aia_mode; 1418 uint64_t socket_count = riscv_socket_count(machine); 1419 uint64_t max_hart_per_socket = 0; 1420 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1421 uint64_t socket_bits, hart_bits, guest_bits; 1422 1423 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1424 1425 if (aia_fd < 0) { 1426 error_report("Unable to create in-kernel irqchip"); 1427 exit(1); 1428 } 1429 1430 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1431 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1432 &default_aia_mode, false, NULL); 1433 if (ret < 0) { 1434 error_report("KVM AIA: failed to get current KVM AIA mode"); 1435 exit(1); 1436 } 1437 qemu_log("KVM AIA: default mode is %s\n", 1438 kvm_aia_mode_str(default_aia_mode)); 1439 1440 if (default_aia_mode != aia_mode) { 1441 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1442 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1443 &aia_mode, true, NULL); 1444 if (ret < 0) 1445 warn_report("KVM AIA: failed to set KVM AIA mode"); 1446 else 1447 qemu_log("KVM AIA: set current mode to %s\n", 1448 kvm_aia_mode_str(aia_mode)); 1449 } 1450 1451 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1452 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1453 &aia_irq_num, true, NULL); 1454 if (ret < 0) { 1455 error_report("KVM AIA: failed to set number of input irq lines"); 1456 exit(1); 1457 } 1458 1459 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1460 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1461 &aia_msi_num, true, NULL); 1462 if (ret < 0) { 1463 error_report("KVM AIA: failed to set number of msi"); 1464 exit(1); 1465 } 1466 1467 1468 if (socket_count > 1) { 1469 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1470 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1471 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1472 &socket_bits, true, NULL); 1473 if (ret < 0) { 1474 error_report("KVM AIA: failed to set group_bits"); 1475 exit(1); 1476 } 1477 1478 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1479 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1480 &group_shift, true, NULL); 1481 if (ret < 0) { 1482 error_report("KVM AIA: failed to set group_shift"); 1483 exit(1); 1484 } 1485 } 1486 1487 guest_bits = guest_num == 0 ? 0 : 1488 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1489 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1490 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1491 &guest_bits, true, NULL); 1492 if (ret < 0) { 1493 error_report("KVM AIA: failed to set guest_bits"); 1494 exit(1); 1495 } 1496 1497 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1498 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1499 &aplic_base, true, NULL); 1500 if (ret < 0) { 1501 error_report("KVM AIA: failed to set the base address of APLIC"); 1502 exit(1); 1503 } 1504 1505 for (socket = 0; socket < socket_count; socket++) { 1506 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1507 hart_count = riscv_socket_hart_count(machine, socket); 1508 base_hart = riscv_socket_first_hartid(machine, socket); 1509 1510 if (max_hart_per_socket < hart_count) { 1511 max_hart_per_socket = hart_count; 1512 } 1513 1514 for (i = 0; i < hart_count; i++) { 1515 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1516 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1517 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1518 &imsic_addr, true, NULL); 1519 if (ret < 0) { 1520 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1521 exit(1); 1522 } 1523 } 1524 } 1525 1526 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1527 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1528 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1529 &hart_bits, true, NULL); 1530 if (ret < 0) { 1531 error_report("KVM AIA: failed to set hart_bits"); 1532 exit(1); 1533 } 1534 1535 if (kvm_has_gsi_routing()) { 1536 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1537 /* KVM AIA only has one APLIC instance */ 1538 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1539 } 1540 kvm_gsi_routing_allowed = true; 1541 kvm_irqchip_commit_routes(kvm_state); 1542 } 1543 1544 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1545 KVM_DEV_RISCV_AIA_CTRL_INIT, 1546 NULL, true, NULL); 1547 if (ret < 0) { 1548 error_report("KVM AIA: initialized fail"); 1549 exit(1); 1550 } 1551 1552 kvm_msi_via_irqfd_allowed = true; 1553 } 1554 1555 static void kvm_cpu_instance_init(CPUState *cs) 1556 { 1557 Object *obj = OBJECT(RISCV_CPU(cs)); 1558 DeviceState *dev = DEVICE(obj); 1559 1560 riscv_init_kvm_registers(obj); 1561 1562 kvm_riscv_add_cpu_user_properties(obj); 1563 1564 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1565 /* Check if we have a specific KVM handler for the option */ 1566 if (object_property_find(obj, prop->name)) { 1567 continue; 1568 } 1569 qdev_property_add_static(dev, prop); 1570 } 1571 } 1572 1573 /* 1574 * We'll get here via the following path: 1575 * 1576 * riscv_cpu_realize() 1577 * -> cpu_exec_realizefn() 1578 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1579 */ 1580 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1581 { 1582 RISCVCPU *cpu = RISCV_CPU(cs); 1583 int ret; 1584 1585 if (riscv_has_ext(&cpu->env, RVV)) { 1586 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1587 if (ret) { 1588 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1589 strerrorname_np(errno)); 1590 return false; 1591 } 1592 } 1593 1594 return true; 1595 } 1596 1597 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1598 { 1599 CPURISCVState *env = &cpu->env; 1600 KVMScratchCPU kvmcpu; 1601 struct kvm_one_reg reg; 1602 uint64_t val; 1603 int ret; 1604 1605 /* short-circuit without spinning the scratch CPU */ 1606 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz) { 1607 return; 1608 } 1609 1610 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1611 error_setg(errp, "Unable to create scratch KVM cpu"); 1612 return; 1613 } 1614 1615 if (cpu->cfg.ext_zicbom && 1616 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 1617 1618 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1619 kvm_cbom_blocksize.kvm_reg_id); 1620 reg.addr = (uint64_t)&val; 1621 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1622 if (ret != 0) { 1623 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 1624 return; 1625 } 1626 1627 if (cpu->cfg.cbom_blocksize != val) { 1628 error_setg(errp, "Unable to set cbom_blocksize to a different " 1629 "value than the host (%lu)", val); 1630 return; 1631 } 1632 } 1633 1634 if (cpu->cfg.ext_zicboz && 1635 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 1636 1637 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1638 kvm_cboz_blocksize.kvm_reg_id); 1639 reg.addr = (uint64_t)&val; 1640 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1641 if (ret != 0) { 1642 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 1643 return; 1644 } 1645 1646 if (cpu->cfg.cboz_blocksize != val) { 1647 error_setg(errp, "Unable to set cboz_blocksize to a different " 1648 "value than the host (%lu)", val); 1649 return; 1650 } 1651 } 1652 1653 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1654 } 1655 1656 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1657 { 1658 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1659 1660 acc->cpu_instance_init = kvm_cpu_instance_init; 1661 acc->cpu_target_realize = kvm_cpu_realize; 1662 } 1663 1664 static const TypeInfo kvm_cpu_accel_type_info = { 1665 .name = ACCEL_CPU_NAME("kvm"), 1666 1667 .parent = TYPE_ACCEL_CPU, 1668 .class_init = kvm_cpu_accel_class_init, 1669 .abstract = true, 1670 }; 1671 static void kvm_cpu_accel_register_types(void) 1672 { 1673 type_register_static(&kvm_cpu_accel_type_info); 1674 } 1675 type_init(kvm_cpu_accel_register_types); 1676 1677 static void riscv_host_cpu_init(Object *obj) 1678 { 1679 CPURISCVState *env = &RISCV_CPU(obj)->env; 1680 1681 #if defined(TARGET_RISCV32) 1682 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1683 #elif defined(TARGET_RISCV64) 1684 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1685 #endif 1686 } 1687 1688 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1689 { 1690 .name = TYPE_RISCV_CPU_HOST, 1691 .parent = TYPE_RISCV_CPU, 1692 .instance_init = riscv_host_cpu_init, 1693 } 1694 }; 1695 1696 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1697