1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ 76 KVM_REG_RISCV_CORE_REG(name)) 77 78 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ 79 KVM_REG_RISCV_CSR_REG(name)) 80 81 #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ 82 KVM_REG_RISCV_TIMER_REG(name)) 83 84 #define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) 85 86 #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) 87 88 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 89 do { \ 90 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 91 if (_ret) { \ 92 return _ret; \ 93 } \ 94 } while (0) 95 96 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 97 do { \ 98 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 99 if (_ret) { \ 100 return _ret; \ 101 } \ 102 } while (0) 103 104 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ 105 do { \ 106 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 107 if (ret) { \ 108 abort(); \ 109 } \ 110 } while (0) 111 112 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ 113 do { \ 114 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 115 if (ret) { \ 116 abort(); \ 117 } \ 118 } while (0) 119 120 typedef struct KVMCPUConfig { 121 const char *name; 122 const char *description; 123 target_ulong offset; 124 int kvm_reg_id; 125 bool user_set; 126 bool supported; 127 } KVMCPUConfig; 128 129 #define KVM_MISA_CFG(_bit, _reg_id) \ 130 {.offset = _bit, .kvm_reg_id = _reg_id} 131 132 /* KVM ISA extensions */ 133 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 134 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 135 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 136 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 137 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 138 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 139 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 140 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 141 }; 142 143 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 144 const char *name, 145 void *opaque, Error **errp) 146 { 147 KVMCPUConfig *misa_ext_cfg = opaque; 148 target_ulong misa_bit = misa_ext_cfg->offset; 149 RISCVCPU *cpu = RISCV_CPU(obj); 150 CPURISCVState *env = &cpu->env; 151 bool value = env->misa_ext_mask & misa_bit; 152 153 visit_type_bool(v, name, &value, errp); 154 } 155 156 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 157 const char *name, 158 void *opaque, Error **errp) 159 { 160 KVMCPUConfig *misa_ext_cfg = opaque; 161 target_ulong misa_bit = misa_ext_cfg->offset; 162 RISCVCPU *cpu = RISCV_CPU(obj); 163 CPURISCVState *env = &cpu->env; 164 bool value, host_bit; 165 166 if (!visit_type_bool(v, name, &value, errp)) { 167 return; 168 } 169 170 host_bit = env->misa_ext_mask & misa_bit; 171 172 if (value == host_bit) { 173 return; 174 } 175 176 if (!value) { 177 misa_ext_cfg->user_set = true; 178 return; 179 } 180 181 /* 182 * Forbid users to enable extensions that aren't 183 * available in the hart. 184 */ 185 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 186 "enabled in the host", misa_ext_cfg->name); 187 } 188 189 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 190 { 191 CPURISCVState *env = &cpu->env; 192 uint64_t id, reg; 193 int i, ret; 194 195 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 196 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 197 target_ulong misa_bit = misa_cfg->offset; 198 199 if (!misa_cfg->user_set) { 200 continue; 201 } 202 203 /* If we're here we're going to disable the MISA bit */ 204 reg = 0; 205 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 206 misa_cfg->kvm_reg_id); 207 ret = kvm_set_one_reg(cs, id, ®); 208 if (ret != 0) { 209 /* 210 * We're not checking for -EINVAL because if the bit is about 211 * to be disabled, it means that it was already enabled by 212 * KVM. We determined that by fetching the 'isa' register 213 * during init() time. Any error at this point is worth 214 * aborting. 215 */ 216 error_report("Unable to set KVM reg %s, error %d", 217 misa_cfg->name, ret); 218 exit(EXIT_FAILURE); 219 } 220 env->misa_ext &= ~misa_bit; 221 } 222 } 223 224 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 225 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 226 .kvm_reg_id = _reg_id} 227 228 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 229 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 230 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 231 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 232 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 233 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 234 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 235 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 236 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 237 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 238 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 239 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 240 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 241 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 242 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 243 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 244 }; 245 246 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 247 { 248 return (void *)&cpu->cfg + kvmcfg->offset; 249 } 250 251 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 252 uint32_t val) 253 { 254 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 255 256 *ext_enabled = val; 257 } 258 259 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 260 KVMCPUConfig *multi_ext) 261 { 262 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 263 264 return *ext_enabled; 265 } 266 267 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 268 const char *name, 269 void *opaque, Error **errp) 270 { 271 KVMCPUConfig *multi_ext_cfg = opaque; 272 RISCVCPU *cpu = RISCV_CPU(obj); 273 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 274 275 visit_type_bool(v, name, &value, errp); 276 } 277 278 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 279 const char *name, 280 void *opaque, Error **errp) 281 { 282 KVMCPUConfig *multi_ext_cfg = opaque; 283 RISCVCPU *cpu = RISCV_CPU(obj); 284 bool value, host_val; 285 286 if (!visit_type_bool(v, name, &value, errp)) { 287 return; 288 } 289 290 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 291 292 /* 293 * Ignore if the user is setting the same value 294 * as the host. 295 */ 296 if (value == host_val) { 297 return; 298 } 299 300 if (!multi_ext_cfg->supported) { 301 /* 302 * Error out if the user is trying to enable an 303 * extension that KVM doesn't support. Ignore 304 * option otherwise. 305 */ 306 if (value) { 307 error_setg(errp, "KVM does not support disabling extension %s", 308 multi_ext_cfg->name); 309 } 310 311 return; 312 } 313 314 multi_ext_cfg->user_set = true; 315 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 316 } 317 318 static KVMCPUConfig kvm_cbom_blocksize = { 319 .name = "cbom_blocksize", 320 .offset = CPU_CFG_OFFSET(cbom_blocksize), 321 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 322 }; 323 324 static KVMCPUConfig kvm_cboz_blocksize = { 325 .name = "cboz_blocksize", 326 .offset = CPU_CFG_OFFSET(cboz_blocksize), 327 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 328 }; 329 330 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 331 const char *name, 332 void *opaque, Error **errp) 333 { 334 KVMCPUConfig *cbomz_cfg = opaque; 335 RISCVCPU *cpu = RISCV_CPU(obj); 336 uint16_t value, *host_val; 337 338 if (!visit_type_uint16(v, name, &value, errp)) { 339 return; 340 } 341 342 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 343 344 if (value != *host_val) { 345 error_report("Unable to set %s to a different value than " 346 "the host (%u)", 347 cbomz_cfg->name, *host_val); 348 exit(EXIT_FAILURE); 349 } 350 351 cbomz_cfg->user_set = true; 352 } 353 354 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 355 { 356 CPURISCVState *env = &cpu->env; 357 uint64_t id, reg; 358 int i, ret; 359 360 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 361 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 362 363 if (!multi_ext_cfg->user_set) { 364 continue; 365 } 366 367 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 368 multi_ext_cfg->kvm_reg_id); 369 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 370 ret = kvm_set_one_reg(cs, id, ®); 371 if (ret != 0) { 372 error_report("Unable to %s extension %s in KVM, error %d", 373 reg ? "enable" : "disable", 374 multi_ext_cfg->name, ret); 375 exit(EXIT_FAILURE); 376 } 377 } 378 } 379 380 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 381 const char *name, 382 void *opaque, Error **errp) 383 { 384 bool value = false; 385 386 visit_type_bool(v, name, &value, errp); 387 } 388 389 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 390 const char *name, 391 void *opaque, Error **errp) 392 { 393 const char *propname = opaque; 394 bool value; 395 396 if (!visit_type_bool(v, name, &value, errp)) { 397 return; 398 } 399 400 if (value) { 401 error_setg(errp, "extension %s is not available with KVM", 402 propname); 403 } 404 } 405 406 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 407 { 408 /* Check if KVM created the property already */ 409 if (object_property_find(obj, prop_name)) { 410 return; 411 } 412 413 /* 414 * Set the default to disabled for every extension 415 * unknown to KVM and error out if the user attempts 416 * to enable any of them. 417 */ 418 object_property_add(obj, prop_name, "bool", 419 cpu_get_cfg_unavailable, 420 cpu_set_cfg_unavailable, 421 NULL, (void *)prop_name); 422 } 423 424 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 425 const RISCVCPUMultiExtConfig *array) 426 { 427 const RISCVCPUMultiExtConfig *prop; 428 429 g_assert(array); 430 431 for (prop = array; prop && prop->name; prop++) { 432 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 433 } 434 } 435 436 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 437 { 438 int i; 439 440 riscv_add_satp_mode_properties(cpu_obj); 441 442 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 443 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 444 int bit = misa_cfg->offset; 445 446 misa_cfg->name = riscv_get_misa_ext_name(bit); 447 misa_cfg->description = riscv_get_misa_ext_description(bit); 448 449 object_property_add(cpu_obj, misa_cfg->name, "bool", 450 kvm_cpu_get_misa_ext_cfg, 451 kvm_cpu_set_misa_ext_cfg, 452 NULL, misa_cfg); 453 object_property_set_description(cpu_obj, misa_cfg->name, 454 misa_cfg->description); 455 } 456 457 for (i = 0; misa_bits[i] != 0; i++) { 458 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 459 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 460 } 461 462 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 463 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 464 465 object_property_add(cpu_obj, multi_cfg->name, "bool", 466 kvm_cpu_get_multi_ext_cfg, 467 kvm_cpu_set_multi_ext_cfg, 468 NULL, multi_cfg); 469 } 470 471 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 472 NULL, kvm_cpu_set_cbomz_blksize, 473 NULL, &kvm_cbom_blocksize); 474 475 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 476 NULL, kvm_cpu_set_cbomz_blksize, 477 NULL, &kvm_cboz_blocksize); 478 479 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 480 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 481 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 482 } 483 484 static int kvm_riscv_get_regs_core(CPUState *cs) 485 { 486 int ret = 0; 487 int i; 488 target_ulong reg; 489 CPURISCVState *env = &RISCV_CPU(cs)->env; 490 491 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 492 if (ret) { 493 return ret; 494 } 495 env->pc = reg; 496 497 for (i = 1; i < 32; i++) { 498 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 499 ret = kvm_get_one_reg(cs, id, ®); 500 if (ret) { 501 return ret; 502 } 503 env->gpr[i] = reg; 504 } 505 506 return ret; 507 } 508 509 static int kvm_riscv_put_regs_core(CPUState *cs) 510 { 511 int ret = 0; 512 int i; 513 target_ulong reg; 514 CPURISCVState *env = &RISCV_CPU(cs)->env; 515 516 reg = env->pc; 517 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 518 if (ret) { 519 return ret; 520 } 521 522 for (i = 1; i < 32; i++) { 523 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 524 reg = env->gpr[i]; 525 ret = kvm_set_one_reg(cs, id, ®); 526 if (ret) { 527 return ret; 528 } 529 } 530 531 return ret; 532 } 533 534 static int kvm_riscv_get_regs_csr(CPUState *cs) 535 { 536 CPURISCVState *env = &RISCV_CPU(cs)->env; 537 538 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 539 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 540 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 541 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 542 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 543 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 544 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 545 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 546 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 547 548 return 0; 549 } 550 551 static int kvm_riscv_put_regs_csr(CPUState *cs) 552 { 553 CPURISCVState *env = &RISCV_CPU(cs)->env; 554 555 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 556 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 557 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 558 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 559 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 560 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 561 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 562 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 563 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 564 565 return 0; 566 } 567 568 static int kvm_riscv_get_regs_fp(CPUState *cs) 569 { 570 int ret = 0; 571 int i; 572 CPURISCVState *env = &RISCV_CPU(cs)->env; 573 574 if (riscv_has_ext(env, RVD)) { 575 uint64_t reg; 576 for (i = 0; i < 32; i++) { 577 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 578 if (ret) { 579 return ret; 580 } 581 env->fpr[i] = reg; 582 } 583 return ret; 584 } 585 586 if (riscv_has_ext(env, RVF)) { 587 uint32_t reg; 588 for (i = 0; i < 32; i++) { 589 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 590 if (ret) { 591 return ret; 592 } 593 env->fpr[i] = reg; 594 } 595 return ret; 596 } 597 598 return ret; 599 } 600 601 static int kvm_riscv_put_regs_fp(CPUState *cs) 602 { 603 int ret = 0; 604 int i; 605 CPURISCVState *env = &RISCV_CPU(cs)->env; 606 607 if (riscv_has_ext(env, RVD)) { 608 uint64_t reg; 609 for (i = 0; i < 32; i++) { 610 reg = env->fpr[i]; 611 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 612 if (ret) { 613 return ret; 614 } 615 } 616 return ret; 617 } 618 619 if (riscv_has_ext(env, RVF)) { 620 uint32_t reg; 621 for (i = 0; i < 32; i++) { 622 reg = env->fpr[i]; 623 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 624 if (ret) { 625 return ret; 626 } 627 } 628 return ret; 629 } 630 631 return ret; 632 } 633 634 static void kvm_riscv_get_regs_timer(CPUState *cs) 635 { 636 CPURISCVState *env = &RISCV_CPU(cs)->env; 637 638 if (env->kvm_timer_dirty) { 639 return; 640 } 641 642 KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); 643 KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); 644 KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); 645 KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); 646 647 env->kvm_timer_dirty = true; 648 } 649 650 static void kvm_riscv_put_regs_timer(CPUState *cs) 651 { 652 uint64_t reg; 653 CPURISCVState *env = &RISCV_CPU(cs)->env; 654 655 if (!env->kvm_timer_dirty) { 656 return; 657 } 658 659 KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); 660 KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); 661 662 /* 663 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 664 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 665 * doesn't matter that adaping in QEMU now. 666 * TODO If KVM changes, adapt here. 667 */ 668 if (env->kvm_timer_state) { 669 KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); 670 } 671 672 /* 673 * For now, migration will not work between Hosts with different timer 674 * frequency. Therefore, we should check whether they are the same here 675 * during the migration. 676 */ 677 if (migration_is_running(migrate_get_current()->state)) { 678 KVM_RISCV_GET_TIMER(cs, env, frequency, reg); 679 if (reg != env->kvm_timer_frequency) { 680 error_report("Dst Hosts timer frequency != Src Hosts"); 681 } 682 } 683 684 env->kvm_timer_dirty = false; 685 } 686 687 typedef struct KVMScratchCPU { 688 int kvmfd; 689 int vmfd; 690 int cpufd; 691 } KVMScratchCPU; 692 693 /* 694 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 695 * from target/arm/kvm.c. 696 */ 697 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 698 { 699 int kvmfd = -1, vmfd = -1, cpufd = -1; 700 701 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 702 if (kvmfd < 0) { 703 goto err; 704 } 705 do { 706 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 707 } while (vmfd == -1 && errno == EINTR); 708 if (vmfd < 0) { 709 goto err; 710 } 711 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 712 if (cpufd < 0) { 713 goto err; 714 } 715 716 scratch->kvmfd = kvmfd; 717 scratch->vmfd = vmfd; 718 scratch->cpufd = cpufd; 719 720 return true; 721 722 err: 723 if (cpufd >= 0) { 724 close(cpufd); 725 } 726 if (vmfd >= 0) { 727 close(vmfd); 728 } 729 if (kvmfd >= 0) { 730 close(kvmfd); 731 } 732 733 return false; 734 } 735 736 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 737 { 738 close(scratch->cpufd); 739 close(scratch->vmfd); 740 close(scratch->kvmfd); 741 } 742 743 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 744 { 745 CPURISCVState *env = &cpu->env; 746 struct kvm_one_reg reg; 747 int ret; 748 749 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 750 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 751 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 752 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 753 if (ret != 0) { 754 error_report("Unable to retrieve mvendorid from host, error %d", ret); 755 } 756 757 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 758 KVM_REG_RISCV_CONFIG_REG(marchid)); 759 reg.addr = (uint64_t)&cpu->cfg.marchid; 760 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 761 if (ret != 0) { 762 error_report("Unable to retrieve marchid from host, error %d", ret); 763 } 764 765 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 766 KVM_REG_RISCV_CONFIG_REG(mimpid)); 767 reg.addr = (uint64_t)&cpu->cfg.mimpid; 768 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 769 if (ret != 0) { 770 error_report("Unable to retrieve mimpid from host, error %d", ret); 771 } 772 } 773 774 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 775 KVMScratchCPU *kvmcpu) 776 { 777 CPURISCVState *env = &cpu->env; 778 struct kvm_one_reg reg; 779 int ret; 780 781 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 782 KVM_REG_RISCV_CONFIG_REG(isa)); 783 reg.addr = (uint64_t)&env->misa_ext_mask; 784 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 785 786 if (ret) { 787 error_report("Unable to fetch ISA register from KVM, " 788 "error %d", ret); 789 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 790 exit(EXIT_FAILURE); 791 } 792 793 env->misa_ext = env->misa_ext_mask; 794 } 795 796 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 797 KVMCPUConfig *cbomz_cfg) 798 { 799 CPURISCVState *env = &cpu->env; 800 struct kvm_one_reg reg; 801 int ret; 802 803 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 804 cbomz_cfg->kvm_reg_id); 805 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 806 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 807 if (ret != 0) { 808 error_report("Unable to read KVM reg %s, error %d", 809 cbomz_cfg->name, ret); 810 exit(EXIT_FAILURE); 811 } 812 } 813 814 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 815 KVMScratchCPU *kvmcpu) 816 { 817 CPURISCVState *env = &cpu->env; 818 uint64_t val; 819 int i, ret; 820 821 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 822 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 823 struct kvm_one_reg reg; 824 825 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 826 multi_ext_cfg->kvm_reg_id); 827 reg.addr = (uint64_t)&val; 828 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 829 if (ret != 0) { 830 if (errno == EINVAL) { 831 /* Silently default to 'false' if KVM does not support it. */ 832 multi_ext_cfg->supported = false; 833 val = false; 834 } else { 835 error_report("Unable to read ISA_EXT KVM register %s: %s", 836 multi_ext_cfg->name, strerror(errno)); 837 exit(EXIT_FAILURE); 838 } 839 } else { 840 multi_ext_cfg->supported = true; 841 } 842 843 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 844 } 845 846 if (cpu->cfg.ext_zicbom) { 847 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 848 } 849 850 if (cpu->cfg.ext_zicboz) { 851 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 852 } 853 } 854 855 static int uint64_cmp(const void *a, const void *b) 856 { 857 uint64_t val1 = *(const uint64_t *)a; 858 uint64_t val2 = *(const uint64_t *)b; 859 860 if (val1 < val2) { 861 return -1; 862 } 863 864 if (val1 > val2) { 865 return 1; 866 } 867 868 return 0; 869 } 870 871 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 872 { 873 KVMCPUConfig *multi_ext_cfg; 874 struct kvm_one_reg reg; 875 struct kvm_reg_list rl_struct; 876 struct kvm_reg_list *reglist; 877 uint64_t val, reg_id, *reg_search; 878 int i, ret; 879 880 rl_struct.n = 0; 881 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 882 883 /* 884 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 885 * (EINVAL). Use read_legacy() in this case. 886 */ 887 if (errno == EINVAL) { 888 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 889 } else if (errno != E2BIG) { 890 /* 891 * E2BIG is an expected error message for the API since we 892 * don't know the number of registers. The right amount will 893 * be written in rl_struct.n. 894 * 895 * Error out if we get any other errno. 896 */ 897 error_report("Error when accessing get-reg-list: %s", 898 strerror(errno)); 899 exit(EXIT_FAILURE); 900 } 901 902 reglist = g_malloc(sizeof(struct kvm_reg_list) + 903 rl_struct.n * sizeof(uint64_t)); 904 reglist->n = rl_struct.n; 905 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 906 if (ret) { 907 error_report("Error when reading KVM_GET_REG_LIST: %s", 908 strerror(errno)); 909 exit(EXIT_FAILURE); 910 } 911 912 /* sort reglist to use bsearch() */ 913 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 914 915 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 916 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 917 reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, 918 multi_ext_cfg->kvm_reg_id); 919 reg_search = bsearch(®_id, reglist->reg, reglist->n, 920 sizeof(uint64_t), uint64_cmp); 921 if (!reg_search) { 922 continue; 923 } 924 925 reg.id = reg_id; 926 reg.addr = (uint64_t)&val; 927 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 928 if (ret != 0) { 929 error_report("Unable to read ISA_EXT KVM register %s: %s", 930 multi_ext_cfg->name, strerror(errno)); 931 exit(EXIT_FAILURE); 932 } 933 934 multi_ext_cfg->supported = true; 935 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 936 } 937 938 if (cpu->cfg.ext_zicbom) { 939 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 940 } 941 942 if (cpu->cfg.ext_zicboz) { 943 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 944 } 945 } 946 947 static void riscv_init_kvm_registers(Object *cpu_obj) 948 { 949 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 950 KVMScratchCPU kvmcpu; 951 952 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 953 return; 954 } 955 956 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 957 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 958 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 959 960 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 961 } 962 963 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 964 KVM_CAP_LAST_INFO 965 }; 966 967 int kvm_arch_get_registers(CPUState *cs) 968 { 969 int ret = 0; 970 971 ret = kvm_riscv_get_regs_core(cs); 972 if (ret) { 973 return ret; 974 } 975 976 ret = kvm_riscv_get_regs_csr(cs); 977 if (ret) { 978 return ret; 979 } 980 981 ret = kvm_riscv_get_regs_fp(cs); 982 if (ret) { 983 return ret; 984 } 985 986 return ret; 987 } 988 989 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 990 { 991 if (cap_has_mp_state) { 992 struct kvm_mp_state mp_state = { 993 .mp_state = state 994 }; 995 996 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 997 if (ret) { 998 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 999 __func__, ret, strerror(-ret)); 1000 return -1; 1001 } 1002 } 1003 1004 return 0; 1005 } 1006 1007 int kvm_arch_put_registers(CPUState *cs, int level) 1008 { 1009 int ret = 0; 1010 1011 ret = kvm_riscv_put_regs_core(cs); 1012 if (ret) { 1013 return ret; 1014 } 1015 1016 ret = kvm_riscv_put_regs_csr(cs); 1017 if (ret) { 1018 return ret; 1019 } 1020 1021 ret = kvm_riscv_put_regs_fp(cs); 1022 if (ret) { 1023 return ret; 1024 } 1025 1026 if (KVM_PUT_RESET_STATE == level) { 1027 RISCVCPU *cpu = RISCV_CPU(cs); 1028 if (cs->cpu_index == 0) { 1029 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1030 } else { 1031 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1032 } 1033 if (ret) { 1034 return ret; 1035 } 1036 } 1037 1038 return ret; 1039 } 1040 1041 int kvm_arch_release_virq_post(int virq) 1042 { 1043 return 0; 1044 } 1045 1046 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1047 uint64_t address, uint32_t data, PCIDevice *dev) 1048 { 1049 return 0; 1050 } 1051 1052 int kvm_arch_destroy_vcpu(CPUState *cs) 1053 { 1054 return 0; 1055 } 1056 1057 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1058 { 1059 return cpu->cpu_index; 1060 } 1061 1062 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1063 RunState state) 1064 { 1065 CPUState *cs = opaque; 1066 1067 if (running) { 1068 kvm_riscv_put_regs_timer(cs); 1069 } else { 1070 kvm_riscv_get_regs_timer(cs); 1071 } 1072 } 1073 1074 void kvm_arch_init_irq_routing(KVMState *s) 1075 { 1076 } 1077 1078 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1079 { 1080 CPURISCVState *env = &cpu->env; 1081 target_ulong reg; 1082 uint64_t id; 1083 int ret; 1084 1085 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1086 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 1087 /* 1088 * cfg.mvendorid is an uint32 but a target_ulong will 1089 * be written. Assign it to a target_ulong var to avoid 1090 * writing pieces of other cpu->cfg fields in the reg. 1091 */ 1092 reg = cpu->cfg.mvendorid; 1093 ret = kvm_set_one_reg(cs, id, ®); 1094 if (ret != 0) { 1095 return ret; 1096 } 1097 1098 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1099 KVM_REG_RISCV_CONFIG_REG(marchid)); 1100 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1101 if (ret != 0) { 1102 return ret; 1103 } 1104 1105 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1106 KVM_REG_RISCV_CONFIG_REG(mimpid)); 1107 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1108 1109 return ret; 1110 } 1111 1112 int kvm_arch_init_vcpu(CPUState *cs) 1113 { 1114 int ret = 0; 1115 RISCVCPU *cpu = RISCV_CPU(cs); 1116 1117 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1118 1119 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1120 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1121 if (ret != 0) { 1122 return ret; 1123 } 1124 } 1125 1126 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1127 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1128 1129 return ret; 1130 } 1131 1132 int kvm_arch_msi_data_to_gsi(uint32_t data) 1133 { 1134 abort(); 1135 } 1136 1137 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1138 int vector, PCIDevice *dev) 1139 { 1140 return 0; 1141 } 1142 1143 int kvm_arch_get_default_type(MachineState *ms) 1144 { 1145 return 0; 1146 } 1147 1148 int kvm_arch_init(MachineState *ms, KVMState *s) 1149 { 1150 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1151 return 0; 1152 } 1153 1154 int kvm_arch_irqchip_create(KVMState *s) 1155 { 1156 if (kvm_kernel_irqchip_split()) { 1157 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1158 exit(1); 1159 } 1160 1161 /* 1162 * We can create the VAIA using the newer device control API. 1163 */ 1164 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1165 } 1166 1167 int kvm_arch_process_async_events(CPUState *cs) 1168 { 1169 return 0; 1170 } 1171 1172 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1173 { 1174 } 1175 1176 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1177 { 1178 return MEMTXATTRS_UNSPECIFIED; 1179 } 1180 1181 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1182 { 1183 return true; 1184 } 1185 1186 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1187 { 1188 int ret = 0; 1189 unsigned char ch; 1190 switch (run->riscv_sbi.extension_id) { 1191 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1192 ch = run->riscv_sbi.args[0]; 1193 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1194 break; 1195 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1196 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1197 if (ret == sizeof(ch)) { 1198 run->riscv_sbi.ret[0] = ch; 1199 } else { 1200 run->riscv_sbi.ret[0] = -1; 1201 } 1202 ret = 0; 1203 break; 1204 default: 1205 qemu_log_mask(LOG_UNIMP, 1206 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1207 __func__, run->riscv_sbi.extension_id); 1208 ret = -1; 1209 break; 1210 } 1211 return ret; 1212 } 1213 1214 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1215 { 1216 int ret = 0; 1217 switch (run->exit_reason) { 1218 case KVM_EXIT_RISCV_SBI: 1219 ret = kvm_riscv_handle_sbi(cs, run); 1220 break; 1221 default: 1222 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1223 __func__, run->exit_reason); 1224 ret = -1; 1225 break; 1226 } 1227 return ret; 1228 } 1229 1230 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1231 { 1232 CPURISCVState *env = &cpu->env; 1233 int i; 1234 1235 if (!kvm_enabled()) { 1236 return; 1237 } 1238 for (i = 0; i < 32; i++) { 1239 env->gpr[i] = 0; 1240 } 1241 env->pc = cpu->env.kernel_addr; 1242 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1243 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1244 env->satp = 0; 1245 env->mie = 0; 1246 env->stvec = 0; 1247 env->sscratch = 0; 1248 env->sepc = 0; 1249 env->scause = 0; 1250 env->stval = 0; 1251 env->mip = 0; 1252 } 1253 1254 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1255 { 1256 int ret; 1257 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1258 1259 if (irq != IRQ_S_EXT) { 1260 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1261 abort(); 1262 } 1263 1264 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1265 if (ret < 0) { 1266 perror("Set irq failed"); 1267 abort(); 1268 } 1269 } 1270 1271 bool kvm_arch_cpu_check_are_resettable(void) 1272 { 1273 return true; 1274 } 1275 1276 static int aia_mode; 1277 1278 static const char *kvm_aia_mode_str(uint64_t mode) 1279 { 1280 switch (mode) { 1281 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1282 return "emul"; 1283 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1284 return "hwaccel"; 1285 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1286 default: 1287 return "auto"; 1288 }; 1289 } 1290 1291 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1292 { 1293 return g_strdup(kvm_aia_mode_str(aia_mode)); 1294 } 1295 1296 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1297 { 1298 if (!strcmp(val, "emul")) { 1299 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1300 } else if (!strcmp(val, "hwaccel")) { 1301 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1302 } else if (!strcmp(val, "auto")) { 1303 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1304 } else { 1305 error_setg(errp, "Invalid KVM AIA mode"); 1306 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1307 } 1308 } 1309 1310 void kvm_arch_accel_class_init(ObjectClass *oc) 1311 { 1312 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1313 riscv_set_kvm_aia); 1314 object_class_property_set_description(oc, "riscv-aia", 1315 "Set KVM AIA mode. Valid values are " 1316 "emul, hwaccel, and auto. Default " 1317 "is auto."); 1318 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1319 "auto"); 1320 } 1321 1322 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1323 uint64_t aia_irq_num, uint64_t aia_msi_num, 1324 uint64_t aplic_base, uint64_t imsic_base, 1325 uint64_t guest_num) 1326 { 1327 int ret, i; 1328 int aia_fd = -1; 1329 uint64_t default_aia_mode; 1330 uint64_t socket_count = riscv_socket_count(machine); 1331 uint64_t max_hart_per_socket = 0; 1332 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1333 uint64_t socket_bits, hart_bits, guest_bits; 1334 1335 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1336 1337 if (aia_fd < 0) { 1338 error_report("Unable to create in-kernel irqchip"); 1339 exit(1); 1340 } 1341 1342 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1343 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1344 &default_aia_mode, false, NULL); 1345 if (ret < 0) { 1346 error_report("KVM AIA: failed to get current KVM AIA mode"); 1347 exit(1); 1348 } 1349 qemu_log("KVM AIA: default mode is %s\n", 1350 kvm_aia_mode_str(default_aia_mode)); 1351 1352 if (default_aia_mode != aia_mode) { 1353 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1354 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1355 &aia_mode, true, NULL); 1356 if (ret < 0) 1357 warn_report("KVM AIA: failed to set KVM AIA mode"); 1358 else 1359 qemu_log("KVM AIA: set current mode to %s\n", 1360 kvm_aia_mode_str(aia_mode)); 1361 } 1362 1363 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1364 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1365 &aia_irq_num, true, NULL); 1366 if (ret < 0) { 1367 error_report("KVM AIA: failed to set number of input irq lines"); 1368 exit(1); 1369 } 1370 1371 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1372 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1373 &aia_msi_num, true, NULL); 1374 if (ret < 0) { 1375 error_report("KVM AIA: failed to set number of msi"); 1376 exit(1); 1377 } 1378 1379 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1380 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1381 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1382 &socket_bits, true, NULL); 1383 if (ret < 0) { 1384 error_report("KVM AIA: failed to set group_bits"); 1385 exit(1); 1386 } 1387 1388 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1389 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1390 &group_shift, true, NULL); 1391 if (ret < 0) { 1392 error_report("KVM AIA: failed to set group_shift"); 1393 exit(1); 1394 } 1395 1396 guest_bits = guest_num == 0 ? 0 : 1397 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1398 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1399 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1400 &guest_bits, true, NULL); 1401 if (ret < 0) { 1402 error_report("KVM AIA: failed to set guest_bits"); 1403 exit(1); 1404 } 1405 1406 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1407 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1408 &aplic_base, true, NULL); 1409 if (ret < 0) { 1410 error_report("KVM AIA: failed to set the base address of APLIC"); 1411 exit(1); 1412 } 1413 1414 for (socket = 0; socket < socket_count; socket++) { 1415 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1416 hart_count = riscv_socket_hart_count(machine, socket); 1417 base_hart = riscv_socket_first_hartid(machine, socket); 1418 1419 if (max_hart_per_socket < hart_count) { 1420 max_hart_per_socket = hart_count; 1421 } 1422 1423 for (i = 0; i < hart_count; i++) { 1424 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1425 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1426 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1427 &imsic_addr, true, NULL); 1428 if (ret < 0) { 1429 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1430 exit(1); 1431 } 1432 } 1433 } 1434 1435 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1436 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1437 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1438 &hart_bits, true, NULL); 1439 if (ret < 0) { 1440 error_report("KVM AIA: failed to set hart_bits"); 1441 exit(1); 1442 } 1443 1444 if (kvm_has_gsi_routing()) { 1445 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1446 /* KVM AIA only has one APLIC instance */ 1447 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1448 } 1449 kvm_gsi_routing_allowed = true; 1450 kvm_irqchip_commit_routes(kvm_state); 1451 } 1452 1453 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1454 KVM_DEV_RISCV_AIA_CTRL_INIT, 1455 NULL, true, NULL); 1456 if (ret < 0) { 1457 error_report("KVM AIA: initialized fail"); 1458 exit(1); 1459 } 1460 1461 kvm_msi_via_irqfd_allowed = true; 1462 } 1463 1464 static void kvm_cpu_instance_init(CPUState *cs) 1465 { 1466 Object *obj = OBJECT(RISCV_CPU(cs)); 1467 DeviceState *dev = DEVICE(obj); 1468 1469 riscv_init_kvm_registers(obj); 1470 1471 kvm_riscv_add_cpu_user_properties(obj); 1472 1473 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1474 /* Check if we have a specific KVM handler for the option */ 1475 if (object_property_find(obj, prop->name)) { 1476 continue; 1477 } 1478 qdev_property_add_static(dev, prop); 1479 } 1480 } 1481 1482 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1483 { 1484 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1485 1486 acc->cpu_instance_init = kvm_cpu_instance_init; 1487 } 1488 1489 static const TypeInfo kvm_cpu_accel_type_info = { 1490 .name = ACCEL_CPU_NAME("kvm"), 1491 1492 .parent = TYPE_ACCEL_CPU, 1493 .class_init = kvm_cpu_accel_class_init, 1494 .abstract = true, 1495 }; 1496 static void kvm_cpu_accel_register_types(void) 1497 { 1498 type_register_static(&kvm_cpu_accel_type_info); 1499 } 1500 type_init(kvm_cpu_accel_register_types); 1501 1502 static void riscv_host_cpu_init(Object *obj) 1503 { 1504 CPURISCVState *env = &RISCV_CPU(obj)->env; 1505 1506 #if defined(TARGET_RISCV32) 1507 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1508 #elif defined(TARGET_RISCV64) 1509 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1510 #endif 1511 } 1512 1513 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1514 { 1515 .name = TYPE_RISCV_CPU_HOST, 1516 .parent = TYPE_RISCV_CPU, 1517 .instance_init = riscv_host_cpu_init, 1518 } 1519 }; 1520 1521 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1522