1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/kvm.h" 32 #include "sysemu/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "hw/core/accel-cpu.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "exec/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/misc.h" 48 #include "sysemu/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) 90 { 91 uint64_t size_ctz = __builtin_ctz(size_b); 92 93 return id | (size_ctz << KVM_REG_SIZE_SHIFT); 94 } 95 96 static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, 97 uint64_t idx) 98 { 99 uint64_t id; 100 size_t size_b; 101 102 g_assert(idx < 32); 103 104 id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); 105 size_b = cpu->cfg.vlenb; 106 107 return kvm_encode_reg_size_id(id, size_b); 108 } 109 110 #define RISCV_CORE_REG(env, name) \ 111 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 112 KVM_REG_RISCV_CORE_REG(name)) 113 114 #define RISCV_CSR_REG(env, name) \ 115 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 116 KVM_REG_RISCV_CSR_REG(name)) 117 118 #define RISCV_CONFIG_REG(env, name) \ 119 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 120 KVM_REG_RISCV_CONFIG_REG(name)) 121 122 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 123 KVM_REG_RISCV_TIMER_REG(name)) 124 125 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 126 127 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 128 129 #define RISCV_VECTOR_CSR_REG(env, name) \ 130 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ 131 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 132 133 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 134 do { \ 135 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 136 if (_ret) { \ 137 return _ret; \ 138 } \ 139 } while (0) 140 141 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 142 do { \ 143 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 144 if (_ret) { \ 145 return _ret; \ 146 } \ 147 } while (0) 148 149 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 150 do { \ 151 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 152 if (ret) { \ 153 abort(); \ 154 } \ 155 } while (0) 156 157 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 158 do { \ 159 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 160 if (ret) { \ 161 abort(); \ 162 } \ 163 } while (0) 164 165 typedef struct KVMCPUConfig { 166 const char *name; 167 const char *description; 168 target_ulong offset; 169 uint64_t kvm_reg_id; 170 bool user_set; 171 bool supported; 172 } KVMCPUConfig; 173 174 #define KVM_MISA_CFG(_bit, _reg_id) \ 175 {.offset = _bit, .kvm_reg_id = _reg_id} 176 177 /* KVM ISA extensions */ 178 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 179 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 180 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 181 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 182 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 184 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 185 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 186 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 187 }; 188 189 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 190 const char *name, 191 void *opaque, Error **errp) 192 { 193 KVMCPUConfig *misa_ext_cfg = opaque; 194 target_ulong misa_bit = misa_ext_cfg->offset; 195 RISCVCPU *cpu = RISCV_CPU(obj); 196 CPURISCVState *env = &cpu->env; 197 bool value = env->misa_ext_mask & misa_bit; 198 199 visit_type_bool(v, name, &value, errp); 200 } 201 202 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 203 const char *name, 204 void *opaque, Error **errp) 205 { 206 KVMCPUConfig *misa_ext_cfg = opaque; 207 target_ulong misa_bit = misa_ext_cfg->offset; 208 RISCVCPU *cpu = RISCV_CPU(obj); 209 CPURISCVState *env = &cpu->env; 210 bool value, host_bit; 211 212 if (!visit_type_bool(v, name, &value, errp)) { 213 return; 214 } 215 216 host_bit = env->misa_ext_mask & misa_bit; 217 218 if (value == host_bit) { 219 return; 220 } 221 222 if (!value) { 223 misa_ext_cfg->user_set = true; 224 return; 225 } 226 227 /* 228 * Forbid users to enable extensions that aren't 229 * available in the hart. 230 */ 231 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 232 "enabled in the host", misa_ext_cfg->name); 233 } 234 235 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 236 { 237 CPURISCVState *env = &cpu->env; 238 uint64_t id, reg; 239 int i, ret; 240 241 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 242 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 243 target_ulong misa_bit = misa_cfg->offset; 244 245 if (!misa_cfg->user_set) { 246 continue; 247 } 248 249 /* If we're here we're going to disable the MISA bit */ 250 reg = 0; 251 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 252 misa_cfg->kvm_reg_id); 253 ret = kvm_set_one_reg(cs, id, ®); 254 if (ret != 0) { 255 /* 256 * We're not checking for -EINVAL because if the bit is about 257 * to be disabled, it means that it was already enabled by 258 * KVM. We determined that by fetching the 'isa' register 259 * during init() time. Any error at this point is worth 260 * aborting. 261 */ 262 error_report("Unable to set KVM reg %s, error %d", 263 misa_cfg->name, ret); 264 exit(EXIT_FAILURE); 265 } 266 env->misa_ext &= ~misa_bit; 267 } 268 } 269 270 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 271 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 272 .kvm_reg_id = _reg_id} 273 274 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 275 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 276 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 277 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 278 KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), 279 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 280 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 281 KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), 282 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 283 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 284 KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP), 285 KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP), 286 KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), 287 KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS), 288 KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), 289 KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), 290 KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), 291 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 292 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 293 KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), 294 KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), 295 KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), 296 KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), 297 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 298 KVM_EXT_CFG("zca", ext_zca, KVM_RISCV_ISA_EXT_ZCA), 299 KVM_EXT_CFG("zcb", ext_zcb, KVM_RISCV_ISA_EXT_ZCB), 300 KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD), 301 KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF), 302 KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), 303 KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), 304 KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), 305 KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), 306 KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), 307 KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), 308 KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), 309 KVM_EXT_CFG("ztso", ext_ztso, KVM_RISCV_ISA_EXT_ZTSO), 310 KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), 311 KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), 312 KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), 313 KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), 314 KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), 315 KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), 316 KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), 317 KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), 318 KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), 319 KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), 320 KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), 321 KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), 322 KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), 323 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 324 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 325 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 326 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 327 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 328 }; 329 330 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 331 { 332 return (void *)&cpu->cfg + kvmcfg->offset; 333 } 334 335 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 336 uint32_t val) 337 { 338 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 339 340 *ext_enabled = val; 341 } 342 343 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 344 KVMCPUConfig *multi_ext) 345 { 346 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 347 348 return *ext_enabled; 349 } 350 351 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 352 const char *name, 353 void *opaque, Error **errp) 354 { 355 KVMCPUConfig *multi_ext_cfg = opaque; 356 RISCVCPU *cpu = RISCV_CPU(obj); 357 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 358 359 visit_type_bool(v, name, &value, errp); 360 } 361 362 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 363 const char *name, 364 void *opaque, Error **errp) 365 { 366 KVMCPUConfig *multi_ext_cfg = opaque; 367 RISCVCPU *cpu = RISCV_CPU(obj); 368 bool value, host_val; 369 370 if (!visit_type_bool(v, name, &value, errp)) { 371 return; 372 } 373 374 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 375 376 /* 377 * Ignore if the user is setting the same value 378 * as the host. 379 */ 380 if (value == host_val) { 381 return; 382 } 383 384 if (!multi_ext_cfg->supported) { 385 /* 386 * Error out if the user is trying to enable an 387 * extension that KVM doesn't support. Ignore 388 * option otherwise. 389 */ 390 if (value) { 391 error_setg(errp, "KVM does not support disabling extension %s", 392 multi_ext_cfg->name); 393 } 394 395 return; 396 } 397 398 multi_ext_cfg->user_set = true; 399 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 400 } 401 402 static KVMCPUConfig kvm_cbom_blocksize = { 403 .name = "cbom_blocksize", 404 .offset = CPU_CFG_OFFSET(cbom_blocksize), 405 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 406 }; 407 408 static KVMCPUConfig kvm_cboz_blocksize = { 409 .name = "cboz_blocksize", 410 .offset = CPU_CFG_OFFSET(cboz_blocksize), 411 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 412 }; 413 414 static KVMCPUConfig kvm_v_vlenb = { 415 .name = "vlenb", 416 .offset = CPU_CFG_OFFSET(vlenb), 417 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | 418 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) 419 }; 420 421 static KVMCPUConfig kvm_sbi_dbcn = { 422 .name = "sbi_dbcn", 423 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | 424 KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN 425 }; 426 427 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 428 { 429 CPURISCVState *env = &cpu->env; 430 uint64_t id, reg; 431 int i, ret; 432 433 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 434 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 435 436 if (!multi_ext_cfg->user_set) { 437 continue; 438 } 439 440 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 441 multi_ext_cfg->kvm_reg_id); 442 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 443 ret = kvm_set_one_reg(cs, id, ®); 444 if (ret != 0) { 445 if (!reg && ret == -EINVAL) { 446 warn_report("KVM cannot disable extension %s", 447 multi_ext_cfg->name); 448 } else { 449 error_report("Unable to enable extension %s in KVM, error %d", 450 multi_ext_cfg->name, ret); 451 exit(EXIT_FAILURE); 452 } 453 } 454 } 455 } 456 457 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 458 const char *name, 459 void *opaque, Error **errp) 460 { 461 bool value = false; 462 463 visit_type_bool(v, name, &value, errp); 464 } 465 466 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 467 const char *name, 468 void *opaque, Error **errp) 469 { 470 const char *propname = opaque; 471 bool value; 472 473 if (!visit_type_bool(v, name, &value, errp)) { 474 return; 475 } 476 477 if (value) { 478 error_setg(errp, "'%s' is not available with KVM", 479 propname); 480 } 481 } 482 483 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 484 { 485 /* Check if KVM created the property already */ 486 if (object_property_find(obj, prop_name)) { 487 return; 488 } 489 490 /* 491 * Set the default to disabled for every extension 492 * unknown to KVM and error out if the user attempts 493 * to enable any of them. 494 */ 495 object_property_add(obj, prop_name, "bool", 496 cpu_get_cfg_unavailable, 497 cpu_set_cfg_unavailable, 498 NULL, (void *)prop_name); 499 } 500 501 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 502 const RISCVCPUMultiExtConfig *array) 503 { 504 const RISCVCPUMultiExtConfig *prop; 505 506 g_assert(array); 507 508 for (prop = array; prop && prop->name; prop++) { 509 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 510 } 511 } 512 513 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 514 { 515 int i; 516 517 riscv_add_satp_mode_properties(cpu_obj); 518 519 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 520 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 521 int bit = misa_cfg->offset; 522 523 misa_cfg->name = riscv_get_misa_ext_name(bit); 524 misa_cfg->description = riscv_get_misa_ext_description(bit); 525 526 object_property_add(cpu_obj, misa_cfg->name, "bool", 527 kvm_cpu_get_misa_ext_cfg, 528 kvm_cpu_set_misa_ext_cfg, 529 NULL, misa_cfg); 530 object_property_set_description(cpu_obj, misa_cfg->name, 531 misa_cfg->description); 532 } 533 534 for (i = 0; misa_bits[i] != 0; i++) { 535 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 536 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 537 } 538 539 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 540 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 541 542 object_property_add(cpu_obj, multi_cfg->name, "bool", 543 kvm_cpu_get_multi_ext_cfg, 544 kvm_cpu_set_multi_ext_cfg, 545 NULL, multi_cfg); 546 } 547 548 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 549 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 550 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 551 552 /* We don't have the needed KVM support for profiles */ 553 for (i = 0; riscv_profiles[i] != NULL; i++) { 554 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 555 } 556 } 557 558 static int kvm_riscv_get_regs_core(CPUState *cs) 559 { 560 int ret = 0; 561 int i; 562 target_ulong reg; 563 CPURISCVState *env = &RISCV_CPU(cs)->env; 564 565 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 566 if (ret) { 567 return ret; 568 } 569 env->pc = reg; 570 571 for (i = 1; i < 32; i++) { 572 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 573 ret = kvm_get_one_reg(cs, id, ®); 574 if (ret) { 575 return ret; 576 } 577 env->gpr[i] = reg; 578 } 579 580 return ret; 581 } 582 583 static int kvm_riscv_put_regs_core(CPUState *cs) 584 { 585 int ret = 0; 586 int i; 587 target_ulong reg; 588 CPURISCVState *env = &RISCV_CPU(cs)->env; 589 590 reg = env->pc; 591 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 592 if (ret) { 593 return ret; 594 } 595 596 for (i = 1; i < 32; i++) { 597 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 598 reg = env->gpr[i]; 599 ret = kvm_set_one_reg(cs, id, ®); 600 if (ret) { 601 return ret; 602 } 603 } 604 605 return ret; 606 } 607 608 static int kvm_riscv_get_regs_csr(CPUState *cs) 609 { 610 CPURISCVState *env = &RISCV_CPU(cs)->env; 611 612 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 613 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 614 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 615 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 616 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 617 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 618 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 619 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 620 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 621 622 return 0; 623 } 624 625 static int kvm_riscv_put_regs_csr(CPUState *cs) 626 { 627 CPURISCVState *env = &RISCV_CPU(cs)->env; 628 629 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 630 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 631 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 632 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 633 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 634 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 635 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 636 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 637 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 638 639 return 0; 640 } 641 642 static int kvm_riscv_get_regs_fp(CPUState *cs) 643 { 644 int ret = 0; 645 int i; 646 CPURISCVState *env = &RISCV_CPU(cs)->env; 647 648 if (riscv_has_ext(env, RVD)) { 649 uint64_t reg; 650 for (i = 0; i < 32; i++) { 651 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 652 if (ret) { 653 return ret; 654 } 655 env->fpr[i] = reg; 656 } 657 return ret; 658 } 659 660 if (riscv_has_ext(env, RVF)) { 661 uint32_t reg; 662 for (i = 0; i < 32; i++) { 663 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 664 if (ret) { 665 return ret; 666 } 667 env->fpr[i] = reg; 668 } 669 return ret; 670 } 671 672 return ret; 673 } 674 675 static int kvm_riscv_put_regs_fp(CPUState *cs) 676 { 677 int ret = 0; 678 int i; 679 CPURISCVState *env = &RISCV_CPU(cs)->env; 680 681 if (riscv_has_ext(env, RVD)) { 682 uint64_t reg; 683 for (i = 0; i < 32; i++) { 684 reg = env->fpr[i]; 685 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 686 if (ret) { 687 return ret; 688 } 689 } 690 return ret; 691 } 692 693 if (riscv_has_ext(env, RVF)) { 694 uint32_t reg; 695 for (i = 0; i < 32; i++) { 696 reg = env->fpr[i]; 697 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 698 if (ret) { 699 return ret; 700 } 701 } 702 return ret; 703 } 704 705 return ret; 706 } 707 708 static void kvm_riscv_get_regs_timer(CPUState *cs) 709 { 710 CPURISCVState *env = &RISCV_CPU(cs)->env; 711 712 if (env->kvm_timer_dirty) { 713 return; 714 } 715 716 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 717 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 718 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 719 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 720 721 env->kvm_timer_dirty = true; 722 } 723 724 static void kvm_riscv_put_regs_timer(CPUState *cs) 725 { 726 uint64_t reg; 727 CPURISCVState *env = &RISCV_CPU(cs)->env; 728 729 if (!env->kvm_timer_dirty) { 730 return; 731 } 732 733 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 734 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 735 736 /* 737 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 738 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 739 * doesn't matter that adaping in QEMU now. 740 * TODO If KVM changes, adapt here. 741 */ 742 if (env->kvm_timer_state) { 743 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 744 } 745 746 /* 747 * For now, migration will not work between Hosts with different timer 748 * frequency. Therefore, we should check whether they are the same here 749 * during the migration. 750 */ 751 if (migration_is_running()) { 752 KVM_RISCV_GET_TIMER(cs, frequency, reg); 753 if (reg != env->kvm_timer_frequency) { 754 error_report("Dst Hosts timer frequency != Src Hosts"); 755 } 756 } 757 758 env->kvm_timer_dirty = false; 759 } 760 761 uint64_t kvm_riscv_get_timebase_frequency(CPUState *cs) 762 { 763 uint64_t reg; 764 765 KVM_RISCV_GET_TIMER(cs, frequency, reg); 766 767 return reg; 768 } 769 770 static int kvm_riscv_get_regs_vector(CPUState *cs) 771 { 772 RISCVCPU *cpu = RISCV_CPU(cs); 773 CPURISCVState *env = &cpu->env; 774 target_ulong reg; 775 uint64_t vreg_id; 776 int vreg_idx, ret = 0; 777 778 if (!riscv_has_ext(env, RVV)) { 779 return 0; 780 } 781 782 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 783 if (ret) { 784 return ret; 785 } 786 env->vstart = reg; 787 788 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 789 if (ret) { 790 return ret; 791 } 792 env->vl = reg; 793 794 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 795 if (ret) { 796 return ret; 797 } 798 env->vtype = reg; 799 800 if (kvm_v_vlenb.supported) { 801 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 802 if (ret) { 803 return ret; 804 } 805 cpu->cfg.vlenb = reg; 806 807 for (int i = 0; i < 32; i++) { 808 /* 809 * vreg[] is statically allocated using RV_VLEN_MAX. 810 * Use it instead of vlenb to calculate vreg_idx for 811 * simplicity. 812 */ 813 vreg_idx = i * RV_VLEN_MAX / 64; 814 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 815 816 ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 817 if (ret) { 818 return ret; 819 } 820 } 821 } 822 823 return 0; 824 } 825 826 static int kvm_riscv_put_regs_vector(CPUState *cs) 827 { 828 RISCVCPU *cpu = RISCV_CPU(cs); 829 CPURISCVState *env = &cpu->env; 830 target_ulong reg; 831 uint64_t vreg_id; 832 int vreg_idx, ret = 0; 833 834 if (!riscv_has_ext(env, RVV)) { 835 return 0; 836 } 837 838 reg = env->vstart; 839 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 840 if (ret) { 841 return ret; 842 } 843 844 reg = env->vl; 845 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 846 if (ret) { 847 return ret; 848 } 849 850 reg = env->vtype; 851 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 852 if (ret) { 853 return ret; 854 } 855 856 if (kvm_v_vlenb.supported) { 857 reg = cpu->cfg.vlenb; 858 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 859 860 for (int i = 0; i < 32; i++) { 861 /* 862 * vreg[] is statically allocated using RV_VLEN_MAX. 863 * Use it instead of vlenb to calculate vreg_idx for 864 * simplicity. 865 */ 866 vreg_idx = i * RV_VLEN_MAX / 64; 867 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 868 869 ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 870 if (ret) { 871 return ret; 872 } 873 } 874 } 875 876 return ret; 877 } 878 879 typedef struct KVMScratchCPU { 880 int kvmfd; 881 int vmfd; 882 int cpufd; 883 } KVMScratchCPU; 884 885 /* 886 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 887 * from target/arm/kvm.c. 888 */ 889 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 890 { 891 int kvmfd = -1, vmfd = -1, cpufd = -1; 892 893 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 894 if (kvmfd < 0) { 895 goto err; 896 } 897 do { 898 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 899 } while (vmfd == -1 && errno == EINTR); 900 if (vmfd < 0) { 901 goto err; 902 } 903 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 904 if (cpufd < 0) { 905 goto err; 906 } 907 908 scratch->kvmfd = kvmfd; 909 scratch->vmfd = vmfd; 910 scratch->cpufd = cpufd; 911 912 return true; 913 914 err: 915 if (cpufd >= 0) { 916 close(cpufd); 917 } 918 if (vmfd >= 0) { 919 close(vmfd); 920 } 921 if (kvmfd >= 0) { 922 close(kvmfd); 923 } 924 925 return false; 926 } 927 928 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 929 { 930 close(scratch->cpufd); 931 close(scratch->vmfd); 932 close(scratch->kvmfd); 933 } 934 935 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 936 { 937 CPURISCVState *env = &cpu->env; 938 struct kvm_one_reg reg; 939 int ret; 940 941 reg.id = RISCV_CONFIG_REG(env, mvendorid); 942 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 943 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 944 if (ret != 0) { 945 error_report("Unable to retrieve mvendorid from host, error %d", ret); 946 } 947 948 reg.id = RISCV_CONFIG_REG(env, marchid); 949 reg.addr = (uint64_t)&cpu->cfg.marchid; 950 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 951 if (ret != 0) { 952 error_report("Unable to retrieve marchid from host, error %d", ret); 953 } 954 955 reg.id = RISCV_CONFIG_REG(env, mimpid); 956 reg.addr = (uint64_t)&cpu->cfg.mimpid; 957 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 958 if (ret != 0) { 959 error_report("Unable to retrieve mimpid from host, error %d", ret); 960 } 961 } 962 963 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 964 KVMScratchCPU *kvmcpu) 965 { 966 CPURISCVState *env = &cpu->env; 967 struct kvm_one_reg reg; 968 int ret; 969 970 reg.id = RISCV_CONFIG_REG(env, isa); 971 reg.addr = (uint64_t)&env->misa_ext_mask; 972 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 973 974 if (ret) { 975 error_report("Unable to fetch ISA register from KVM, " 976 "error %d", ret); 977 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 978 exit(EXIT_FAILURE); 979 } 980 981 env->misa_ext = env->misa_ext_mask; 982 } 983 984 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 985 KVMCPUConfig *cbomz_cfg) 986 { 987 CPURISCVState *env = &cpu->env; 988 struct kvm_one_reg reg; 989 int ret; 990 991 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 992 cbomz_cfg->kvm_reg_id); 993 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 994 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 995 if (ret != 0) { 996 error_report("Unable to read KVM reg %s, error %d", 997 cbomz_cfg->name, ret); 998 exit(EXIT_FAILURE); 999 } 1000 } 1001 1002 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 1003 KVMScratchCPU *kvmcpu) 1004 { 1005 CPURISCVState *env = &cpu->env; 1006 uint64_t val; 1007 int i, ret; 1008 1009 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1010 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1011 struct kvm_one_reg reg; 1012 1013 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 1014 multi_ext_cfg->kvm_reg_id); 1015 reg.addr = (uint64_t)&val; 1016 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1017 if (ret != 0) { 1018 if (errno == EINVAL) { 1019 /* Silently default to 'false' if KVM does not support it. */ 1020 multi_ext_cfg->supported = false; 1021 val = false; 1022 } else { 1023 error_report("Unable to read ISA_EXT KVM register %s: %s", 1024 multi_ext_cfg->name, strerror(errno)); 1025 exit(EXIT_FAILURE); 1026 } 1027 } else { 1028 multi_ext_cfg->supported = true; 1029 } 1030 1031 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1032 } 1033 1034 if (cpu->cfg.ext_zicbom) { 1035 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1036 } 1037 1038 if (cpu->cfg.ext_zicboz) { 1039 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1040 } 1041 } 1042 1043 static int uint64_cmp(const void *a, const void *b) 1044 { 1045 uint64_t val1 = *(const uint64_t *)a; 1046 uint64_t val2 = *(const uint64_t *)b; 1047 1048 if (val1 < val2) { 1049 return -1; 1050 } 1051 1052 if (val1 > val2) { 1053 return 1; 1054 } 1055 1056 return 0; 1057 } 1058 1059 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, 1060 KVMScratchCPU *kvmcpu, 1061 struct kvm_reg_list *reglist) 1062 { 1063 struct kvm_reg_list *reg_search; 1064 1065 reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, 1066 sizeof(uint64_t), uint64_cmp); 1067 1068 if (reg_search) { 1069 kvm_sbi_dbcn.supported = true; 1070 } 1071 } 1072 1073 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1074 struct kvm_reg_list *reglist) 1075 { 1076 struct kvm_one_reg reg; 1077 struct kvm_reg_list *reg_search; 1078 uint64_t val; 1079 int ret; 1080 1081 reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, 1082 sizeof(uint64_t), uint64_cmp); 1083 1084 if (reg_search) { 1085 reg.id = kvm_v_vlenb.kvm_reg_id; 1086 reg.addr = (uint64_t)&val; 1087 1088 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1089 if (ret != 0) { 1090 error_report("Unable to read vlenb register, error code: %d", 1091 errno); 1092 exit(EXIT_FAILURE); 1093 } 1094 1095 kvm_v_vlenb.supported = true; 1096 cpu->cfg.vlenb = val; 1097 } 1098 } 1099 1100 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 1101 { 1102 KVMCPUConfig *multi_ext_cfg; 1103 struct kvm_one_reg reg; 1104 struct kvm_reg_list rl_struct; 1105 struct kvm_reg_list *reglist; 1106 uint64_t val, reg_id, *reg_search; 1107 int i, ret; 1108 1109 rl_struct.n = 0; 1110 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 1111 1112 /* 1113 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 1114 * (EINVAL). Use read_legacy() in this case. 1115 */ 1116 if (errno == EINVAL) { 1117 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 1118 } else if (errno != E2BIG) { 1119 /* 1120 * E2BIG is an expected error message for the API since we 1121 * don't know the number of registers. The right amount will 1122 * be written in rl_struct.n. 1123 * 1124 * Error out if we get any other errno. 1125 */ 1126 error_report("Error when accessing get-reg-list: %s", 1127 strerror(errno)); 1128 exit(EXIT_FAILURE); 1129 } 1130 1131 reglist = g_malloc(sizeof(struct kvm_reg_list) + 1132 rl_struct.n * sizeof(uint64_t)); 1133 reglist->n = rl_struct.n; 1134 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 1135 if (ret) { 1136 error_report("Error when reading KVM_GET_REG_LIST: %s", 1137 strerror(errno)); 1138 exit(EXIT_FAILURE); 1139 } 1140 1141 /* sort reglist to use bsearch() */ 1142 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 1143 1144 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1145 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1146 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 1147 multi_ext_cfg->kvm_reg_id); 1148 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1149 sizeof(uint64_t), uint64_cmp); 1150 if (!reg_search) { 1151 continue; 1152 } 1153 1154 reg.id = reg_id; 1155 reg.addr = (uint64_t)&val; 1156 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1157 if (ret != 0) { 1158 error_report("Unable to read ISA_EXT KVM register %s: %s", 1159 multi_ext_cfg->name, strerror(errno)); 1160 exit(EXIT_FAILURE); 1161 } 1162 1163 multi_ext_cfg->supported = true; 1164 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1165 } 1166 1167 if (cpu->cfg.ext_zicbom) { 1168 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1169 } 1170 1171 if (cpu->cfg.ext_zicboz) { 1172 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1173 } 1174 1175 if (riscv_has_ext(&cpu->env, RVV)) { 1176 kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); 1177 } 1178 1179 kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist); 1180 } 1181 1182 static void riscv_init_kvm_registers(Object *cpu_obj) 1183 { 1184 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1185 KVMScratchCPU kvmcpu; 1186 1187 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1188 return; 1189 } 1190 1191 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1192 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1193 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1194 1195 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1196 } 1197 1198 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1199 KVM_CAP_LAST_INFO 1200 }; 1201 1202 int kvm_arch_get_registers(CPUState *cs, Error **errp) 1203 { 1204 int ret = 0; 1205 1206 ret = kvm_riscv_get_regs_core(cs); 1207 if (ret) { 1208 return ret; 1209 } 1210 1211 ret = kvm_riscv_get_regs_csr(cs); 1212 if (ret) { 1213 return ret; 1214 } 1215 1216 ret = kvm_riscv_get_regs_fp(cs); 1217 if (ret) { 1218 return ret; 1219 } 1220 1221 ret = kvm_riscv_get_regs_vector(cs); 1222 if (ret) { 1223 return ret; 1224 } 1225 1226 return ret; 1227 } 1228 1229 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1230 { 1231 if (cap_has_mp_state) { 1232 struct kvm_mp_state mp_state = { 1233 .mp_state = state 1234 }; 1235 1236 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1237 if (ret) { 1238 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1239 __func__, ret, strerror(-ret)); 1240 return -1; 1241 } 1242 } 1243 1244 return 0; 1245 } 1246 1247 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 1248 { 1249 int ret = 0; 1250 1251 ret = kvm_riscv_put_regs_core(cs); 1252 if (ret) { 1253 return ret; 1254 } 1255 1256 ret = kvm_riscv_put_regs_csr(cs); 1257 if (ret) { 1258 return ret; 1259 } 1260 1261 ret = kvm_riscv_put_regs_fp(cs); 1262 if (ret) { 1263 return ret; 1264 } 1265 1266 ret = kvm_riscv_put_regs_vector(cs); 1267 if (ret) { 1268 return ret; 1269 } 1270 1271 if (KVM_PUT_RESET_STATE == level) { 1272 RISCVCPU *cpu = RISCV_CPU(cs); 1273 if (cs->cpu_index == 0) { 1274 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1275 } else { 1276 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1277 } 1278 if (ret) { 1279 return ret; 1280 } 1281 } 1282 1283 return ret; 1284 } 1285 1286 int kvm_arch_release_virq_post(int virq) 1287 { 1288 return 0; 1289 } 1290 1291 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1292 uint64_t address, uint32_t data, PCIDevice *dev) 1293 { 1294 return 0; 1295 } 1296 1297 int kvm_arch_destroy_vcpu(CPUState *cs) 1298 { 1299 return 0; 1300 } 1301 1302 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1303 { 1304 return cpu->cpu_index; 1305 } 1306 1307 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1308 RunState state) 1309 { 1310 CPUState *cs = opaque; 1311 1312 if (running) { 1313 kvm_riscv_put_regs_timer(cs); 1314 } else { 1315 kvm_riscv_get_regs_timer(cs); 1316 } 1317 } 1318 1319 void kvm_arch_init_irq_routing(KVMState *s) 1320 { 1321 } 1322 1323 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1324 { 1325 CPURISCVState *env = &cpu->env; 1326 target_ulong reg; 1327 uint64_t id; 1328 int ret; 1329 1330 id = RISCV_CONFIG_REG(env, mvendorid); 1331 /* 1332 * cfg.mvendorid is an uint32 but a target_ulong will 1333 * be written. Assign it to a target_ulong var to avoid 1334 * writing pieces of other cpu->cfg fields in the reg. 1335 */ 1336 reg = cpu->cfg.mvendorid; 1337 ret = kvm_set_one_reg(cs, id, ®); 1338 if (ret != 0) { 1339 return ret; 1340 } 1341 1342 id = RISCV_CONFIG_REG(env, marchid); 1343 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1344 if (ret != 0) { 1345 return ret; 1346 } 1347 1348 id = RISCV_CONFIG_REG(env, mimpid); 1349 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1350 1351 return ret; 1352 } 1353 1354 static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) 1355 { 1356 target_ulong reg = 1; 1357 1358 if (!kvm_sbi_dbcn.supported) { 1359 return 0; 1360 } 1361 1362 return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); 1363 } 1364 1365 int kvm_arch_init_vcpu(CPUState *cs) 1366 { 1367 int ret = 0; 1368 RISCVCPU *cpu = RISCV_CPU(cs); 1369 1370 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1371 1372 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1373 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1374 if (ret != 0) { 1375 return ret; 1376 } 1377 } 1378 1379 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1380 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1381 1382 ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); 1383 1384 return ret; 1385 } 1386 1387 int kvm_arch_msi_data_to_gsi(uint32_t data) 1388 { 1389 abort(); 1390 } 1391 1392 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1393 int vector, PCIDevice *dev) 1394 { 1395 return 0; 1396 } 1397 1398 int kvm_arch_get_default_type(MachineState *ms) 1399 { 1400 return 0; 1401 } 1402 1403 int kvm_arch_init(MachineState *ms, KVMState *s) 1404 { 1405 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1406 return 0; 1407 } 1408 1409 int kvm_arch_irqchip_create(KVMState *s) 1410 { 1411 if (kvm_kernel_irqchip_split()) { 1412 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1413 exit(1); 1414 } 1415 1416 /* 1417 * We can create the VAIA using the newer device control API. 1418 */ 1419 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1420 } 1421 1422 int kvm_arch_process_async_events(CPUState *cs) 1423 { 1424 return 0; 1425 } 1426 1427 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1428 { 1429 } 1430 1431 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1432 { 1433 return MEMTXATTRS_UNSPECIFIED; 1434 } 1435 1436 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1437 { 1438 return true; 1439 } 1440 1441 static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) 1442 { 1443 g_autofree uint8_t *buf = NULL; 1444 RISCVCPU *cpu = RISCV_CPU(cs); 1445 target_ulong num_bytes; 1446 uint64_t addr; 1447 unsigned char ch; 1448 int ret; 1449 1450 switch (run->riscv_sbi.function_id) { 1451 case SBI_EXT_DBCN_CONSOLE_READ: 1452 case SBI_EXT_DBCN_CONSOLE_WRITE: 1453 num_bytes = run->riscv_sbi.args[0]; 1454 1455 if (num_bytes == 0) { 1456 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1457 run->riscv_sbi.ret[1] = 0; 1458 break; 1459 } 1460 1461 addr = run->riscv_sbi.args[1]; 1462 1463 /* 1464 * Handle the case where a 32 bit CPU is running in a 1465 * 64 bit addressing env. 1466 */ 1467 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { 1468 addr |= (uint64_t)run->riscv_sbi.args[2] << 32; 1469 } 1470 1471 buf = g_malloc0(num_bytes); 1472 1473 if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { 1474 ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); 1475 if (ret < 0) { 1476 error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " 1477 "reading chardev"); 1478 exit(1); 1479 } 1480 1481 cpu_physical_memory_write(addr, buf, ret); 1482 } else { 1483 cpu_physical_memory_read(addr, buf, num_bytes); 1484 1485 ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); 1486 if (ret < 0) { 1487 error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " 1488 "writing chardev"); 1489 exit(1); 1490 } 1491 } 1492 1493 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1494 run->riscv_sbi.ret[1] = ret; 1495 break; 1496 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 1497 ch = run->riscv_sbi.args[0]; 1498 ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1499 1500 if (ret < 0) { 1501 error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " 1502 "writing chardev"); 1503 exit(1); 1504 } 1505 1506 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1507 run->riscv_sbi.ret[1] = 0; 1508 break; 1509 default: 1510 run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; 1511 } 1512 } 1513 1514 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1515 { 1516 int ret = 0; 1517 unsigned char ch; 1518 switch (run->riscv_sbi.extension_id) { 1519 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1520 ch = run->riscv_sbi.args[0]; 1521 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1522 break; 1523 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1524 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1525 if (ret == sizeof(ch)) { 1526 run->riscv_sbi.ret[0] = ch; 1527 } else { 1528 run->riscv_sbi.ret[0] = -1; 1529 } 1530 ret = 0; 1531 break; 1532 case SBI_EXT_DBCN: 1533 kvm_riscv_handle_sbi_dbcn(cs, run); 1534 break; 1535 default: 1536 qemu_log_mask(LOG_UNIMP, 1537 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1538 __func__, run->riscv_sbi.extension_id); 1539 ret = -1; 1540 break; 1541 } 1542 return ret; 1543 } 1544 1545 static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) 1546 { 1547 target_ulong csr_num = run->riscv_csr.csr_num; 1548 target_ulong new_value = run->riscv_csr.new_value; 1549 target_ulong write_mask = run->riscv_csr.write_mask; 1550 int ret = 0; 1551 1552 switch (csr_num) { 1553 case CSR_SEED: 1554 run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); 1555 break; 1556 default: 1557 qemu_log_mask(LOG_UNIMP, 1558 "%s: un-handled CSR EXIT for CSR %lx\n", 1559 __func__, csr_num); 1560 ret = -1; 1561 break; 1562 } 1563 1564 return ret; 1565 } 1566 1567 static bool kvm_riscv_handle_debug(CPUState *cs) 1568 { 1569 RISCVCPU *cpu = RISCV_CPU(cs); 1570 CPURISCVState *env = &cpu->env; 1571 1572 /* Ensure PC is synchronised */ 1573 kvm_cpu_synchronize_state(cs); 1574 1575 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1576 return true; 1577 } 1578 1579 return false; 1580 } 1581 1582 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1583 { 1584 int ret = 0; 1585 switch (run->exit_reason) { 1586 case KVM_EXIT_RISCV_SBI: 1587 ret = kvm_riscv_handle_sbi(cs, run); 1588 break; 1589 case KVM_EXIT_RISCV_CSR: 1590 ret = kvm_riscv_handle_csr(cs, run); 1591 break; 1592 case KVM_EXIT_DEBUG: 1593 if (kvm_riscv_handle_debug(cs)) { 1594 ret = EXCP_DEBUG; 1595 } 1596 break; 1597 default: 1598 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1599 __func__, run->exit_reason); 1600 ret = -1; 1601 break; 1602 } 1603 return ret; 1604 } 1605 1606 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1607 { 1608 CPURISCVState *env = &cpu->env; 1609 int i; 1610 1611 if (!kvm_enabled()) { 1612 return; 1613 } 1614 for (i = 0; i < 32; i++) { 1615 env->gpr[i] = 0; 1616 } 1617 env->pc = cpu->env.kernel_addr; 1618 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1619 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1620 env->satp = 0; 1621 env->mie = 0; 1622 env->stvec = 0; 1623 env->sscratch = 0; 1624 env->sepc = 0; 1625 env->scause = 0; 1626 env->stval = 0; 1627 env->mip = 0; 1628 } 1629 1630 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1631 { 1632 int ret; 1633 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1634 1635 if (irq != IRQ_S_EXT) { 1636 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1637 abort(); 1638 } 1639 1640 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1641 if (ret < 0) { 1642 perror("Set irq failed"); 1643 abort(); 1644 } 1645 } 1646 1647 static int aia_mode; 1648 1649 static const char *kvm_aia_mode_str(uint64_t mode) 1650 { 1651 switch (mode) { 1652 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1653 return "emul"; 1654 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1655 return "hwaccel"; 1656 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1657 default: 1658 return "auto"; 1659 }; 1660 } 1661 1662 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1663 { 1664 return g_strdup(kvm_aia_mode_str(aia_mode)); 1665 } 1666 1667 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1668 { 1669 if (!strcmp(val, "emul")) { 1670 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1671 } else if (!strcmp(val, "hwaccel")) { 1672 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1673 } else if (!strcmp(val, "auto")) { 1674 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1675 } else { 1676 error_setg(errp, "Invalid KVM AIA mode"); 1677 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1678 } 1679 } 1680 1681 void kvm_arch_accel_class_init(ObjectClass *oc) 1682 { 1683 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1684 riscv_set_kvm_aia); 1685 object_class_property_set_description(oc, "riscv-aia", 1686 "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " 1687 "Changing KVM AIA modes relies on host support. Defaults to 'auto' " 1688 "if the host supports it"); 1689 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1690 "auto"); 1691 } 1692 1693 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1694 uint64_t aia_irq_num, uint64_t aia_msi_num, 1695 uint64_t aplic_base, uint64_t imsic_base, 1696 uint64_t guest_num) 1697 { 1698 int ret, i; 1699 int aia_fd = -1; 1700 uint64_t default_aia_mode; 1701 uint64_t socket_count = riscv_socket_count(machine); 1702 uint64_t max_hart_per_socket = 0; 1703 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1704 uint64_t socket_bits, hart_bits, guest_bits; 1705 uint64_t max_group_id; 1706 1707 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1708 1709 if (aia_fd < 0) { 1710 error_report("Unable to create in-kernel irqchip"); 1711 exit(1); 1712 } 1713 1714 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1715 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1716 &default_aia_mode, false, NULL); 1717 if (ret < 0) { 1718 error_report("KVM AIA: failed to get current KVM AIA mode"); 1719 exit(1); 1720 } 1721 1722 if (default_aia_mode != aia_mode) { 1723 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1724 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1725 &aia_mode, true, NULL); 1726 if (ret < 0) { 1727 warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " 1728 "default host mode '%s'", 1729 kvm_aia_mode_str(aia_mode), 1730 kvm_aia_mode_str(default_aia_mode)); 1731 1732 /* failed to change AIA mode, use default */ 1733 aia_mode = default_aia_mode; 1734 } 1735 } 1736 1737 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1738 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1739 &aia_irq_num, true, NULL); 1740 if (ret < 0) { 1741 error_report("KVM AIA: failed to set number of input irq lines"); 1742 exit(1); 1743 } 1744 1745 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1746 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1747 &aia_msi_num, true, NULL); 1748 if (ret < 0) { 1749 error_report("KVM AIA: failed to set number of msi"); 1750 exit(1); 1751 } 1752 1753 1754 if (socket_count > 1) { 1755 max_group_id = socket_count - 1; 1756 socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1; 1757 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1758 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1759 &socket_bits, true, NULL); 1760 if (ret < 0) { 1761 error_report("KVM AIA: failed to set group_bits"); 1762 exit(1); 1763 } 1764 1765 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1766 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1767 &group_shift, true, NULL); 1768 if (ret < 0) { 1769 error_report("KVM AIA: failed to set group_shift"); 1770 exit(1); 1771 } 1772 } 1773 1774 guest_bits = guest_num == 0 ? 0 : 1775 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1776 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1777 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1778 &guest_bits, true, NULL); 1779 if (ret < 0) { 1780 error_report("KVM AIA: failed to set guest_bits"); 1781 exit(1); 1782 } 1783 1784 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1785 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1786 &aplic_base, true, NULL); 1787 if (ret < 0) { 1788 error_report("KVM AIA: failed to set the base address of APLIC"); 1789 exit(1); 1790 } 1791 1792 for (socket = 0; socket < socket_count; socket++) { 1793 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1794 hart_count = riscv_socket_hart_count(machine, socket); 1795 base_hart = riscv_socket_first_hartid(machine, socket); 1796 1797 if (max_hart_per_socket < hart_count) { 1798 max_hart_per_socket = hart_count; 1799 } 1800 1801 for (i = 0; i < hart_count; i++) { 1802 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1803 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1804 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1805 &imsic_addr, true, NULL); 1806 if (ret < 0) { 1807 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1808 exit(1); 1809 } 1810 } 1811 } 1812 1813 1814 if (max_hart_per_socket > 1) { 1815 max_hart_per_socket--; 1816 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1817 } else { 1818 hart_bits = 0; 1819 } 1820 1821 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1822 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1823 &hart_bits, true, NULL); 1824 if (ret < 0) { 1825 error_report("KVM AIA: failed to set hart_bits"); 1826 exit(1); 1827 } 1828 1829 if (kvm_has_gsi_routing()) { 1830 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1831 /* KVM AIA only has one APLIC instance */ 1832 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1833 } 1834 kvm_gsi_routing_allowed = true; 1835 kvm_irqchip_commit_routes(kvm_state); 1836 } 1837 1838 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1839 KVM_DEV_RISCV_AIA_CTRL_INIT, 1840 NULL, true, NULL); 1841 if (ret < 0) { 1842 error_report("KVM AIA: initialized fail"); 1843 exit(1); 1844 } 1845 1846 kvm_msi_via_irqfd_allowed = true; 1847 } 1848 1849 static void kvm_cpu_instance_init(CPUState *cs) 1850 { 1851 Object *obj = OBJECT(RISCV_CPU(cs)); 1852 1853 riscv_init_kvm_registers(obj); 1854 1855 kvm_riscv_add_cpu_user_properties(obj); 1856 } 1857 1858 /* 1859 * We'll get here via the following path: 1860 * 1861 * riscv_cpu_realize() 1862 * -> cpu_exec_realizefn() 1863 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1864 */ 1865 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1866 { 1867 RISCVCPU *cpu = RISCV_CPU(cs); 1868 int ret; 1869 1870 if (riscv_has_ext(&cpu->env, RVV)) { 1871 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1872 if (ret) { 1873 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1874 strerrorname_np(errno)); 1875 return false; 1876 } 1877 } 1878 1879 return true; 1880 } 1881 1882 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1883 { 1884 CPURISCVState *env = &cpu->env; 1885 KVMScratchCPU kvmcpu; 1886 struct kvm_one_reg reg; 1887 uint64_t val; 1888 int ret; 1889 1890 /* short-circuit without spinning the scratch CPU */ 1891 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz && 1892 !riscv_has_ext(env, RVV)) { 1893 return; 1894 } 1895 1896 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1897 error_setg(errp, "Unable to create scratch KVM cpu"); 1898 return; 1899 } 1900 1901 if (cpu->cfg.ext_zicbom && 1902 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 1903 1904 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1905 kvm_cbom_blocksize.kvm_reg_id); 1906 reg.addr = (uint64_t)&val; 1907 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1908 if (ret != 0) { 1909 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 1910 return; 1911 } 1912 1913 if (cpu->cfg.cbom_blocksize != val) { 1914 error_setg(errp, "Unable to set cbom_blocksize to a different " 1915 "value than the host (%lu)", val); 1916 return; 1917 } 1918 } 1919 1920 if (cpu->cfg.ext_zicboz && 1921 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 1922 1923 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1924 kvm_cboz_blocksize.kvm_reg_id); 1925 reg.addr = (uint64_t)&val; 1926 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1927 if (ret != 0) { 1928 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 1929 return; 1930 } 1931 1932 if (cpu->cfg.cboz_blocksize != val) { 1933 error_setg(errp, "Unable to set cboz_blocksize to a different " 1934 "value than the host (%lu)", val); 1935 return; 1936 } 1937 } 1938 1939 /* Users are setting vlen, not vlenb */ 1940 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { 1941 if (!kvm_v_vlenb.supported) { 1942 error_setg(errp, "Unable to set 'vlenb': register not supported"); 1943 return; 1944 } 1945 1946 reg.id = kvm_v_vlenb.kvm_reg_id; 1947 reg.addr = (uint64_t)&val; 1948 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1949 if (ret != 0) { 1950 error_setg(errp, "Unable to read vlenb register, error %d", errno); 1951 return; 1952 } 1953 1954 if (cpu->cfg.vlenb != val) { 1955 error_setg(errp, "Unable to set 'vlen' to a different " 1956 "value than the host (%lu)", val * 8); 1957 return; 1958 } 1959 } 1960 1961 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1962 } 1963 1964 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1965 { 1966 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1967 1968 acc->cpu_instance_init = kvm_cpu_instance_init; 1969 acc->cpu_target_realize = kvm_cpu_realize; 1970 } 1971 1972 static const TypeInfo kvm_cpu_accel_type_info = { 1973 .name = ACCEL_CPU_NAME("kvm"), 1974 1975 .parent = TYPE_ACCEL_CPU, 1976 .class_init = kvm_cpu_accel_class_init, 1977 .abstract = true, 1978 }; 1979 static void kvm_cpu_accel_register_types(void) 1980 { 1981 type_register_static(&kvm_cpu_accel_type_info); 1982 } 1983 type_init(kvm_cpu_accel_register_types); 1984 1985 static void riscv_host_cpu_class_init(ObjectClass *c, void *data) 1986 { 1987 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1988 1989 #if defined(TARGET_RISCV32) 1990 mcc->misa_mxl_max = MXL_RV32; 1991 #elif defined(TARGET_RISCV64) 1992 mcc->misa_mxl_max = MXL_RV64; 1993 #endif 1994 } 1995 1996 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1997 { 1998 .name = TYPE_RISCV_CPU_HOST, 1999 .parent = TYPE_RISCV_CPU, 2000 .class_init = riscv_host_cpu_class_init, 2001 } 2002 }; 2003 2004 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 2005 2006 static const uint32_t ebreak_insn = 0x00100073; 2007 static const uint16_t c_ebreak_insn = 0x9002; 2008 2009 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2010 { 2011 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) { 2012 return -EINVAL; 2013 } 2014 2015 if ((bp->saved_insn & 0x3) == 0x3) { 2016 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) 2017 || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1)) { 2018 return -EINVAL; 2019 } 2020 } else { 2021 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) { 2022 return -EINVAL; 2023 } 2024 } 2025 2026 return 0; 2027 } 2028 2029 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2030 { 2031 uint32_t ebreak; 2032 uint16_t c_ebreak; 2033 2034 if ((bp->saved_insn & 0x3) == 0x3) { 2035 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) || 2036 ebreak != ebreak_insn || 2037 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2038 return -EINVAL; 2039 } 2040 } else { 2041 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) || 2042 c_ebreak != c_ebreak_insn || 2043 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1)) { 2044 return -EINVAL; 2045 } 2046 } 2047 2048 return 0; 2049 } 2050 2051 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2052 { 2053 /* TODO; To be implemented later. */ 2054 return -EINVAL; 2055 } 2056 2057 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2058 { 2059 /* TODO; To be implemented later. */ 2060 return -EINVAL; 2061 } 2062 2063 void kvm_arch_remove_all_hw_breakpoints(void) 2064 { 2065 /* TODO; To be implemented later. */ 2066 } 2067 2068 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 2069 { 2070 if (kvm_sw_breakpoints_active(cs)) { 2071 dbg->control |= KVM_GUESTDBG_ENABLE; 2072 } 2073 } 2074