1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ 76 KVM_REG_RISCV_CORE_REG(name)) 77 78 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ 79 KVM_REG_RISCV_CSR_REG(name)) 80 81 #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ 82 KVM_REG_RISCV_TIMER_REG(name)) 83 84 #define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) 85 86 #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) 87 88 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 89 do { \ 90 int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 91 if (ret) { \ 92 return ret; \ 93 } \ 94 } while (0) 95 96 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 97 do { \ 98 int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 99 if (ret) { \ 100 return ret; \ 101 } \ 102 } while (0) 103 104 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ 105 do { \ 106 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 107 if (ret) { \ 108 abort(); \ 109 } \ 110 } while (0) 111 112 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ 113 do { \ 114 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ 115 if (ret) { \ 116 abort(); \ 117 } \ 118 } while (0) 119 120 typedef struct KVMCPUConfig { 121 const char *name; 122 const char *description; 123 target_ulong offset; 124 int kvm_reg_id; 125 bool user_set; 126 bool supported; 127 } KVMCPUConfig; 128 129 #define KVM_MISA_CFG(_bit, _reg_id) \ 130 {.offset = _bit, .kvm_reg_id = _reg_id} 131 132 /* KVM ISA extensions */ 133 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 134 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 135 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 136 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 137 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 138 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 139 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 140 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 141 }; 142 143 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 144 const char *name, 145 void *opaque, Error **errp) 146 { 147 KVMCPUConfig *misa_ext_cfg = opaque; 148 target_ulong misa_bit = misa_ext_cfg->offset; 149 RISCVCPU *cpu = RISCV_CPU(obj); 150 CPURISCVState *env = &cpu->env; 151 bool value = env->misa_ext_mask & misa_bit; 152 153 visit_type_bool(v, name, &value, errp); 154 } 155 156 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 157 const char *name, 158 void *opaque, Error **errp) 159 { 160 KVMCPUConfig *misa_ext_cfg = opaque; 161 target_ulong misa_bit = misa_ext_cfg->offset; 162 RISCVCPU *cpu = RISCV_CPU(obj); 163 CPURISCVState *env = &cpu->env; 164 bool value, host_bit; 165 166 if (!visit_type_bool(v, name, &value, errp)) { 167 return; 168 } 169 170 host_bit = env->misa_ext_mask & misa_bit; 171 172 if (value == host_bit) { 173 return; 174 } 175 176 if (!value) { 177 misa_ext_cfg->user_set = true; 178 return; 179 } 180 181 /* 182 * Forbid users to enable extensions that aren't 183 * available in the hart. 184 */ 185 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 186 "enabled in the host", misa_ext_cfg->name); 187 } 188 189 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 190 { 191 CPURISCVState *env = &cpu->env; 192 uint64_t id, reg; 193 int i, ret; 194 195 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 196 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 197 target_ulong misa_bit = misa_cfg->offset; 198 199 if (!misa_cfg->user_set) { 200 continue; 201 } 202 203 /* If we're here we're going to disable the MISA bit */ 204 reg = 0; 205 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 206 misa_cfg->kvm_reg_id); 207 ret = kvm_set_one_reg(cs, id, ®); 208 if (ret != 0) { 209 /* 210 * We're not checking for -EINVAL because if the bit is about 211 * to be disabled, it means that it was already enabled by 212 * KVM. We determined that by fetching the 'isa' register 213 * during init() time. Any error at this point is worth 214 * aborting. 215 */ 216 error_report("Unable to set KVM reg %s, error %d", 217 misa_cfg->name, ret); 218 exit(EXIT_FAILURE); 219 } 220 env->misa_ext &= ~misa_bit; 221 } 222 } 223 224 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 225 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 226 .kvm_reg_id = _reg_id} 227 228 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 229 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 230 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 231 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 232 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 233 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 234 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 235 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 236 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 237 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 238 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 239 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 240 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 241 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 242 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 243 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 244 }; 245 246 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 247 { 248 return (void *)&cpu->cfg + kvmcfg->offset; 249 } 250 251 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 252 uint32_t val) 253 { 254 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 255 256 *ext_enabled = val; 257 } 258 259 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 260 KVMCPUConfig *multi_ext) 261 { 262 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 263 264 return *ext_enabled; 265 } 266 267 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 268 const char *name, 269 void *opaque, Error **errp) 270 { 271 KVMCPUConfig *multi_ext_cfg = opaque; 272 RISCVCPU *cpu = RISCV_CPU(obj); 273 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 274 275 visit_type_bool(v, name, &value, errp); 276 } 277 278 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 279 const char *name, 280 void *opaque, Error **errp) 281 { 282 KVMCPUConfig *multi_ext_cfg = opaque; 283 RISCVCPU *cpu = RISCV_CPU(obj); 284 bool value, host_val; 285 286 if (!visit_type_bool(v, name, &value, errp)) { 287 return; 288 } 289 290 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 291 292 /* 293 * Ignore if the user is setting the same value 294 * as the host. 295 */ 296 if (value == host_val) { 297 return; 298 } 299 300 if (!multi_ext_cfg->supported) { 301 /* 302 * Error out if the user is trying to enable an 303 * extension that KVM doesn't support. Ignore 304 * option otherwise. 305 */ 306 if (value) { 307 error_setg(errp, "KVM does not support disabling extension %s", 308 multi_ext_cfg->name); 309 } 310 311 return; 312 } 313 314 multi_ext_cfg->user_set = true; 315 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 316 } 317 318 static KVMCPUConfig kvm_cbom_blocksize = { 319 .name = "cbom_blocksize", 320 .offset = CPU_CFG_OFFSET(cbom_blocksize), 321 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 322 }; 323 324 static KVMCPUConfig kvm_cboz_blocksize = { 325 .name = "cboz_blocksize", 326 .offset = CPU_CFG_OFFSET(cboz_blocksize), 327 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 328 }; 329 330 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 331 const char *name, 332 void *opaque, Error **errp) 333 { 334 KVMCPUConfig *cbomz_cfg = opaque; 335 RISCVCPU *cpu = RISCV_CPU(obj); 336 uint16_t value, *host_val; 337 338 if (!visit_type_uint16(v, name, &value, errp)) { 339 return; 340 } 341 342 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 343 344 if (value != *host_val) { 345 error_report("Unable to set %s to a different value than " 346 "the host (%u)", 347 cbomz_cfg->name, *host_val); 348 exit(EXIT_FAILURE); 349 } 350 351 cbomz_cfg->user_set = true; 352 } 353 354 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 355 { 356 CPURISCVState *env = &cpu->env; 357 uint64_t id, reg; 358 int i, ret; 359 360 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 361 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 362 363 if (!multi_ext_cfg->user_set) { 364 continue; 365 } 366 367 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 368 multi_ext_cfg->kvm_reg_id); 369 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 370 ret = kvm_set_one_reg(cs, id, ®); 371 if (ret != 0) { 372 error_report("Unable to %s extension %s in KVM, error %d", 373 reg ? "enable" : "disable", 374 multi_ext_cfg->name, ret); 375 exit(EXIT_FAILURE); 376 } 377 } 378 } 379 380 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 381 const char *name, 382 void *opaque, Error **errp) 383 { 384 bool value = false; 385 386 visit_type_bool(v, name, &value, errp); 387 } 388 389 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 390 const char *name, 391 void *opaque, Error **errp) 392 { 393 const char *propname = opaque; 394 bool value; 395 396 if (!visit_type_bool(v, name, &value, errp)) { 397 return; 398 } 399 400 if (value) { 401 error_setg(errp, "extension %s is not available with KVM", 402 propname); 403 } 404 } 405 406 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 407 { 408 /* Check if KVM created the property already */ 409 if (object_property_find(obj, prop_name)) { 410 return; 411 } 412 413 /* 414 * Set the default to disabled for every extension 415 * unknown to KVM and error out if the user attempts 416 * to enable any of them. 417 */ 418 object_property_add(obj, prop_name, "bool", 419 cpu_get_cfg_unavailable, 420 cpu_set_cfg_unavailable, 421 NULL, (void *)prop_name); 422 } 423 424 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 425 const RISCVCPUMultiExtConfig *array) 426 { 427 const RISCVCPUMultiExtConfig *prop; 428 429 g_assert(array); 430 431 for (prop = array; prop && prop->name; prop++) { 432 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 433 } 434 } 435 436 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 437 { 438 int i; 439 440 riscv_add_satp_mode_properties(cpu_obj); 441 442 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 443 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 444 int bit = misa_cfg->offset; 445 446 misa_cfg->name = riscv_get_misa_ext_name(bit); 447 misa_cfg->description = riscv_get_misa_ext_description(bit); 448 449 object_property_add(cpu_obj, misa_cfg->name, "bool", 450 kvm_cpu_get_misa_ext_cfg, 451 kvm_cpu_set_misa_ext_cfg, 452 NULL, misa_cfg); 453 object_property_set_description(cpu_obj, misa_cfg->name, 454 misa_cfg->description); 455 } 456 457 for (i = 0; misa_bits[i] != 0; i++) { 458 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 459 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 460 } 461 462 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 463 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 464 465 object_property_add(cpu_obj, multi_cfg->name, "bool", 466 kvm_cpu_get_multi_ext_cfg, 467 kvm_cpu_set_multi_ext_cfg, 468 NULL, multi_cfg); 469 } 470 471 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 472 NULL, kvm_cpu_set_cbomz_blksize, 473 NULL, &kvm_cbom_blocksize); 474 475 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 476 NULL, kvm_cpu_set_cbomz_blksize, 477 NULL, &kvm_cboz_blocksize); 478 479 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 480 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 481 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 482 } 483 484 static int kvm_riscv_get_regs_core(CPUState *cs) 485 { 486 int ret = 0; 487 int i; 488 target_ulong reg; 489 CPURISCVState *env = &RISCV_CPU(cs)->env; 490 491 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 492 if (ret) { 493 return ret; 494 } 495 env->pc = reg; 496 497 for (i = 1; i < 32; i++) { 498 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 499 ret = kvm_get_one_reg(cs, id, ®); 500 if (ret) { 501 return ret; 502 } 503 env->gpr[i] = reg; 504 } 505 506 return ret; 507 } 508 509 static int kvm_riscv_put_regs_core(CPUState *cs) 510 { 511 int ret = 0; 512 int i; 513 target_ulong reg; 514 CPURISCVState *env = &RISCV_CPU(cs)->env; 515 516 reg = env->pc; 517 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 518 if (ret) { 519 return ret; 520 } 521 522 for (i = 1; i < 32; i++) { 523 uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); 524 reg = env->gpr[i]; 525 ret = kvm_set_one_reg(cs, id, ®); 526 if (ret) { 527 return ret; 528 } 529 } 530 531 return ret; 532 } 533 534 static int kvm_riscv_get_regs_csr(CPUState *cs) 535 { 536 int ret = 0; 537 CPURISCVState *env = &RISCV_CPU(cs)->env; 538 539 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 540 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 541 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 542 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 543 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 544 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 545 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 546 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 547 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 548 return ret; 549 } 550 551 static int kvm_riscv_put_regs_csr(CPUState *cs) 552 { 553 int ret = 0; 554 CPURISCVState *env = &RISCV_CPU(cs)->env; 555 556 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 557 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 558 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 559 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 560 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 561 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 562 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 563 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 564 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 565 566 return ret; 567 } 568 569 static int kvm_riscv_get_regs_fp(CPUState *cs) 570 { 571 int ret = 0; 572 int i; 573 CPURISCVState *env = &RISCV_CPU(cs)->env; 574 575 if (riscv_has_ext(env, RVD)) { 576 uint64_t reg; 577 for (i = 0; i < 32; i++) { 578 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 579 if (ret) { 580 return ret; 581 } 582 env->fpr[i] = reg; 583 } 584 return ret; 585 } 586 587 if (riscv_has_ext(env, RVF)) { 588 uint32_t reg; 589 for (i = 0; i < 32; i++) { 590 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 591 if (ret) { 592 return ret; 593 } 594 env->fpr[i] = reg; 595 } 596 return ret; 597 } 598 599 return ret; 600 } 601 602 static int kvm_riscv_put_regs_fp(CPUState *cs) 603 { 604 int ret = 0; 605 int i; 606 CPURISCVState *env = &RISCV_CPU(cs)->env; 607 608 if (riscv_has_ext(env, RVD)) { 609 uint64_t reg; 610 for (i = 0; i < 32; i++) { 611 reg = env->fpr[i]; 612 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); 613 if (ret) { 614 return ret; 615 } 616 } 617 return ret; 618 } 619 620 if (riscv_has_ext(env, RVF)) { 621 uint32_t reg; 622 for (i = 0; i < 32; i++) { 623 reg = env->fpr[i]; 624 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®); 625 if (ret) { 626 return ret; 627 } 628 } 629 return ret; 630 } 631 632 return ret; 633 } 634 635 static void kvm_riscv_get_regs_timer(CPUState *cs) 636 { 637 CPURISCVState *env = &RISCV_CPU(cs)->env; 638 639 if (env->kvm_timer_dirty) { 640 return; 641 } 642 643 KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); 644 KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); 645 KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); 646 KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); 647 648 env->kvm_timer_dirty = true; 649 } 650 651 static void kvm_riscv_put_regs_timer(CPUState *cs) 652 { 653 uint64_t reg; 654 CPURISCVState *env = &RISCV_CPU(cs)->env; 655 656 if (!env->kvm_timer_dirty) { 657 return; 658 } 659 660 KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); 661 KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); 662 663 /* 664 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 665 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 666 * doesn't matter that adaping in QEMU now. 667 * TODO If KVM changes, adapt here. 668 */ 669 if (env->kvm_timer_state) { 670 KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); 671 } 672 673 /* 674 * For now, migration will not work between Hosts with different timer 675 * frequency. Therefore, we should check whether they are the same here 676 * during the migration. 677 */ 678 if (migration_is_running(migrate_get_current()->state)) { 679 KVM_RISCV_GET_TIMER(cs, env, frequency, reg); 680 if (reg != env->kvm_timer_frequency) { 681 error_report("Dst Hosts timer frequency != Src Hosts"); 682 } 683 } 684 685 env->kvm_timer_dirty = false; 686 } 687 688 typedef struct KVMScratchCPU { 689 int kvmfd; 690 int vmfd; 691 int cpufd; 692 } KVMScratchCPU; 693 694 /* 695 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 696 * from target/arm/kvm.c. 697 */ 698 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 699 { 700 int kvmfd = -1, vmfd = -1, cpufd = -1; 701 702 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 703 if (kvmfd < 0) { 704 goto err; 705 } 706 do { 707 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 708 } while (vmfd == -1 && errno == EINTR); 709 if (vmfd < 0) { 710 goto err; 711 } 712 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 713 if (cpufd < 0) { 714 goto err; 715 } 716 717 scratch->kvmfd = kvmfd; 718 scratch->vmfd = vmfd; 719 scratch->cpufd = cpufd; 720 721 return true; 722 723 err: 724 if (cpufd >= 0) { 725 close(cpufd); 726 } 727 if (vmfd >= 0) { 728 close(vmfd); 729 } 730 if (kvmfd >= 0) { 731 close(kvmfd); 732 } 733 734 return false; 735 } 736 737 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 738 { 739 close(scratch->cpufd); 740 close(scratch->vmfd); 741 close(scratch->kvmfd); 742 } 743 744 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 745 { 746 CPURISCVState *env = &cpu->env; 747 struct kvm_one_reg reg; 748 int ret; 749 750 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 751 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 752 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 753 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 754 if (ret != 0) { 755 error_report("Unable to retrieve mvendorid from host, error %d", ret); 756 } 757 758 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 759 KVM_REG_RISCV_CONFIG_REG(marchid)); 760 reg.addr = (uint64_t)&cpu->cfg.marchid; 761 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 762 if (ret != 0) { 763 error_report("Unable to retrieve marchid from host, error %d", ret); 764 } 765 766 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 767 KVM_REG_RISCV_CONFIG_REG(mimpid)); 768 reg.addr = (uint64_t)&cpu->cfg.mimpid; 769 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 770 if (ret != 0) { 771 error_report("Unable to retrieve mimpid from host, error %d", ret); 772 } 773 } 774 775 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 776 KVMScratchCPU *kvmcpu) 777 { 778 CPURISCVState *env = &cpu->env; 779 struct kvm_one_reg reg; 780 int ret; 781 782 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 783 KVM_REG_RISCV_CONFIG_REG(isa)); 784 reg.addr = (uint64_t)&env->misa_ext_mask; 785 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 786 787 if (ret) { 788 error_report("Unable to fetch ISA register from KVM, " 789 "error %d", ret); 790 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 791 exit(EXIT_FAILURE); 792 } 793 794 env->misa_ext = env->misa_ext_mask; 795 } 796 797 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 798 KVMCPUConfig *cbomz_cfg) 799 { 800 CPURISCVState *env = &cpu->env; 801 struct kvm_one_reg reg; 802 int ret; 803 804 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 805 cbomz_cfg->kvm_reg_id); 806 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 807 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 808 if (ret != 0) { 809 error_report("Unable to read KVM reg %s, error %d", 810 cbomz_cfg->name, ret); 811 exit(EXIT_FAILURE); 812 } 813 } 814 815 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 816 KVMScratchCPU *kvmcpu) 817 { 818 CPURISCVState *env = &cpu->env; 819 uint64_t val; 820 int i, ret; 821 822 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 823 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 824 struct kvm_one_reg reg; 825 826 reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, 827 multi_ext_cfg->kvm_reg_id); 828 reg.addr = (uint64_t)&val; 829 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 830 if (ret != 0) { 831 if (errno == EINVAL) { 832 /* Silently default to 'false' if KVM does not support it. */ 833 multi_ext_cfg->supported = false; 834 val = false; 835 } else { 836 error_report("Unable to read ISA_EXT KVM register %s, " 837 "error code: %s", multi_ext_cfg->name, 838 strerrorname_np(errno)); 839 exit(EXIT_FAILURE); 840 } 841 } else { 842 multi_ext_cfg->supported = true; 843 } 844 845 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 846 } 847 848 if (cpu->cfg.ext_zicbom) { 849 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 850 } 851 852 if (cpu->cfg.ext_zicboz) { 853 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 854 } 855 } 856 857 static int uint64_cmp(const void *a, const void *b) 858 { 859 uint64_t val1 = *(const uint64_t *)a; 860 uint64_t val2 = *(const uint64_t *)b; 861 862 if (val1 < val2) { 863 return -1; 864 } 865 866 if (val1 > val2) { 867 return 1; 868 } 869 870 return 0; 871 } 872 873 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 874 { 875 KVMCPUConfig *multi_ext_cfg; 876 struct kvm_one_reg reg; 877 struct kvm_reg_list rl_struct; 878 struct kvm_reg_list *reglist; 879 uint64_t val, reg_id, *reg_search; 880 int i, ret; 881 882 rl_struct.n = 0; 883 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 884 885 /* 886 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 887 * (EINVAL). Use read_legacy() in this case. 888 */ 889 if (errno == EINVAL) { 890 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 891 } else if (errno != E2BIG) { 892 /* 893 * E2BIG is an expected error message for the API since we 894 * don't know the number of registers. The right amount will 895 * be written in rl_struct.n. 896 * 897 * Error out if we get any other errno. 898 */ 899 error_report("Error when accessing get-reg-list, code: %s", 900 strerrorname_np(errno)); 901 exit(EXIT_FAILURE); 902 } 903 904 reglist = g_malloc(sizeof(struct kvm_reg_list) + 905 rl_struct.n * sizeof(uint64_t)); 906 reglist->n = rl_struct.n; 907 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 908 if (ret) { 909 error_report("Error when reading KVM_GET_REG_LIST, code %s ", 910 strerrorname_np(errno)); 911 exit(EXIT_FAILURE); 912 } 913 914 /* sort reglist to use bsearch() */ 915 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 916 917 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 918 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 919 reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, 920 multi_ext_cfg->kvm_reg_id); 921 reg_search = bsearch(®_id, reglist->reg, reglist->n, 922 sizeof(uint64_t), uint64_cmp); 923 if (!reg_search) { 924 continue; 925 } 926 927 reg.id = reg_id; 928 reg.addr = (uint64_t)&val; 929 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 930 if (ret != 0) { 931 error_report("Unable to read ISA_EXT KVM register %s, " 932 "error code: %s", multi_ext_cfg->name, 933 strerrorname_np(errno)); 934 exit(EXIT_FAILURE); 935 } 936 937 multi_ext_cfg->supported = true; 938 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 939 } 940 941 if (cpu->cfg.ext_zicbom) { 942 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 943 } 944 945 if (cpu->cfg.ext_zicboz) { 946 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 947 } 948 } 949 950 static void riscv_init_kvm_registers(Object *cpu_obj) 951 { 952 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 953 KVMScratchCPU kvmcpu; 954 955 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 956 return; 957 } 958 959 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 960 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 961 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 962 963 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 964 } 965 966 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 967 KVM_CAP_LAST_INFO 968 }; 969 970 int kvm_arch_get_registers(CPUState *cs) 971 { 972 int ret = 0; 973 974 ret = kvm_riscv_get_regs_core(cs); 975 if (ret) { 976 return ret; 977 } 978 979 ret = kvm_riscv_get_regs_csr(cs); 980 if (ret) { 981 return ret; 982 } 983 984 ret = kvm_riscv_get_regs_fp(cs); 985 if (ret) { 986 return ret; 987 } 988 989 return ret; 990 } 991 992 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 993 { 994 if (cap_has_mp_state) { 995 struct kvm_mp_state mp_state = { 996 .mp_state = state 997 }; 998 999 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1000 if (ret) { 1001 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1002 __func__, ret, strerror(-ret)); 1003 return -1; 1004 } 1005 } 1006 1007 return 0; 1008 } 1009 1010 int kvm_arch_put_registers(CPUState *cs, int level) 1011 { 1012 int ret = 0; 1013 1014 ret = kvm_riscv_put_regs_core(cs); 1015 if (ret) { 1016 return ret; 1017 } 1018 1019 ret = kvm_riscv_put_regs_csr(cs); 1020 if (ret) { 1021 return ret; 1022 } 1023 1024 ret = kvm_riscv_put_regs_fp(cs); 1025 if (ret) { 1026 return ret; 1027 } 1028 1029 if (KVM_PUT_RESET_STATE == level) { 1030 RISCVCPU *cpu = RISCV_CPU(cs); 1031 if (cs->cpu_index == 0) { 1032 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1033 } else { 1034 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1035 } 1036 if (ret) { 1037 return ret; 1038 } 1039 } 1040 1041 return ret; 1042 } 1043 1044 int kvm_arch_release_virq_post(int virq) 1045 { 1046 return 0; 1047 } 1048 1049 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1050 uint64_t address, uint32_t data, PCIDevice *dev) 1051 { 1052 return 0; 1053 } 1054 1055 int kvm_arch_destroy_vcpu(CPUState *cs) 1056 { 1057 return 0; 1058 } 1059 1060 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1061 { 1062 return cpu->cpu_index; 1063 } 1064 1065 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1066 RunState state) 1067 { 1068 CPUState *cs = opaque; 1069 1070 if (running) { 1071 kvm_riscv_put_regs_timer(cs); 1072 } else { 1073 kvm_riscv_get_regs_timer(cs); 1074 } 1075 } 1076 1077 void kvm_arch_init_irq_routing(KVMState *s) 1078 { 1079 } 1080 1081 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1082 { 1083 CPURISCVState *env = &cpu->env; 1084 target_ulong reg; 1085 uint64_t id; 1086 int ret; 1087 1088 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1089 KVM_REG_RISCV_CONFIG_REG(mvendorid)); 1090 /* 1091 * cfg.mvendorid is an uint32 but a target_ulong will 1092 * be written. Assign it to a target_ulong var to avoid 1093 * writing pieces of other cpu->cfg fields in the reg. 1094 */ 1095 reg = cpu->cfg.mvendorid; 1096 ret = kvm_set_one_reg(cs, id, ®); 1097 if (ret != 0) { 1098 return ret; 1099 } 1100 1101 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1102 KVM_REG_RISCV_CONFIG_REG(marchid)); 1103 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1104 if (ret != 0) { 1105 return ret; 1106 } 1107 1108 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, 1109 KVM_REG_RISCV_CONFIG_REG(mimpid)); 1110 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1111 1112 return ret; 1113 } 1114 1115 int kvm_arch_init_vcpu(CPUState *cs) 1116 { 1117 int ret = 0; 1118 RISCVCPU *cpu = RISCV_CPU(cs); 1119 1120 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1121 1122 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1123 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1124 if (ret != 0) { 1125 return ret; 1126 } 1127 } 1128 1129 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1130 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1131 1132 return ret; 1133 } 1134 1135 int kvm_arch_msi_data_to_gsi(uint32_t data) 1136 { 1137 abort(); 1138 } 1139 1140 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1141 int vector, PCIDevice *dev) 1142 { 1143 return 0; 1144 } 1145 1146 int kvm_arch_get_default_type(MachineState *ms) 1147 { 1148 return 0; 1149 } 1150 1151 int kvm_arch_init(MachineState *ms, KVMState *s) 1152 { 1153 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1154 return 0; 1155 } 1156 1157 int kvm_arch_irqchip_create(KVMState *s) 1158 { 1159 if (kvm_kernel_irqchip_split()) { 1160 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1161 exit(1); 1162 } 1163 1164 /* 1165 * We can create the VAIA using the newer device control API. 1166 */ 1167 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1168 } 1169 1170 int kvm_arch_process_async_events(CPUState *cs) 1171 { 1172 return 0; 1173 } 1174 1175 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1176 { 1177 } 1178 1179 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1180 { 1181 return MEMTXATTRS_UNSPECIFIED; 1182 } 1183 1184 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1185 { 1186 return true; 1187 } 1188 1189 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1190 { 1191 int ret = 0; 1192 unsigned char ch; 1193 switch (run->riscv_sbi.extension_id) { 1194 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1195 ch = run->riscv_sbi.args[0]; 1196 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1197 break; 1198 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1199 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1200 if (ret == sizeof(ch)) { 1201 run->riscv_sbi.ret[0] = ch; 1202 } else { 1203 run->riscv_sbi.ret[0] = -1; 1204 } 1205 ret = 0; 1206 break; 1207 default: 1208 qemu_log_mask(LOG_UNIMP, 1209 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1210 __func__, run->riscv_sbi.extension_id); 1211 ret = -1; 1212 break; 1213 } 1214 return ret; 1215 } 1216 1217 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1218 { 1219 int ret = 0; 1220 switch (run->exit_reason) { 1221 case KVM_EXIT_RISCV_SBI: 1222 ret = kvm_riscv_handle_sbi(cs, run); 1223 break; 1224 default: 1225 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1226 __func__, run->exit_reason); 1227 ret = -1; 1228 break; 1229 } 1230 return ret; 1231 } 1232 1233 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1234 { 1235 CPURISCVState *env = &cpu->env; 1236 int i; 1237 1238 if (!kvm_enabled()) { 1239 return; 1240 } 1241 for (i = 0; i < 32; i++) { 1242 env->gpr[i] = 0; 1243 } 1244 env->pc = cpu->env.kernel_addr; 1245 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1246 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1247 env->satp = 0; 1248 env->mie = 0; 1249 env->stvec = 0; 1250 env->sscratch = 0; 1251 env->sepc = 0; 1252 env->scause = 0; 1253 env->stval = 0; 1254 env->mip = 0; 1255 } 1256 1257 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1258 { 1259 int ret; 1260 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1261 1262 if (irq != IRQ_S_EXT) { 1263 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1264 abort(); 1265 } 1266 1267 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1268 if (ret < 0) { 1269 perror("Set irq failed"); 1270 abort(); 1271 } 1272 } 1273 1274 bool kvm_arch_cpu_check_are_resettable(void) 1275 { 1276 return true; 1277 } 1278 1279 static int aia_mode; 1280 1281 static const char *kvm_aia_mode_str(uint64_t mode) 1282 { 1283 switch (mode) { 1284 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1285 return "emul"; 1286 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1287 return "hwaccel"; 1288 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1289 default: 1290 return "auto"; 1291 }; 1292 } 1293 1294 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1295 { 1296 return g_strdup(kvm_aia_mode_str(aia_mode)); 1297 } 1298 1299 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1300 { 1301 if (!strcmp(val, "emul")) { 1302 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1303 } else if (!strcmp(val, "hwaccel")) { 1304 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1305 } else if (!strcmp(val, "auto")) { 1306 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1307 } else { 1308 error_setg(errp, "Invalid KVM AIA mode"); 1309 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1310 } 1311 } 1312 1313 void kvm_arch_accel_class_init(ObjectClass *oc) 1314 { 1315 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1316 riscv_set_kvm_aia); 1317 object_class_property_set_description(oc, "riscv-aia", 1318 "Set KVM AIA mode. Valid values are " 1319 "emul, hwaccel, and auto. Default " 1320 "is auto."); 1321 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1322 "auto"); 1323 } 1324 1325 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1326 uint64_t aia_irq_num, uint64_t aia_msi_num, 1327 uint64_t aplic_base, uint64_t imsic_base, 1328 uint64_t guest_num) 1329 { 1330 int ret, i; 1331 int aia_fd = -1; 1332 uint64_t default_aia_mode; 1333 uint64_t socket_count = riscv_socket_count(machine); 1334 uint64_t max_hart_per_socket = 0; 1335 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1336 uint64_t socket_bits, hart_bits, guest_bits; 1337 1338 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1339 1340 if (aia_fd < 0) { 1341 error_report("Unable to create in-kernel irqchip"); 1342 exit(1); 1343 } 1344 1345 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1346 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1347 &default_aia_mode, false, NULL); 1348 if (ret < 0) { 1349 error_report("KVM AIA: failed to get current KVM AIA mode"); 1350 exit(1); 1351 } 1352 qemu_log("KVM AIA: default mode is %s\n", 1353 kvm_aia_mode_str(default_aia_mode)); 1354 1355 if (default_aia_mode != aia_mode) { 1356 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1357 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1358 &aia_mode, true, NULL); 1359 if (ret < 0) 1360 warn_report("KVM AIA: failed to set KVM AIA mode"); 1361 else 1362 qemu_log("KVM AIA: set current mode to %s\n", 1363 kvm_aia_mode_str(aia_mode)); 1364 } 1365 1366 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1367 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1368 &aia_irq_num, true, NULL); 1369 if (ret < 0) { 1370 error_report("KVM AIA: failed to set number of input irq lines"); 1371 exit(1); 1372 } 1373 1374 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1375 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1376 &aia_msi_num, true, NULL); 1377 if (ret < 0) { 1378 error_report("KVM AIA: failed to set number of msi"); 1379 exit(1); 1380 } 1381 1382 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1383 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1384 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1385 &socket_bits, true, NULL); 1386 if (ret < 0) { 1387 error_report("KVM AIA: failed to set group_bits"); 1388 exit(1); 1389 } 1390 1391 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1392 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1393 &group_shift, true, NULL); 1394 if (ret < 0) { 1395 error_report("KVM AIA: failed to set group_shift"); 1396 exit(1); 1397 } 1398 1399 guest_bits = guest_num == 0 ? 0 : 1400 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1401 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1402 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1403 &guest_bits, true, NULL); 1404 if (ret < 0) { 1405 error_report("KVM AIA: failed to set guest_bits"); 1406 exit(1); 1407 } 1408 1409 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1410 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1411 &aplic_base, true, NULL); 1412 if (ret < 0) { 1413 error_report("KVM AIA: failed to set the base address of APLIC"); 1414 exit(1); 1415 } 1416 1417 for (socket = 0; socket < socket_count; socket++) { 1418 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1419 hart_count = riscv_socket_hart_count(machine, socket); 1420 base_hart = riscv_socket_first_hartid(machine, socket); 1421 1422 if (max_hart_per_socket < hart_count) { 1423 max_hart_per_socket = hart_count; 1424 } 1425 1426 for (i = 0; i < hart_count; i++) { 1427 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1428 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1429 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1430 &imsic_addr, true, NULL); 1431 if (ret < 0) { 1432 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1433 exit(1); 1434 } 1435 } 1436 } 1437 1438 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1439 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1440 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1441 &hart_bits, true, NULL); 1442 if (ret < 0) { 1443 error_report("KVM AIA: failed to set hart_bits"); 1444 exit(1); 1445 } 1446 1447 if (kvm_has_gsi_routing()) { 1448 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1449 /* KVM AIA only has one APLIC instance */ 1450 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1451 } 1452 kvm_gsi_routing_allowed = true; 1453 kvm_irqchip_commit_routes(kvm_state); 1454 } 1455 1456 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1457 KVM_DEV_RISCV_AIA_CTRL_INIT, 1458 NULL, true, NULL); 1459 if (ret < 0) { 1460 error_report("KVM AIA: initialized fail"); 1461 exit(1); 1462 } 1463 1464 kvm_msi_via_irqfd_allowed = true; 1465 } 1466 1467 static void kvm_cpu_instance_init(CPUState *cs) 1468 { 1469 Object *obj = OBJECT(RISCV_CPU(cs)); 1470 DeviceState *dev = DEVICE(obj); 1471 1472 riscv_init_kvm_registers(obj); 1473 1474 kvm_riscv_add_cpu_user_properties(obj); 1475 1476 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1477 /* Check if we have a specific KVM handler for the option */ 1478 if (object_property_find(obj, prop->name)) { 1479 continue; 1480 } 1481 qdev_property_add_static(dev, prop); 1482 } 1483 } 1484 1485 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1486 { 1487 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1488 1489 acc->cpu_instance_init = kvm_cpu_instance_init; 1490 } 1491 1492 static const TypeInfo kvm_cpu_accel_type_info = { 1493 .name = ACCEL_CPU_NAME("kvm"), 1494 1495 .parent = TYPE_ACCEL_CPU, 1496 .class_init = kvm_cpu_accel_class_init, 1497 .abstract = true, 1498 }; 1499 static void kvm_cpu_accel_register_types(void) 1500 { 1501 type_register_static(&kvm_cpu_accel_type_info); 1502 } 1503 type_init(kvm_cpu_accel_register_types); 1504 1505 static void riscv_host_cpu_init(Object *obj) 1506 { 1507 CPURISCVState *env = &RISCV_CPU(obj)->env; 1508 1509 #if defined(TARGET_RISCV32) 1510 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1511 #elif defined(TARGET_RISCV64) 1512 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1513 #endif 1514 } 1515 1516 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1517 { 1518 .name = TYPE_RISCV_CPU_HOST, 1519 .parent = TYPE_RISCV_CPU, 1520 .instance_init = riscv_host_cpu_init, 1521 } 1522 }; 1523 1524 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1525