1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/kvm.h" 32 #include "sysemu/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "hw/core/accel-cpu.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "exec/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/misc.h" 48 #include "sysemu/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) 90 { 91 uint64_t size_ctz = __builtin_ctz(size_b); 92 93 return id | (size_ctz << KVM_REG_SIZE_SHIFT); 94 } 95 96 static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, 97 uint64_t idx) 98 { 99 uint64_t id; 100 size_t size_b; 101 102 g_assert(idx < 32); 103 104 id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); 105 size_b = cpu->cfg.vlenb; 106 107 return kvm_encode_reg_size_id(id, size_b); 108 } 109 110 #define RISCV_CORE_REG(env, name) \ 111 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 112 KVM_REG_RISCV_CORE_REG(name)) 113 114 #define RISCV_CSR_REG(env, name) \ 115 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 116 KVM_REG_RISCV_CSR_REG(name)) 117 118 #define RISCV_CONFIG_REG(env, name) \ 119 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 120 KVM_REG_RISCV_CONFIG_REG(name)) 121 122 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 123 KVM_REG_RISCV_TIMER_REG(name)) 124 125 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 126 127 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 128 129 #define RISCV_VECTOR_CSR_REG(env, name) \ 130 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ 131 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 132 133 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 134 do { \ 135 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 136 if (_ret) { \ 137 return _ret; \ 138 } \ 139 } while (0) 140 141 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 142 do { \ 143 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 144 if (_ret) { \ 145 return _ret; \ 146 } \ 147 } while (0) 148 149 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 150 do { \ 151 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 152 if (ret) { \ 153 abort(); \ 154 } \ 155 } while (0) 156 157 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 158 do { \ 159 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 160 if (ret) { \ 161 abort(); \ 162 } \ 163 } while (0) 164 165 typedef struct KVMCPUConfig { 166 const char *name; 167 const char *description; 168 target_ulong offset; 169 uint64_t kvm_reg_id; 170 bool user_set; 171 bool supported; 172 } KVMCPUConfig; 173 174 #define KVM_MISA_CFG(_bit, _reg_id) \ 175 {.offset = _bit, .kvm_reg_id = _reg_id} 176 177 /* KVM ISA extensions */ 178 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 179 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 180 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 181 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 182 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 184 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 185 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 186 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 187 }; 188 189 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 190 const char *name, 191 void *opaque, Error **errp) 192 { 193 KVMCPUConfig *misa_ext_cfg = opaque; 194 target_ulong misa_bit = misa_ext_cfg->offset; 195 RISCVCPU *cpu = RISCV_CPU(obj); 196 CPURISCVState *env = &cpu->env; 197 bool value = env->misa_ext_mask & misa_bit; 198 199 visit_type_bool(v, name, &value, errp); 200 } 201 202 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 203 const char *name, 204 void *opaque, Error **errp) 205 { 206 KVMCPUConfig *misa_ext_cfg = opaque; 207 target_ulong misa_bit = misa_ext_cfg->offset; 208 RISCVCPU *cpu = RISCV_CPU(obj); 209 CPURISCVState *env = &cpu->env; 210 bool value, host_bit; 211 212 if (!visit_type_bool(v, name, &value, errp)) { 213 return; 214 } 215 216 host_bit = env->misa_ext_mask & misa_bit; 217 218 if (value == host_bit) { 219 return; 220 } 221 222 if (!value) { 223 misa_ext_cfg->user_set = true; 224 return; 225 } 226 227 /* 228 * Forbid users to enable extensions that aren't 229 * available in the hart. 230 */ 231 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 232 "enabled in the host", misa_ext_cfg->name); 233 } 234 235 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 236 { 237 CPURISCVState *env = &cpu->env; 238 uint64_t id, reg; 239 int i, ret; 240 241 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 242 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 243 target_ulong misa_bit = misa_cfg->offset; 244 245 if (!misa_cfg->user_set) { 246 continue; 247 } 248 249 /* If we're here we're going to disable the MISA bit */ 250 reg = 0; 251 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 252 misa_cfg->kvm_reg_id); 253 ret = kvm_set_one_reg(cs, id, ®); 254 if (ret != 0) { 255 /* 256 * We're not checking for -EINVAL because if the bit is about 257 * to be disabled, it means that it was already enabled by 258 * KVM. We determined that by fetching the 'isa' register 259 * during init() time. Any error at this point is worth 260 * aborting. 261 */ 262 error_report("Unable to set KVM reg %s, error %d", 263 misa_cfg->name, ret); 264 exit(EXIT_FAILURE); 265 } 266 env->misa_ext &= ~misa_bit; 267 } 268 } 269 270 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 271 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 272 .kvm_reg_id = _reg_id} 273 274 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 275 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 276 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 277 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 278 KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), 279 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 280 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 281 KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), 282 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 283 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 284 KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), 285 KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), 286 KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), 287 KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), 288 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 289 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 290 KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), 291 KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), 292 KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), 293 KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), 294 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 295 KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), 296 KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), 297 KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), 298 KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), 299 KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), 300 KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), 301 KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), 302 KVM_EXT_CFG("ztso", ext_ztso, KVM_RISCV_ISA_EXT_ZTSO), 303 KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), 304 KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), 305 KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), 306 KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), 307 KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), 308 KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), 309 KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), 310 KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), 311 KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), 312 KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), 313 KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), 314 KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), 315 KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), 316 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 317 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 318 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 319 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 320 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 321 }; 322 323 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 324 { 325 return (void *)&cpu->cfg + kvmcfg->offset; 326 } 327 328 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 329 uint32_t val) 330 { 331 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 332 333 *ext_enabled = val; 334 } 335 336 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 337 KVMCPUConfig *multi_ext) 338 { 339 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 340 341 return *ext_enabled; 342 } 343 344 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 345 const char *name, 346 void *opaque, Error **errp) 347 { 348 KVMCPUConfig *multi_ext_cfg = opaque; 349 RISCVCPU *cpu = RISCV_CPU(obj); 350 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 351 352 visit_type_bool(v, name, &value, errp); 353 } 354 355 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 356 const char *name, 357 void *opaque, Error **errp) 358 { 359 KVMCPUConfig *multi_ext_cfg = opaque; 360 RISCVCPU *cpu = RISCV_CPU(obj); 361 bool value, host_val; 362 363 if (!visit_type_bool(v, name, &value, errp)) { 364 return; 365 } 366 367 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 368 369 /* 370 * Ignore if the user is setting the same value 371 * as the host. 372 */ 373 if (value == host_val) { 374 return; 375 } 376 377 if (!multi_ext_cfg->supported) { 378 /* 379 * Error out if the user is trying to enable an 380 * extension that KVM doesn't support. Ignore 381 * option otherwise. 382 */ 383 if (value) { 384 error_setg(errp, "KVM does not support disabling extension %s", 385 multi_ext_cfg->name); 386 } 387 388 return; 389 } 390 391 multi_ext_cfg->user_set = true; 392 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 393 } 394 395 static KVMCPUConfig kvm_cbom_blocksize = { 396 .name = "cbom_blocksize", 397 .offset = CPU_CFG_OFFSET(cbom_blocksize), 398 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 399 }; 400 401 static KVMCPUConfig kvm_cboz_blocksize = { 402 .name = "cboz_blocksize", 403 .offset = CPU_CFG_OFFSET(cboz_blocksize), 404 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 405 }; 406 407 static KVMCPUConfig kvm_v_vlenb = { 408 .name = "vlenb", 409 .offset = CPU_CFG_OFFSET(vlenb), 410 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | 411 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) 412 }; 413 414 static KVMCPUConfig kvm_sbi_dbcn = { 415 .name = "sbi_dbcn", 416 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | 417 KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN 418 }; 419 420 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 421 { 422 CPURISCVState *env = &cpu->env; 423 uint64_t id, reg; 424 int i, ret; 425 426 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 427 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 428 429 if (!multi_ext_cfg->user_set) { 430 continue; 431 } 432 433 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 434 multi_ext_cfg->kvm_reg_id); 435 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 436 ret = kvm_set_one_reg(cs, id, ®); 437 if (ret != 0) { 438 if (!reg && ret == -EINVAL) { 439 warn_report("KVM cannot disable extension %s", 440 multi_ext_cfg->name); 441 } else { 442 error_report("Unable to enable extension %s in KVM, error %d", 443 multi_ext_cfg->name, ret); 444 exit(EXIT_FAILURE); 445 } 446 } 447 } 448 } 449 450 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 451 const char *name, 452 void *opaque, Error **errp) 453 { 454 bool value = false; 455 456 visit_type_bool(v, name, &value, errp); 457 } 458 459 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 460 const char *name, 461 void *opaque, Error **errp) 462 { 463 const char *propname = opaque; 464 bool value; 465 466 if (!visit_type_bool(v, name, &value, errp)) { 467 return; 468 } 469 470 if (value) { 471 error_setg(errp, "'%s' is not available with KVM", 472 propname); 473 } 474 } 475 476 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 477 { 478 /* Check if KVM created the property already */ 479 if (object_property_find(obj, prop_name)) { 480 return; 481 } 482 483 /* 484 * Set the default to disabled for every extension 485 * unknown to KVM and error out if the user attempts 486 * to enable any of them. 487 */ 488 object_property_add(obj, prop_name, "bool", 489 cpu_get_cfg_unavailable, 490 cpu_set_cfg_unavailable, 491 NULL, (void *)prop_name); 492 } 493 494 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 495 const RISCVCPUMultiExtConfig *array) 496 { 497 const RISCVCPUMultiExtConfig *prop; 498 499 g_assert(array); 500 501 for (prop = array; prop && prop->name; prop++) { 502 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 503 } 504 } 505 506 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 507 { 508 int i; 509 510 riscv_add_satp_mode_properties(cpu_obj); 511 512 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 513 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 514 int bit = misa_cfg->offset; 515 516 misa_cfg->name = riscv_get_misa_ext_name(bit); 517 misa_cfg->description = riscv_get_misa_ext_description(bit); 518 519 object_property_add(cpu_obj, misa_cfg->name, "bool", 520 kvm_cpu_get_misa_ext_cfg, 521 kvm_cpu_set_misa_ext_cfg, 522 NULL, misa_cfg); 523 object_property_set_description(cpu_obj, misa_cfg->name, 524 misa_cfg->description); 525 } 526 527 for (i = 0; misa_bits[i] != 0; i++) { 528 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 529 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 530 } 531 532 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 533 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 534 535 object_property_add(cpu_obj, multi_cfg->name, "bool", 536 kvm_cpu_get_multi_ext_cfg, 537 kvm_cpu_set_multi_ext_cfg, 538 NULL, multi_cfg); 539 } 540 541 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 542 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 543 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 544 545 /* We don't have the needed KVM support for profiles */ 546 for (i = 0; riscv_profiles[i] != NULL; i++) { 547 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 548 } 549 } 550 551 static int kvm_riscv_get_regs_core(CPUState *cs) 552 { 553 int ret = 0; 554 int i; 555 target_ulong reg; 556 CPURISCVState *env = &RISCV_CPU(cs)->env; 557 558 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 559 if (ret) { 560 return ret; 561 } 562 env->pc = reg; 563 564 for (i = 1; i < 32; i++) { 565 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 566 ret = kvm_get_one_reg(cs, id, ®); 567 if (ret) { 568 return ret; 569 } 570 env->gpr[i] = reg; 571 } 572 573 return ret; 574 } 575 576 static int kvm_riscv_put_regs_core(CPUState *cs) 577 { 578 int ret = 0; 579 int i; 580 target_ulong reg; 581 CPURISCVState *env = &RISCV_CPU(cs)->env; 582 583 reg = env->pc; 584 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 585 if (ret) { 586 return ret; 587 } 588 589 for (i = 1; i < 32; i++) { 590 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 591 reg = env->gpr[i]; 592 ret = kvm_set_one_reg(cs, id, ®); 593 if (ret) { 594 return ret; 595 } 596 } 597 598 return ret; 599 } 600 601 static int kvm_riscv_get_regs_csr(CPUState *cs) 602 { 603 CPURISCVState *env = &RISCV_CPU(cs)->env; 604 605 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 606 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 607 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 608 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 609 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 610 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 611 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 612 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 613 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 614 615 return 0; 616 } 617 618 static int kvm_riscv_put_regs_csr(CPUState *cs) 619 { 620 CPURISCVState *env = &RISCV_CPU(cs)->env; 621 622 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 623 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 624 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 625 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 626 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 627 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 628 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 629 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 630 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 631 632 return 0; 633 } 634 635 static int kvm_riscv_get_regs_fp(CPUState *cs) 636 { 637 int ret = 0; 638 int i; 639 CPURISCVState *env = &RISCV_CPU(cs)->env; 640 641 if (riscv_has_ext(env, RVD)) { 642 uint64_t reg; 643 for (i = 0; i < 32; i++) { 644 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 645 if (ret) { 646 return ret; 647 } 648 env->fpr[i] = reg; 649 } 650 return ret; 651 } 652 653 if (riscv_has_ext(env, RVF)) { 654 uint32_t reg; 655 for (i = 0; i < 32; i++) { 656 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 657 if (ret) { 658 return ret; 659 } 660 env->fpr[i] = reg; 661 } 662 return ret; 663 } 664 665 return ret; 666 } 667 668 static int kvm_riscv_put_regs_fp(CPUState *cs) 669 { 670 int ret = 0; 671 int i; 672 CPURISCVState *env = &RISCV_CPU(cs)->env; 673 674 if (riscv_has_ext(env, RVD)) { 675 uint64_t reg; 676 for (i = 0; i < 32; i++) { 677 reg = env->fpr[i]; 678 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 679 if (ret) { 680 return ret; 681 } 682 } 683 return ret; 684 } 685 686 if (riscv_has_ext(env, RVF)) { 687 uint32_t reg; 688 for (i = 0; i < 32; i++) { 689 reg = env->fpr[i]; 690 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 691 if (ret) { 692 return ret; 693 } 694 } 695 return ret; 696 } 697 698 return ret; 699 } 700 701 static void kvm_riscv_get_regs_timer(CPUState *cs) 702 { 703 CPURISCVState *env = &RISCV_CPU(cs)->env; 704 705 if (env->kvm_timer_dirty) { 706 return; 707 } 708 709 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 710 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 711 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 712 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 713 714 env->kvm_timer_dirty = true; 715 } 716 717 static void kvm_riscv_put_regs_timer(CPUState *cs) 718 { 719 uint64_t reg; 720 CPURISCVState *env = &RISCV_CPU(cs)->env; 721 722 if (!env->kvm_timer_dirty) { 723 return; 724 } 725 726 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 727 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 728 729 /* 730 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 731 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 732 * doesn't matter that adaping in QEMU now. 733 * TODO If KVM changes, adapt here. 734 */ 735 if (env->kvm_timer_state) { 736 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 737 } 738 739 /* 740 * For now, migration will not work between Hosts with different timer 741 * frequency. Therefore, we should check whether they are the same here 742 * during the migration. 743 */ 744 if (migration_is_running()) { 745 KVM_RISCV_GET_TIMER(cs, frequency, reg); 746 if (reg != env->kvm_timer_frequency) { 747 error_report("Dst Hosts timer frequency != Src Hosts"); 748 } 749 } 750 751 env->kvm_timer_dirty = false; 752 } 753 754 uint64_t kvm_riscv_get_timebase_frequency(CPUState *cs) 755 { 756 uint64_t reg; 757 758 KVM_RISCV_GET_TIMER(cs, frequency, reg); 759 760 return reg; 761 } 762 763 static int kvm_riscv_get_regs_vector(CPUState *cs) 764 { 765 RISCVCPU *cpu = RISCV_CPU(cs); 766 CPURISCVState *env = &cpu->env; 767 target_ulong reg; 768 uint64_t vreg_id; 769 int vreg_idx, ret = 0; 770 771 if (!riscv_has_ext(env, RVV)) { 772 return 0; 773 } 774 775 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 776 if (ret) { 777 return ret; 778 } 779 env->vstart = reg; 780 781 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 782 if (ret) { 783 return ret; 784 } 785 env->vl = reg; 786 787 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 788 if (ret) { 789 return ret; 790 } 791 env->vtype = reg; 792 793 if (kvm_v_vlenb.supported) { 794 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 795 if (ret) { 796 return ret; 797 } 798 cpu->cfg.vlenb = reg; 799 800 for (int i = 0; i < 32; i++) { 801 /* 802 * vreg[] is statically allocated using RV_VLEN_MAX. 803 * Use it instead of vlenb to calculate vreg_idx for 804 * simplicity. 805 */ 806 vreg_idx = i * RV_VLEN_MAX / 64; 807 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 808 809 ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 810 if (ret) { 811 return ret; 812 } 813 } 814 } 815 816 return 0; 817 } 818 819 static int kvm_riscv_put_regs_vector(CPUState *cs) 820 { 821 RISCVCPU *cpu = RISCV_CPU(cs); 822 CPURISCVState *env = &cpu->env; 823 target_ulong reg; 824 uint64_t vreg_id; 825 int vreg_idx, ret = 0; 826 827 if (!riscv_has_ext(env, RVV)) { 828 return 0; 829 } 830 831 reg = env->vstart; 832 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 833 if (ret) { 834 return ret; 835 } 836 837 reg = env->vl; 838 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 839 if (ret) { 840 return ret; 841 } 842 843 reg = env->vtype; 844 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 845 if (ret) { 846 return ret; 847 } 848 849 if (kvm_v_vlenb.supported) { 850 reg = cpu->cfg.vlenb; 851 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 852 853 for (int i = 0; i < 32; i++) { 854 /* 855 * vreg[] is statically allocated using RV_VLEN_MAX. 856 * Use it instead of vlenb to calculate vreg_idx for 857 * simplicity. 858 */ 859 vreg_idx = i * RV_VLEN_MAX / 64; 860 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 861 862 ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 863 if (ret) { 864 return ret; 865 } 866 } 867 } 868 869 return ret; 870 } 871 872 typedef struct KVMScratchCPU { 873 int kvmfd; 874 int vmfd; 875 int cpufd; 876 } KVMScratchCPU; 877 878 /* 879 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 880 * from target/arm/kvm.c. 881 */ 882 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 883 { 884 int kvmfd = -1, vmfd = -1, cpufd = -1; 885 886 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 887 if (kvmfd < 0) { 888 goto err; 889 } 890 do { 891 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 892 } while (vmfd == -1 && errno == EINTR); 893 if (vmfd < 0) { 894 goto err; 895 } 896 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 897 if (cpufd < 0) { 898 goto err; 899 } 900 901 scratch->kvmfd = kvmfd; 902 scratch->vmfd = vmfd; 903 scratch->cpufd = cpufd; 904 905 return true; 906 907 err: 908 if (cpufd >= 0) { 909 close(cpufd); 910 } 911 if (vmfd >= 0) { 912 close(vmfd); 913 } 914 if (kvmfd >= 0) { 915 close(kvmfd); 916 } 917 918 return false; 919 } 920 921 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 922 { 923 close(scratch->cpufd); 924 close(scratch->vmfd); 925 close(scratch->kvmfd); 926 } 927 928 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 929 { 930 CPURISCVState *env = &cpu->env; 931 struct kvm_one_reg reg; 932 int ret; 933 934 reg.id = RISCV_CONFIG_REG(env, mvendorid); 935 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 936 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 937 if (ret != 0) { 938 error_report("Unable to retrieve mvendorid from host, error %d", ret); 939 } 940 941 reg.id = RISCV_CONFIG_REG(env, marchid); 942 reg.addr = (uint64_t)&cpu->cfg.marchid; 943 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 944 if (ret != 0) { 945 error_report("Unable to retrieve marchid from host, error %d", ret); 946 } 947 948 reg.id = RISCV_CONFIG_REG(env, mimpid); 949 reg.addr = (uint64_t)&cpu->cfg.mimpid; 950 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 951 if (ret != 0) { 952 error_report("Unable to retrieve mimpid from host, error %d", ret); 953 } 954 } 955 956 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 957 KVMScratchCPU *kvmcpu) 958 { 959 CPURISCVState *env = &cpu->env; 960 struct kvm_one_reg reg; 961 int ret; 962 963 reg.id = RISCV_CONFIG_REG(env, isa); 964 reg.addr = (uint64_t)&env->misa_ext_mask; 965 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 966 967 if (ret) { 968 error_report("Unable to fetch ISA register from KVM, " 969 "error %d", ret); 970 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 971 exit(EXIT_FAILURE); 972 } 973 974 env->misa_ext = env->misa_ext_mask; 975 } 976 977 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 978 KVMCPUConfig *cbomz_cfg) 979 { 980 CPURISCVState *env = &cpu->env; 981 struct kvm_one_reg reg; 982 int ret; 983 984 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 985 cbomz_cfg->kvm_reg_id); 986 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 987 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 988 if (ret != 0) { 989 error_report("Unable to read KVM reg %s, error %d", 990 cbomz_cfg->name, ret); 991 exit(EXIT_FAILURE); 992 } 993 } 994 995 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 996 KVMScratchCPU *kvmcpu) 997 { 998 CPURISCVState *env = &cpu->env; 999 uint64_t val; 1000 int i, ret; 1001 1002 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1003 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1004 struct kvm_one_reg reg; 1005 1006 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 1007 multi_ext_cfg->kvm_reg_id); 1008 reg.addr = (uint64_t)&val; 1009 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1010 if (ret != 0) { 1011 if (errno == EINVAL) { 1012 /* Silently default to 'false' if KVM does not support it. */ 1013 multi_ext_cfg->supported = false; 1014 val = false; 1015 } else { 1016 error_report("Unable to read ISA_EXT KVM register %s: %s", 1017 multi_ext_cfg->name, strerror(errno)); 1018 exit(EXIT_FAILURE); 1019 } 1020 } else { 1021 multi_ext_cfg->supported = true; 1022 } 1023 1024 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1025 } 1026 1027 if (cpu->cfg.ext_zicbom) { 1028 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1029 } 1030 1031 if (cpu->cfg.ext_zicboz) { 1032 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1033 } 1034 } 1035 1036 static int uint64_cmp(const void *a, const void *b) 1037 { 1038 uint64_t val1 = *(const uint64_t *)a; 1039 uint64_t val2 = *(const uint64_t *)b; 1040 1041 if (val1 < val2) { 1042 return -1; 1043 } 1044 1045 if (val1 > val2) { 1046 return 1; 1047 } 1048 1049 return 0; 1050 } 1051 1052 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, 1053 KVMScratchCPU *kvmcpu, 1054 struct kvm_reg_list *reglist) 1055 { 1056 struct kvm_reg_list *reg_search; 1057 1058 reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, 1059 sizeof(uint64_t), uint64_cmp); 1060 1061 if (reg_search) { 1062 kvm_sbi_dbcn.supported = true; 1063 } 1064 } 1065 1066 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1067 struct kvm_reg_list *reglist) 1068 { 1069 struct kvm_one_reg reg; 1070 struct kvm_reg_list *reg_search; 1071 uint64_t val; 1072 int ret; 1073 1074 reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, 1075 sizeof(uint64_t), uint64_cmp); 1076 1077 if (reg_search) { 1078 reg.id = kvm_v_vlenb.kvm_reg_id; 1079 reg.addr = (uint64_t)&val; 1080 1081 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1082 if (ret != 0) { 1083 error_report("Unable to read vlenb register, error code: %d", 1084 errno); 1085 exit(EXIT_FAILURE); 1086 } 1087 1088 kvm_v_vlenb.supported = true; 1089 cpu->cfg.vlenb = val; 1090 } 1091 } 1092 1093 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 1094 { 1095 KVMCPUConfig *multi_ext_cfg; 1096 struct kvm_one_reg reg; 1097 struct kvm_reg_list rl_struct; 1098 struct kvm_reg_list *reglist; 1099 uint64_t val, reg_id, *reg_search; 1100 int i, ret; 1101 1102 rl_struct.n = 0; 1103 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 1104 1105 /* 1106 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 1107 * (EINVAL). Use read_legacy() in this case. 1108 */ 1109 if (errno == EINVAL) { 1110 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 1111 } else if (errno != E2BIG) { 1112 /* 1113 * E2BIG is an expected error message for the API since we 1114 * don't know the number of registers. The right amount will 1115 * be written in rl_struct.n. 1116 * 1117 * Error out if we get any other errno. 1118 */ 1119 error_report("Error when accessing get-reg-list: %s", 1120 strerror(errno)); 1121 exit(EXIT_FAILURE); 1122 } 1123 1124 reglist = g_malloc(sizeof(struct kvm_reg_list) + 1125 rl_struct.n * sizeof(uint64_t)); 1126 reglist->n = rl_struct.n; 1127 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 1128 if (ret) { 1129 error_report("Error when reading KVM_GET_REG_LIST: %s", 1130 strerror(errno)); 1131 exit(EXIT_FAILURE); 1132 } 1133 1134 /* sort reglist to use bsearch() */ 1135 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 1136 1137 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1138 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1139 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 1140 multi_ext_cfg->kvm_reg_id); 1141 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1142 sizeof(uint64_t), uint64_cmp); 1143 if (!reg_search) { 1144 continue; 1145 } 1146 1147 reg.id = reg_id; 1148 reg.addr = (uint64_t)&val; 1149 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1150 if (ret != 0) { 1151 error_report("Unable to read ISA_EXT KVM register %s: %s", 1152 multi_ext_cfg->name, strerror(errno)); 1153 exit(EXIT_FAILURE); 1154 } 1155 1156 multi_ext_cfg->supported = true; 1157 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1158 } 1159 1160 if (cpu->cfg.ext_zicbom) { 1161 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1162 } 1163 1164 if (cpu->cfg.ext_zicboz) { 1165 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1166 } 1167 1168 if (riscv_has_ext(&cpu->env, RVV)) { 1169 kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); 1170 } 1171 1172 kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist); 1173 } 1174 1175 static void riscv_init_kvm_registers(Object *cpu_obj) 1176 { 1177 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1178 KVMScratchCPU kvmcpu; 1179 1180 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1181 return; 1182 } 1183 1184 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1185 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1186 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1187 1188 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1189 } 1190 1191 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1192 KVM_CAP_LAST_INFO 1193 }; 1194 1195 int kvm_arch_get_registers(CPUState *cs, Error **errp) 1196 { 1197 int ret = 0; 1198 1199 ret = kvm_riscv_get_regs_core(cs); 1200 if (ret) { 1201 return ret; 1202 } 1203 1204 ret = kvm_riscv_get_regs_csr(cs); 1205 if (ret) { 1206 return ret; 1207 } 1208 1209 ret = kvm_riscv_get_regs_fp(cs); 1210 if (ret) { 1211 return ret; 1212 } 1213 1214 ret = kvm_riscv_get_regs_vector(cs); 1215 if (ret) { 1216 return ret; 1217 } 1218 1219 return ret; 1220 } 1221 1222 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1223 { 1224 if (cap_has_mp_state) { 1225 struct kvm_mp_state mp_state = { 1226 .mp_state = state 1227 }; 1228 1229 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1230 if (ret) { 1231 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1232 __func__, ret, strerror(-ret)); 1233 return -1; 1234 } 1235 } 1236 1237 return 0; 1238 } 1239 1240 int kvm_arch_put_registers(CPUState *cs, int level, Error **errp) 1241 { 1242 int ret = 0; 1243 1244 ret = kvm_riscv_put_regs_core(cs); 1245 if (ret) { 1246 return ret; 1247 } 1248 1249 ret = kvm_riscv_put_regs_csr(cs); 1250 if (ret) { 1251 return ret; 1252 } 1253 1254 ret = kvm_riscv_put_regs_fp(cs); 1255 if (ret) { 1256 return ret; 1257 } 1258 1259 ret = kvm_riscv_put_regs_vector(cs); 1260 if (ret) { 1261 return ret; 1262 } 1263 1264 if (KVM_PUT_RESET_STATE == level) { 1265 RISCVCPU *cpu = RISCV_CPU(cs); 1266 if (cs->cpu_index == 0) { 1267 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1268 } else { 1269 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1270 } 1271 if (ret) { 1272 return ret; 1273 } 1274 } 1275 1276 return ret; 1277 } 1278 1279 int kvm_arch_release_virq_post(int virq) 1280 { 1281 return 0; 1282 } 1283 1284 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1285 uint64_t address, uint32_t data, PCIDevice *dev) 1286 { 1287 return 0; 1288 } 1289 1290 int kvm_arch_destroy_vcpu(CPUState *cs) 1291 { 1292 return 0; 1293 } 1294 1295 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1296 { 1297 return cpu->cpu_index; 1298 } 1299 1300 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1301 RunState state) 1302 { 1303 CPUState *cs = opaque; 1304 1305 if (running) { 1306 kvm_riscv_put_regs_timer(cs); 1307 } else { 1308 kvm_riscv_get_regs_timer(cs); 1309 } 1310 } 1311 1312 void kvm_arch_init_irq_routing(KVMState *s) 1313 { 1314 } 1315 1316 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1317 { 1318 CPURISCVState *env = &cpu->env; 1319 target_ulong reg; 1320 uint64_t id; 1321 int ret; 1322 1323 id = RISCV_CONFIG_REG(env, mvendorid); 1324 /* 1325 * cfg.mvendorid is an uint32 but a target_ulong will 1326 * be written. Assign it to a target_ulong var to avoid 1327 * writing pieces of other cpu->cfg fields in the reg. 1328 */ 1329 reg = cpu->cfg.mvendorid; 1330 ret = kvm_set_one_reg(cs, id, ®); 1331 if (ret != 0) { 1332 return ret; 1333 } 1334 1335 id = RISCV_CONFIG_REG(env, marchid); 1336 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1337 if (ret != 0) { 1338 return ret; 1339 } 1340 1341 id = RISCV_CONFIG_REG(env, mimpid); 1342 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1343 1344 return ret; 1345 } 1346 1347 static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) 1348 { 1349 target_ulong reg = 1; 1350 1351 if (!kvm_sbi_dbcn.supported) { 1352 return 0; 1353 } 1354 1355 return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); 1356 } 1357 1358 int kvm_arch_init_vcpu(CPUState *cs) 1359 { 1360 int ret = 0; 1361 RISCVCPU *cpu = RISCV_CPU(cs); 1362 1363 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1364 1365 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1366 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1367 if (ret != 0) { 1368 return ret; 1369 } 1370 } 1371 1372 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1373 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1374 1375 ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); 1376 1377 return ret; 1378 } 1379 1380 int kvm_arch_msi_data_to_gsi(uint32_t data) 1381 { 1382 abort(); 1383 } 1384 1385 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1386 int vector, PCIDevice *dev) 1387 { 1388 return 0; 1389 } 1390 1391 int kvm_arch_get_default_type(MachineState *ms) 1392 { 1393 return 0; 1394 } 1395 1396 int kvm_arch_init(MachineState *ms, KVMState *s) 1397 { 1398 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1399 return 0; 1400 } 1401 1402 int kvm_arch_irqchip_create(KVMState *s) 1403 { 1404 if (kvm_kernel_irqchip_split()) { 1405 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1406 exit(1); 1407 } 1408 1409 /* 1410 * We can create the VAIA using the newer device control API. 1411 */ 1412 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1413 } 1414 1415 int kvm_arch_process_async_events(CPUState *cs) 1416 { 1417 return 0; 1418 } 1419 1420 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1421 { 1422 } 1423 1424 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1425 { 1426 return MEMTXATTRS_UNSPECIFIED; 1427 } 1428 1429 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1430 { 1431 return true; 1432 } 1433 1434 static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) 1435 { 1436 g_autofree uint8_t *buf = NULL; 1437 RISCVCPU *cpu = RISCV_CPU(cs); 1438 target_ulong num_bytes; 1439 uint64_t addr; 1440 unsigned char ch; 1441 int ret; 1442 1443 switch (run->riscv_sbi.function_id) { 1444 case SBI_EXT_DBCN_CONSOLE_READ: 1445 case SBI_EXT_DBCN_CONSOLE_WRITE: 1446 num_bytes = run->riscv_sbi.args[0]; 1447 1448 if (num_bytes == 0) { 1449 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1450 run->riscv_sbi.ret[1] = 0; 1451 break; 1452 } 1453 1454 addr = run->riscv_sbi.args[1]; 1455 1456 /* 1457 * Handle the case where a 32 bit CPU is running in a 1458 * 64 bit addressing env. 1459 */ 1460 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { 1461 addr |= (uint64_t)run->riscv_sbi.args[2] << 32; 1462 } 1463 1464 buf = g_malloc0(num_bytes); 1465 1466 if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { 1467 ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); 1468 if (ret < 0) { 1469 error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " 1470 "reading chardev"); 1471 exit(1); 1472 } 1473 1474 cpu_physical_memory_write(addr, buf, ret); 1475 } else { 1476 cpu_physical_memory_read(addr, buf, num_bytes); 1477 1478 ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); 1479 if (ret < 0) { 1480 error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " 1481 "writing chardev"); 1482 exit(1); 1483 } 1484 } 1485 1486 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1487 run->riscv_sbi.ret[1] = ret; 1488 break; 1489 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 1490 ch = run->riscv_sbi.args[0]; 1491 ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1492 1493 if (ret < 0) { 1494 error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " 1495 "writing chardev"); 1496 exit(1); 1497 } 1498 1499 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1500 run->riscv_sbi.ret[1] = 0; 1501 break; 1502 default: 1503 run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; 1504 } 1505 } 1506 1507 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1508 { 1509 int ret = 0; 1510 unsigned char ch; 1511 switch (run->riscv_sbi.extension_id) { 1512 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1513 ch = run->riscv_sbi.args[0]; 1514 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1515 break; 1516 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1517 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1518 if (ret == sizeof(ch)) { 1519 run->riscv_sbi.ret[0] = ch; 1520 } else { 1521 run->riscv_sbi.ret[0] = -1; 1522 } 1523 ret = 0; 1524 break; 1525 case SBI_EXT_DBCN: 1526 kvm_riscv_handle_sbi_dbcn(cs, run); 1527 break; 1528 default: 1529 qemu_log_mask(LOG_UNIMP, 1530 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1531 __func__, run->riscv_sbi.extension_id); 1532 ret = -1; 1533 break; 1534 } 1535 return ret; 1536 } 1537 1538 static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) 1539 { 1540 target_ulong csr_num = run->riscv_csr.csr_num; 1541 target_ulong new_value = run->riscv_csr.new_value; 1542 target_ulong write_mask = run->riscv_csr.write_mask; 1543 int ret = 0; 1544 1545 switch (csr_num) { 1546 case CSR_SEED: 1547 run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); 1548 break; 1549 default: 1550 qemu_log_mask(LOG_UNIMP, 1551 "%s: un-handled CSR EXIT for CSR %lx\n", 1552 __func__, csr_num); 1553 ret = -1; 1554 break; 1555 } 1556 1557 return ret; 1558 } 1559 1560 static bool kvm_riscv_handle_debug(CPUState *cs) 1561 { 1562 RISCVCPU *cpu = RISCV_CPU(cs); 1563 CPURISCVState *env = &cpu->env; 1564 1565 /* Ensure PC is synchronised */ 1566 kvm_cpu_synchronize_state(cs); 1567 1568 if (kvm_find_sw_breakpoint(cs, env->pc)) { 1569 return true; 1570 } 1571 1572 return false; 1573 } 1574 1575 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1576 { 1577 int ret = 0; 1578 switch (run->exit_reason) { 1579 case KVM_EXIT_RISCV_SBI: 1580 ret = kvm_riscv_handle_sbi(cs, run); 1581 break; 1582 case KVM_EXIT_RISCV_CSR: 1583 ret = kvm_riscv_handle_csr(cs, run); 1584 break; 1585 case KVM_EXIT_DEBUG: 1586 if (kvm_riscv_handle_debug(cs)) { 1587 ret = EXCP_DEBUG; 1588 } 1589 break; 1590 default: 1591 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1592 __func__, run->exit_reason); 1593 ret = -1; 1594 break; 1595 } 1596 return ret; 1597 } 1598 1599 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1600 { 1601 CPURISCVState *env = &cpu->env; 1602 int i; 1603 1604 if (!kvm_enabled()) { 1605 return; 1606 } 1607 for (i = 0; i < 32; i++) { 1608 env->gpr[i] = 0; 1609 } 1610 env->pc = cpu->env.kernel_addr; 1611 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1612 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1613 env->satp = 0; 1614 env->mie = 0; 1615 env->stvec = 0; 1616 env->sscratch = 0; 1617 env->sepc = 0; 1618 env->scause = 0; 1619 env->stval = 0; 1620 env->mip = 0; 1621 } 1622 1623 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1624 { 1625 int ret; 1626 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1627 1628 if (irq != IRQ_S_EXT) { 1629 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1630 abort(); 1631 } 1632 1633 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1634 if (ret < 0) { 1635 perror("Set irq failed"); 1636 abort(); 1637 } 1638 } 1639 1640 static int aia_mode; 1641 1642 static const char *kvm_aia_mode_str(uint64_t mode) 1643 { 1644 switch (mode) { 1645 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1646 return "emul"; 1647 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1648 return "hwaccel"; 1649 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1650 default: 1651 return "auto"; 1652 }; 1653 } 1654 1655 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1656 { 1657 return g_strdup(kvm_aia_mode_str(aia_mode)); 1658 } 1659 1660 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1661 { 1662 if (!strcmp(val, "emul")) { 1663 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1664 } else if (!strcmp(val, "hwaccel")) { 1665 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1666 } else if (!strcmp(val, "auto")) { 1667 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1668 } else { 1669 error_setg(errp, "Invalid KVM AIA mode"); 1670 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1671 } 1672 } 1673 1674 void kvm_arch_accel_class_init(ObjectClass *oc) 1675 { 1676 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1677 riscv_set_kvm_aia); 1678 object_class_property_set_description(oc, "riscv-aia", 1679 "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " 1680 "Changing KVM AIA modes relies on host support. Defaults to 'auto' " 1681 "if the host supports it"); 1682 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1683 "auto"); 1684 } 1685 1686 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1687 uint64_t aia_irq_num, uint64_t aia_msi_num, 1688 uint64_t aplic_base, uint64_t imsic_base, 1689 uint64_t guest_num) 1690 { 1691 int ret, i; 1692 int aia_fd = -1; 1693 uint64_t default_aia_mode; 1694 uint64_t socket_count = riscv_socket_count(machine); 1695 uint64_t max_hart_per_socket = 0; 1696 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1697 uint64_t socket_bits, hart_bits, guest_bits; 1698 uint64_t max_group_id; 1699 1700 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1701 1702 if (aia_fd < 0) { 1703 error_report("Unable to create in-kernel irqchip"); 1704 exit(1); 1705 } 1706 1707 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1708 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1709 &default_aia_mode, false, NULL); 1710 if (ret < 0) { 1711 error_report("KVM AIA: failed to get current KVM AIA mode"); 1712 exit(1); 1713 } 1714 1715 if (default_aia_mode != aia_mode) { 1716 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1717 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1718 &aia_mode, true, NULL); 1719 if (ret < 0) { 1720 warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " 1721 "default host mode '%s'", 1722 kvm_aia_mode_str(aia_mode), 1723 kvm_aia_mode_str(default_aia_mode)); 1724 1725 /* failed to change AIA mode, use default */ 1726 aia_mode = default_aia_mode; 1727 } 1728 } 1729 1730 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1731 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1732 &aia_irq_num, true, NULL); 1733 if (ret < 0) { 1734 error_report("KVM AIA: failed to set number of input irq lines"); 1735 exit(1); 1736 } 1737 1738 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1739 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1740 &aia_msi_num, true, NULL); 1741 if (ret < 0) { 1742 error_report("KVM AIA: failed to set number of msi"); 1743 exit(1); 1744 } 1745 1746 1747 if (socket_count > 1) { 1748 max_group_id = socket_count - 1; 1749 socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1; 1750 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1751 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1752 &socket_bits, true, NULL); 1753 if (ret < 0) { 1754 error_report("KVM AIA: failed to set group_bits"); 1755 exit(1); 1756 } 1757 1758 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1759 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1760 &group_shift, true, NULL); 1761 if (ret < 0) { 1762 error_report("KVM AIA: failed to set group_shift"); 1763 exit(1); 1764 } 1765 } 1766 1767 guest_bits = guest_num == 0 ? 0 : 1768 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1769 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1770 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1771 &guest_bits, true, NULL); 1772 if (ret < 0) { 1773 error_report("KVM AIA: failed to set guest_bits"); 1774 exit(1); 1775 } 1776 1777 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1778 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1779 &aplic_base, true, NULL); 1780 if (ret < 0) { 1781 error_report("KVM AIA: failed to set the base address of APLIC"); 1782 exit(1); 1783 } 1784 1785 for (socket = 0; socket < socket_count; socket++) { 1786 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1787 hart_count = riscv_socket_hart_count(machine, socket); 1788 base_hart = riscv_socket_first_hartid(machine, socket); 1789 1790 if (max_hart_per_socket < hart_count) { 1791 max_hart_per_socket = hart_count; 1792 } 1793 1794 for (i = 0; i < hart_count; i++) { 1795 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1796 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1797 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1798 &imsic_addr, true, NULL); 1799 if (ret < 0) { 1800 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1801 exit(1); 1802 } 1803 } 1804 } 1805 1806 1807 if (max_hart_per_socket > 1) { 1808 max_hart_per_socket--; 1809 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1810 } else { 1811 hart_bits = 0; 1812 } 1813 1814 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1815 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1816 &hart_bits, true, NULL); 1817 if (ret < 0) { 1818 error_report("KVM AIA: failed to set hart_bits"); 1819 exit(1); 1820 } 1821 1822 if (kvm_has_gsi_routing()) { 1823 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1824 /* KVM AIA only has one APLIC instance */ 1825 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1826 } 1827 kvm_gsi_routing_allowed = true; 1828 kvm_irqchip_commit_routes(kvm_state); 1829 } 1830 1831 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1832 KVM_DEV_RISCV_AIA_CTRL_INIT, 1833 NULL, true, NULL); 1834 if (ret < 0) { 1835 error_report("KVM AIA: initialized fail"); 1836 exit(1); 1837 } 1838 1839 kvm_msi_via_irqfd_allowed = true; 1840 } 1841 1842 static void kvm_cpu_instance_init(CPUState *cs) 1843 { 1844 Object *obj = OBJECT(RISCV_CPU(cs)); 1845 1846 riscv_init_kvm_registers(obj); 1847 1848 kvm_riscv_add_cpu_user_properties(obj); 1849 } 1850 1851 /* 1852 * We'll get here via the following path: 1853 * 1854 * riscv_cpu_realize() 1855 * -> cpu_exec_realizefn() 1856 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1857 */ 1858 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1859 { 1860 RISCVCPU *cpu = RISCV_CPU(cs); 1861 int ret; 1862 1863 if (riscv_has_ext(&cpu->env, RVV)) { 1864 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1865 if (ret) { 1866 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1867 strerrorname_np(errno)); 1868 return false; 1869 } 1870 } 1871 1872 return true; 1873 } 1874 1875 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1876 { 1877 CPURISCVState *env = &cpu->env; 1878 KVMScratchCPU kvmcpu; 1879 struct kvm_one_reg reg; 1880 uint64_t val; 1881 int ret; 1882 1883 /* short-circuit without spinning the scratch CPU */ 1884 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz && 1885 !riscv_has_ext(env, RVV)) { 1886 return; 1887 } 1888 1889 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1890 error_setg(errp, "Unable to create scratch KVM cpu"); 1891 return; 1892 } 1893 1894 if (cpu->cfg.ext_zicbom && 1895 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 1896 1897 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1898 kvm_cbom_blocksize.kvm_reg_id); 1899 reg.addr = (uint64_t)&val; 1900 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1901 if (ret != 0) { 1902 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 1903 return; 1904 } 1905 1906 if (cpu->cfg.cbom_blocksize != val) { 1907 error_setg(errp, "Unable to set cbom_blocksize to a different " 1908 "value than the host (%lu)", val); 1909 return; 1910 } 1911 } 1912 1913 if (cpu->cfg.ext_zicboz && 1914 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 1915 1916 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1917 kvm_cboz_blocksize.kvm_reg_id); 1918 reg.addr = (uint64_t)&val; 1919 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1920 if (ret != 0) { 1921 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 1922 return; 1923 } 1924 1925 if (cpu->cfg.cboz_blocksize != val) { 1926 error_setg(errp, "Unable to set cboz_blocksize to a different " 1927 "value than the host (%lu)", val); 1928 return; 1929 } 1930 } 1931 1932 /* Users are setting vlen, not vlenb */ 1933 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { 1934 if (!kvm_v_vlenb.supported) { 1935 error_setg(errp, "Unable to set 'vlenb': register not supported"); 1936 return; 1937 } 1938 1939 reg.id = kvm_v_vlenb.kvm_reg_id; 1940 reg.addr = (uint64_t)&val; 1941 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1942 if (ret != 0) { 1943 error_setg(errp, "Unable to read vlenb register, error %d", errno); 1944 return; 1945 } 1946 1947 if (cpu->cfg.vlenb != val) { 1948 error_setg(errp, "Unable to set 'vlen' to a different " 1949 "value than the host (%lu)", val * 8); 1950 return; 1951 } 1952 } 1953 1954 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1955 } 1956 1957 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1958 { 1959 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1960 1961 acc->cpu_instance_init = kvm_cpu_instance_init; 1962 acc->cpu_target_realize = kvm_cpu_realize; 1963 } 1964 1965 static const TypeInfo kvm_cpu_accel_type_info = { 1966 .name = ACCEL_CPU_NAME("kvm"), 1967 1968 .parent = TYPE_ACCEL_CPU, 1969 .class_init = kvm_cpu_accel_class_init, 1970 .abstract = true, 1971 }; 1972 static void kvm_cpu_accel_register_types(void) 1973 { 1974 type_register_static(&kvm_cpu_accel_type_info); 1975 } 1976 type_init(kvm_cpu_accel_register_types); 1977 1978 static void riscv_host_cpu_class_init(ObjectClass *c, void *data) 1979 { 1980 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1981 1982 #if defined(TARGET_RISCV32) 1983 mcc->misa_mxl_max = MXL_RV32; 1984 #elif defined(TARGET_RISCV64) 1985 mcc->misa_mxl_max = MXL_RV64; 1986 #endif 1987 } 1988 1989 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1990 { 1991 .name = TYPE_RISCV_CPU_HOST, 1992 .parent = TYPE_RISCV_CPU, 1993 .class_init = riscv_host_cpu_class_init, 1994 } 1995 }; 1996 1997 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1998 1999 static const uint32_t ebreak_insn = 0x00100073; 2000 static const uint16_t c_ebreak_insn = 0x9002; 2001 2002 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2003 { 2004 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) { 2005 return -EINVAL; 2006 } 2007 2008 if ((bp->saved_insn & 0x3) == 0x3) { 2009 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) 2010 || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1)) { 2011 return -EINVAL; 2012 } 2013 } else { 2014 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) { 2015 return -EINVAL; 2016 } 2017 } 2018 2019 return 0; 2020 } 2021 2022 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 2023 { 2024 uint32_t ebreak; 2025 uint16_t c_ebreak; 2026 2027 if ((bp->saved_insn & 0x3) == 0x3) { 2028 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) || 2029 ebreak != ebreak_insn || 2030 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2031 return -EINVAL; 2032 } 2033 } else { 2034 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) || 2035 c_ebreak != c_ebreak_insn || 2036 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1)) { 2037 return -EINVAL; 2038 } 2039 } 2040 2041 return 0; 2042 } 2043 2044 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2045 { 2046 /* TODO; To be implemented later. */ 2047 return -EINVAL; 2048 } 2049 2050 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2051 { 2052 /* TODO; To be implemented later. */ 2053 return -EINVAL; 2054 } 2055 2056 void kvm_arch_remove_all_hw_breakpoints(void) 2057 { 2058 /* TODO; To be implemented later. */ 2059 } 2060 2061 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 2062 { 2063 if (kvm_sw_breakpoints_active(cs)) { 2064 dbg->control |= KVM_GUESTDBG_ENABLE; 2065 } 2066 } 2067