1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 #include <sys/prctl.h> 22 23 #include <linux/kvm.h> 24 25 #include "qemu/timer.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/main-loop.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/kvm.h" 32 #include "sysemu/kvm_int.h" 33 #include "cpu.h" 34 #include "trace.h" 35 #include "hw/core/accel-cpu.h" 36 #include "hw/pci/pci.h" 37 #include "exec/memattrs.h" 38 #include "exec/address-spaces.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/intc/riscv_imsic.h" 42 #include "qemu/log.h" 43 #include "hw/loader.h" 44 #include "kvm_riscv.h" 45 #include "sbi_ecall_interface.h" 46 #include "chardev/char-fe.h" 47 #include "migration/misc.h" 48 #include "sysemu/runstate.h" 49 #include "hw/riscv/numa.h" 50 51 #define PR_RISCV_V_SET_CONTROL 69 52 #define PR_RISCV_V_VSTATE_CTRL_ON 2 53 54 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 55 { 56 kvm_set_irq(kvm_state, irq, !!level); 57 } 58 59 static bool cap_has_mp_state; 60 61 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 62 uint64_t idx) 63 { 64 uint64_t id = KVM_REG_RISCV | type | idx; 65 66 switch (riscv_cpu_mxl(env)) { 67 case MXL_RV32: 68 id |= KVM_REG_SIZE_U32; 69 break; 70 case MXL_RV64: 71 id |= KVM_REG_SIZE_U64; 72 break; 73 default: 74 g_assert_not_reached(); 75 } 76 return id; 77 } 78 79 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 80 { 81 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 82 } 83 84 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 85 { 86 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 87 } 88 89 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) 90 { 91 uint64_t size_ctz = __builtin_ctz(size_b); 92 93 return id | (size_ctz << KVM_REG_SIZE_SHIFT); 94 } 95 96 static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, 97 uint64_t idx) 98 { 99 uint64_t id; 100 size_t size_b; 101 102 g_assert(idx < 32); 103 104 id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); 105 size_b = cpu->cfg.vlenb; 106 107 return kvm_encode_reg_size_id(id, size_b); 108 } 109 110 #define RISCV_CORE_REG(env, name) \ 111 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 112 KVM_REG_RISCV_CORE_REG(name)) 113 114 #define RISCV_CSR_REG(env, name) \ 115 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 116 KVM_REG_RISCV_CSR_REG(name)) 117 118 #define RISCV_CONFIG_REG(env, name) \ 119 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 120 KVM_REG_RISCV_CONFIG_REG(name)) 121 122 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 123 KVM_REG_RISCV_TIMER_REG(name)) 124 125 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 126 127 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 128 129 #define RISCV_VECTOR_CSR_REG(env, name) \ 130 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ 131 KVM_REG_RISCV_VECTOR_CSR_REG(name)) 132 133 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 134 do { \ 135 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 136 if (_ret) { \ 137 return _ret; \ 138 } \ 139 } while (0) 140 141 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 142 do { \ 143 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 144 if (_ret) { \ 145 return _ret; \ 146 } \ 147 } while (0) 148 149 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 150 do { \ 151 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 152 if (ret) { \ 153 abort(); \ 154 } \ 155 } while (0) 156 157 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 158 do { \ 159 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 160 if (ret) { \ 161 abort(); \ 162 } \ 163 } while (0) 164 165 typedef struct KVMCPUConfig { 166 const char *name; 167 const char *description; 168 target_ulong offset; 169 uint64_t kvm_reg_id; 170 bool user_set; 171 bool supported; 172 } KVMCPUConfig; 173 174 #define KVM_MISA_CFG(_bit, _reg_id) \ 175 {.offset = _bit, .kvm_reg_id = _reg_id} 176 177 /* KVM ISA extensions */ 178 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 179 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 180 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 181 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 182 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 183 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 184 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 185 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 186 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), 187 }; 188 189 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 190 const char *name, 191 void *opaque, Error **errp) 192 { 193 KVMCPUConfig *misa_ext_cfg = opaque; 194 target_ulong misa_bit = misa_ext_cfg->offset; 195 RISCVCPU *cpu = RISCV_CPU(obj); 196 CPURISCVState *env = &cpu->env; 197 bool value = env->misa_ext_mask & misa_bit; 198 199 visit_type_bool(v, name, &value, errp); 200 } 201 202 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 203 const char *name, 204 void *opaque, Error **errp) 205 { 206 KVMCPUConfig *misa_ext_cfg = opaque; 207 target_ulong misa_bit = misa_ext_cfg->offset; 208 RISCVCPU *cpu = RISCV_CPU(obj); 209 CPURISCVState *env = &cpu->env; 210 bool value, host_bit; 211 212 if (!visit_type_bool(v, name, &value, errp)) { 213 return; 214 } 215 216 host_bit = env->misa_ext_mask & misa_bit; 217 218 if (value == host_bit) { 219 return; 220 } 221 222 if (!value) { 223 misa_ext_cfg->user_set = true; 224 return; 225 } 226 227 /* 228 * Forbid users to enable extensions that aren't 229 * available in the hart. 230 */ 231 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 232 "enabled in the host", misa_ext_cfg->name); 233 } 234 235 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 236 { 237 CPURISCVState *env = &cpu->env; 238 uint64_t id, reg; 239 int i, ret; 240 241 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 242 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 243 target_ulong misa_bit = misa_cfg->offset; 244 245 if (!misa_cfg->user_set) { 246 continue; 247 } 248 249 /* If we're here we're going to disable the MISA bit */ 250 reg = 0; 251 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 252 misa_cfg->kvm_reg_id); 253 ret = kvm_set_one_reg(cs, id, ®); 254 if (ret != 0) { 255 /* 256 * We're not checking for -EINVAL because if the bit is about 257 * to be disabled, it means that it was already enabled by 258 * KVM. We determined that by fetching the 'isa' register 259 * during init() time. Any error at this point is worth 260 * aborting. 261 */ 262 error_report("Unable to set KVM reg %s, error %d", 263 misa_cfg->name, ret); 264 exit(EXIT_FAILURE); 265 } 266 env->misa_ext &= ~misa_bit; 267 } 268 } 269 270 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 271 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 272 .kvm_reg_id = _reg_id} 273 274 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 275 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 276 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 277 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 278 KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), 279 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 280 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 281 KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), 282 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 283 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 284 KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), 285 KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), 286 KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), 287 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 288 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 289 KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), 290 KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), 291 KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), 292 KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), 293 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 294 KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), 295 KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), 296 KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), 297 KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), 298 KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), 299 KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), 300 KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), 301 KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), 302 KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), 303 KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), 304 KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), 305 KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), 306 KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), 307 KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), 308 KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), 309 KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), 310 KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), 311 KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), 312 KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), 313 KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), 314 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 315 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 316 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 317 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 318 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 319 }; 320 321 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 322 { 323 return (void *)&cpu->cfg + kvmcfg->offset; 324 } 325 326 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 327 uint32_t val) 328 { 329 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 330 331 *ext_enabled = val; 332 } 333 334 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 335 KVMCPUConfig *multi_ext) 336 { 337 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 338 339 return *ext_enabled; 340 } 341 342 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 343 const char *name, 344 void *opaque, Error **errp) 345 { 346 KVMCPUConfig *multi_ext_cfg = opaque; 347 RISCVCPU *cpu = RISCV_CPU(obj); 348 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 349 350 visit_type_bool(v, name, &value, errp); 351 } 352 353 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 354 const char *name, 355 void *opaque, Error **errp) 356 { 357 KVMCPUConfig *multi_ext_cfg = opaque; 358 RISCVCPU *cpu = RISCV_CPU(obj); 359 bool value, host_val; 360 361 if (!visit_type_bool(v, name, &value, errp)) { 362 return; 363 } 364 365 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 366 367 /* 368 * Ignore if the user is setting the same value 369 * as the host. 370 */ 371 if (value == host_val) { 372 return; 373 } 374 375 if (!multi_ext_cfg->supported) { 376 /* 377 * Error out if the user is trying to enable an 378 * extension that KVM doesn't support. Ignore 379 * option otherwise. 380 */ 381 if (value) { 382 error_setg(errp, "KVM does not support disabling extension %s", 383 multi_ext_cfg->name); 384 } 385 386 return; 387 } 388 389 multi_ext_cfg->user_set = true; 390 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 391 } 392 393 static KVMCPUConfig kvm_cbom_blocksize = { 394 .name = "cbom_blocksize", 395 .offset = CPU_CFG_OFFSET(cbom_blocksize), 396 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 397 }; 398 399 static KVMCPUConfig kvm_cboz_blocksize = { 400 .name = "cboz_blocksize", 401 .offset = CPU_CFG_OFFSET(cboz_blocksize), 402 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 403 }; 404 405 static KVMCPUConfig kvm_v_vlenb = { 406 .name = "vlenb", 407 .offset = CPU_CFG_OFFSET(vlenb), 408 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | 409 KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) 410 }; 411 412 static KVMCPUConfig kvm_sbi_dbcn = { 413 .name = "sbi_dbcn", 414 .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | 415 KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN 416 }; 417 418 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 419 { 420 CPURISCVState *env = &cpu->env; 421 uint64_t id, reg; 422 int i, ret; 423 424 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 425 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 426 427 if (!multi_ext_cfg->user_set) { 428 continue; 429 } 430 431 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 432 multi_ext_cfg->kvm_reg_id); 433 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 434 ret = kvm_set_one_reg(cs, id, ®); 435 if (ret != 0) { 436 if (!reg && ret == -EINVAL) { 437 warn_report("KVM cannot disable extension %s", 438 multi_ext_cfg->name); 439 } else { 440 error_report("Unable to enable extension %s in KVM, error %d", 441 multi_ext_cfg->name, ret); 442 exit(EXIT_FAILURE); 443 } 444 } 445 } 446 } 447 448 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 449 const char *name, 450 void *opaque, Error **errp) 451 { 452 bool value = false; 453 454 visit_type_bool(v, name, &value, errp); 455 } 456 457 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 458 const char *name, 459 void *opaque, Error **errp) 460 { 461 const char *propname = opaque; 462 bool value; 463 464 if (!visit_type_bool(v, name, &value, errp)) { 465 return; 466 } 467 468 if (value) { 469 error_setg(errp, "'%s' is not available with KVM", 470 propname); 471 } 472 } 473 474 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 475 { 476 /* Check if KVM created the property already */ 477 if (object_property_find(obj, prop_name)) { 478 return; 479 } 480 481 /* 482 * Set the default to disabled for every extension 483 * unknown to KVM and error out if the user attempts 484 * to enable any of them. 485 */ 486 object_property_add(obj, prop_name, "bool", 487 cpu_get_cfg_unavailable, 488 cpu_set_cfg_unavailable, 489 NULL, (void *)prop_name); 490 } 491 492 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 493 const RISCVCPUMultiExtConfig *array) 494 { 495 const RISCVCPUMultiExtConfig *prop; 496 497 g_assert(array); 498 499 for (prop = array; prop && prop->name; prop++) { 500 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 501 } 502 } 503 504 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 505 { 506 int i; 507 508 riscv_add_satp_mode_properties(cpu_obj); 509 510 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 511 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 512 int bit = misa_cfg->offset; 513 514 misa_cfg->name = riscv_get_misa_ext_name(bit); 515 misa_cfg->description = riscv_get_misa_ext_description(bit); 516 517 object_property_add(cpu_obj, misa_cfg->name, "bool", 518 kvm_cpu_get_misa_ext_cfg, 519 kvm_cpu_set_misa_ext_cfg, 520 NULL, misa_cfg); 521 object_property_set_description(cpu_obj, misa_cfg->name, 522 misa_cfg->description); 523 } 524 525 for (i = 0; misa_bits[i] != 0; i++) { 526 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 527 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 528 } 529 530 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 531 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 532 533 object_property_add(cpu_obj, multi_cfg->name, "bool", 534 kvm_cpu_get_multi_ext_cfg, 535 kvm_cpu_set_multi_ext_cfg, 536 NULL, multi_cfg); 537 } 538 539 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 540 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 541 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 542 543 /* We don't have the needed KVM support for profiles */ 544 for (i = 0; riscv_profiles[i] != NULL; i++) { 545 riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); 546 } 547 } 548 549 static int kvm_riscv_get_regs_core(CPUState *cs) 550 { 551 int ret = 0; 552 int i; 553 target_ulong reg; 554 CPURISCVState *env = &RISCV_CPU(cs)->env; 555 556 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 557 if (ret) { 558 return ret; 559 } 560 env->pc = reg; 561 562 for (i = 1; i < 32; i++) { 563 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 564 ret = kvm_get_one_reg(cs, id, ®); 565 if (ret) { 566 return ret; 567 } 568 env->gpr[i] = reg; 569 } 570 571 return ret; 572 } 573 574 static int kvm_riscv_put_regs_core(CPUState *cs) 575 { 576 int ret = 0; 577 int i; 578 target_ulong reg; 579 CPURISCVState *env = &RISCV_CPU(cs)->env; 580 581 reg = env->pc; 582 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 583 if (ret) { 584 return ret; 585 } 586 587 for (i = 1; i < 32; i++) { 588 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 589 reg = env->gpr[i]; 590 ret = kvm_set_one_reg(cs, id, ®); 591 if (ret) { 592 return ret; 593 } 594 } 595 596 return ret; 597 } 598 599 static int kvm_riscv_get_regs_csr(CPUState *cs) 600 { 601 CPURISCVState *env = &RISCV_CPU(cs)->env; 602 603 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 604 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 605 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 606 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 607 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 608 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 609 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 610 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 611 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 612 613 return 0; 614 } 615 616 static int kvm_riscv_put_regs_csr(CPUState *cs) 617 { 618 CPURISCVState *env = &RISCV_CPU(cs)->env; 619 620 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 621 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 622 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 623 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 624 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 625 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 626 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 627 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 628 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 629 630 return 0; 631 } 632 633 static int kvm_riscv_get_regs_fp(CPUState *cs) 634 { 635 int ret = 0; 636 int i; 637 CPURISCVState *env = &RISCV_CPU(cs)->env; 638 639 if (riscv_has_ext(env, RVD)) { 640 uint64_t reg; 641 for (i = 0; i < 32; i++) { 642 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 643 if (ret) { 644 return ret; 645 } 646 env->fpr[i] = reg; 647 } 648 return ret; 649 } 650 651 if (riscv_has_ext(env, RVF)) { 652 uint32_t reg; 653 for (i = 0; i < 32; i++) { 654 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 655 if (ret) { 656 return ret; 657 } 658 env->fpr[i] = reg; 659 } 660 return ret; 661 } 662 663 return ret; 664 } 665 666 static int kvm_riscv_put_regs_fp(CPUState *cs) 667 { 668 int ret = 0; 669 int i; 670 CPURISCVState *env = &RISCV_CPU(cs)->env; 671 672 if (riscv_has_ext(env, RVD)) { 673 uint64_t reg; 674 for (i = 0; i < 32; i++) { 675 reg = env->fpr[i]; 676 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 677 if (ret) { 678 return ret; 679 } 680 } 681 return ret; 682 } 683 684 if (riscv_has_ext(env, RVF)) { 685 uint32_t reg; 686 for (i = 0; i < 32; i++) { 687 reg = env->fpr[i]; 688 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 689 if (ret) { 690 return ret; 691 } 692 } 693 return ret; 694 } 695 696 return ret; 697 } 698 699 static void kvm_riscv_get_regs_timer(CPUState *cs) 700 { 701 CPURISCVState *env = &RISCV_CPU(cs)->env; 702 703 if (env->kvm_timer_dirty) { 704 return; 705 } 706 707 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 708 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 709 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 710 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 711 712 env->kvm_timer_dirty = true; 713 } 714 715 static void kvm_riscv_put_regs_timer(CPUState *cs) 716 { 717 uint64_t reg; 718 CPURISCVState *env = &RISCV_CPU(cs)->env; 719 720 if (!env->kvm_timer_dirty) { 721 return; 722 } 723 724 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 725 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 726 727 /* 728 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 729 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 730 * doesn't matter that adaping in QEMU now. 731 * TODO If KVM changes, adapt here. 732 */ 733 if (env->kvm_timer_state) { 734 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 735 } 736 737 /* 738 * For now, migration will not work between Hosts with different timer 739 * frequency. Therefore, we should check whether they are the same here 740 * during the migration. 741 */ 742 if (migration_is_running()) { 743 KVM_RISCV_GET_TIMER(cs, frequency, reg); 744 if (reg != env->kvm_timer_frequency) { 745 error_report("Dst Hosts timer frequency != Src Hosts"); 746 } 747 } 748 749 env->kvm_timer_dirty = false; 750 } 751 752 uint64_t kvm_riscv_get_timebase_frequency(CPUState *cs) 753 { 754 uint64_t reg; 755 756 KVM_RISCV_GET_TIMER(cs, frequency, reg); 757 758 return reg; 759 } 760 761 static int kvm_riscv_get_regs_vector(CPUState *cs) 762 { 763 RISCVCPU *cpu = RISCV_CPU(cs); 764 CPURISCVState *env = &cpu->env; 765 target_ulong reg; 766 uint64_t vreg_id; 767 int vreg_idx, ret = 0; 768 769 if (!riscv_has_ext(env, RVV)) { 770 return 0; 771 } 772 773 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 774 if (ret) { 775 return ret; 776 } 777 env->vstart = reg; 778 779 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 780 if (ret) { 781 return ret; 782 } 783 env->vl = reg; 784 785 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 786 if (ret) { 787 return ret; 788 } 789 env->vtype = reg; 790 791 if (kvm_v_vlenb.supported) { 792 ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 793 if (ret) { 794 return ret; 795 } 796 cpu->cfg.vlenb = reg; 797 798 for (int i = 0; i < 32; i++) { 799 /* 800 * vreg[] is statically allocated using RV_VLEN_MAX. 801 * Use it instead of vlenb to calculate vreg_idx for 802 * simplicity. 803 */ 804 vreg_idx = i * RV_VLEN_MAX / 64; 805 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 806 807 ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 808 if (ret) { 809 return ret; 810 } 811 } 812 } 813 814 return 0; 815 } 816 817 static int kvm_riscv_put_regs_vector(CPUState *cs) 818 { 819 RISCVCPU *cpu = RISCV_CPU(cs); 820 CPURISCVState *env = &cpu->env; 821 target_ulong reg; 822 uint64_t vreg_id; 823 int vreg_idx, ret = 0; 824 825 if (!riscv_has_ext(env, RVV)) { 826 return 0; 827 } 828 829 reg = env->vstart; 830 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); 831 if (ret) { 832 return ret; 833 } 834 835 reg = env->vl; 836 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); 837 if (ret) { 838 return ret; 839 } 840 841 reg = env->vtype; 842 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); 843 if (ret) { 844 return ret; 845 } 846 847 if (kvm_v_vlenb.supported) { 848 reg = cpu->cfg.vlenb; 849 ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®); 850 851 for (int i = 0; i < 32; i++) { 852 /* 853 * vreg[] is statically allocated using RV_VLEN_MAX. 854 * Use it instead of vlenb to calculate vreg_idx for 855 * simplicity. 856 */ 857 vreg_idx = i * RV_VLEN_MAX / 64; 858 vreg_id = kvm_riscv_vector_reg_id(cpu, i); 859 860 ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); 861 if (ret) { 862 return ret; 863 } 864 } 865 } 866 867 return ret; 868 } 869 870 typedef struct KVMScratchCPU { 871 int kvmfd; 872 int vmfd; 873 int cpufd; 874 } KVMScratchCPU; 875 876 /* 877 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 878 * from target/arm/kvm.c. 879 */ 880 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 881 { 882 int kvmfd = -1, vmfd = -1, cpufd = -1; 883 884 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 885 if (kvmfd < 0) { 886 goto err; 887 } 888 do { 889 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 890 } while (vmfd == -1 && errno == EINTR); 891 if (vmfd < 0) { 892 goto err; 893 } 894 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 895 if (cpufd < 0) { 896 goto err; 897 } 898 899 scratch->kvmfd = kvmfd; 900 scratch->vmfd = vmfd; 901 scratch->cpufd = cpufd; 902 903 return true; 904 905 err: 906 if (cpufd >= 0) { 907 close(cpufd); 908 } 909 if (vmfd >= 0) { 910 close(vmfd); 911 } 912 if (kvmfd >= 0) { 913 close(kvmfd); 914 } 915 916 return false; 917 } 918 919 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 920 { 921 close(scratch->cpufd); 922 close(scratch->vmfd); 923 close(scratch->kvmfd); 924 } 925 926 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 927 { 928 CPURISCVState *env = &cpu->env; 929 struct kvm_one_reg reg; 930 int ret; 931 932 reg.id = RISCV_CONFIG_REG(env, mvendorid); 933 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 934 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 935 if (ret != 0) { 936 error_report("Unable to retrieve mvendorid from host, error %d", ret); 937 } 938 939 reg.id = RISCV_CONFIG_REG(env, marchid); 940 reg.addr = (uint64_t)&cpu->cfg.marchid; 941 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 942 if (ret != 0) { 943 error_report("Unable to retrieve marchid from host, error %d", ret); 944 } 945 946 reg.id = RISCV_CONFIG_REG(env, mimpid); 947 reg.addr = (uint64_t)&cpu->cfg.mimpid; 948 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 949 if (ret != 0) { 950 error_report("Unable to retrieve mimpid from host, error %d", ret); 951 } 952 } 953 954 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 955 KVMScratchCPU *kvmcpu) 956 { 957 CPURISCVState *env = &cpu->env; 958 struct kvm_one_reg reg; 959 int ret; 960 961 reg.id = RISCV_CONFIG_REG(env, isa); 962 reg.addr = (uint64_t)&env->misa_ext_mask; 963 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 964 965 if (ret) { 966 error_report("Unable to fetch ISA register from KVM, " 967 "error %d", ret); 968 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 969 exit(EXIT_FAILURE); 970 } 971 972 env->misa_ext = env->misa_ext_mask; 973 } 974 975 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 976 KVMCPUConfig *cbomz_cfg) 977 { 978 CPURISCVState *env = &cpu->env; 979 struct kvm_one_reg reg; 980 int ret; 981 982 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 983 cbomz_cfg->kvm_reg_id); 984 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 985 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 986 if (ret != 0) { 987 error_report("Unable to read KVM reg %s, error %d", 988 cbomz_cfg->name, ret); 989 exit(EXIT_FAILURE); 990 } 991 } 992 993 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 994 KVMScratchCPU *kvmcpu) 995 { 996 CPURISCVState *env = &cpu->env; 997 uint64_t val; 998 int i, ret; 999 1000 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1001 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1002 struct kvm_one_reg reg; 1003 1004 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 1005 multi_ext_cfg->kvm_reg_id); 1006 reg.addr = (uint64_t)&val; 1007 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1008 if (ret != 0) { 1009 if (errno == EINVAL) { 1010 /* Silently default to 'false' if KVM does not support it. */ 1011 multi_ext_cfg->supported = false; 1012 val = false; 1013 } else { 1014 error_report("Unable to read ISA_EXT KVM register %s: %s", 1015 multi_ext_cfg->name, strerror(errno)); 1016 exit(EXIT_FAILURE); 1017 } 1018 } else { 1019 multi_ext_cfg->supported = true; 1020 } 1021 1022 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1023 } 1024 1025 if (cpu->cfg.ext_zicbom) { 1026 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1027 } 1028 1029 if (cpu->cfg.ext_zicboz) { 1030 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1031 } 1032 } 1033 1034 static int uint64_cmp(const void *a, const void *b) 1035 { 1036 uint64_t val1 = *(const uint64_t *)a; 1037 uint64_t val2 = *(const uint64_t *)b; 1038 1039 if (val1 < val2) { 1040 return -1; 1041 } 1042 1043 if (val1 > val2) { 1044 return 1; 1045 } 1046 1047 return 0; 1048 } 1049 1050 static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, 1051 KVMScratchCPU *kvmcpu, 1052 struct kvm_reg_list *reglist) 1053 { 1054 struct kvm_reg_list *reg_search; 1055 1056 reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, 1057 sizeof(uint64_t), uint64_cmp); 1058 1059 if (reg_search) { 1060 kvm_sbi_dbcn.supported = true; 1061 } 1062 } 1063 1064 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 1065 struct kvm_reg_list *reglist) 1066 { 1067 struct kvm_one_reg reg; 1068 struct kvm_reg_list *reg_search; 1069 uint64_t val; 1070 int ret; 1071 1072 reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, 1073 sizeof(uint64_t), uint64_cmp); 1074 1075 if (reg_search) { 1076 reg.id = kvm_v_vlenb.kvm_reg_id; 1077 reg.addr = (uint64_t)&val; 1078 1079 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1080 if (ret != 0) { 1081 error_report("Unable to read vlenb register, error code: %d", 1082 errno); 1083 exit(EXIT_FAILURE); 1084 } 1085 1086 kvm_v_vlenb.supported = true; 1087 cpu->cfg.vlenb = val; 1088 } 1089 } 1090 1091 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 1092 { 1093 KVMCPUConfig *multi_ext_cfg; 1094 struct kvm_one_reg reg; 1095 struct kvm_reg_list rl_struct; 1096 struct kvm_reg_list *reglist; 1097 uint64_t val, reg_id, *reg_search; 1098 int i, ret; 1099 1100 rl_struct.n = 0; 1101 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 1102 1103 /* 1104 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 1105 * (EINVAL). Use read_legacy() in this case. 1106 */ 1107 if (errno == EINVAL) { 1108 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 1109 } else if (errno != E2BIG) { 1110 /* 1111 * E2BIG is an expected error message for the API since we 1112 * don't know the number of registers. The right amount will 1113 * be written in rl_struct.n. 1114 * 1115 * Error out if we get any other errno. 1116 */ 1117 error_report("Error when accessing get-reg-list: %s", 1118 strerror(errno)); 1119 exit(EXIT_FAILURE); 1120 } 1121 1122 reglist = g_malloc(sizeof(struct kvm_reg_list) + 1123 rl_struct.n * sizeof(uint64_t)); 1124 reglist->n = rl_struct.n; 1125 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 1126 if (ret) { 1127 error_report("Error when reading KVM_GET_REG_LIST: %s", 1128 strerror(errno)); 1129 exit(EXIT_FAILURE); 1130 } 1131 1132 /* sort reglist to use bsearch() */ 1133 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 1134 1135 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 1136 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 1137 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 1138 multi_ext_cfg->kvm_reg_id); 1139 reg_search = bsearch(®_id, reglist->reg, reglist->n, 1140 sizeof(uint64_t), uint64_cmp); 1141 if (!reg_search) { 1142 continue; 1143 } 1144 1145 reg.id = reg_id; 1146 reg.addr = (uint64_t)&val; 1147 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 1148 if (ret != 0) { 1149 error_report("Unable to read ISA_EXT KVM register %s: %s", 1150 multi_ext_cfg->name, strerror(errno)); 1151 exit(EXIT_FAILURE); 1152 } 1153 1154 multi_ext_cfg->supported = true; 1155 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 1156 } 1157 1158 if (cpu->cfg.ext_zicbom) { 1159 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 1160 } 1161 1162 if (cpu->cfg.ext_zicboz) { 1163 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 1164 } 1165 1166 if (riscv_has_ext(&cpu->env, RVV)) { 1167 kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); 1168 } 1169 1170 kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist); 1171 } 1172 1173 static void riscv_init_kvm_registers(Object *cpu_obj) 1174 { 1175 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 1176 KVMScratchCPU kvmcpu; 1177 1178 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1179 return; 1180 } 1181 1182 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 1183 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 1184 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 1185 1186 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1187 } 1188 1189 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 1190 KVM_CAP_LAST_INFO 1191 }; 1192 1193 int kvm_arch_get_registers(CPUState *cs) 1194 { 1195 int ret = 0; 1196 1197 ret = kvm_riscv_get_regs_core(cs); 1198 if (ret) { 1199 return ret; 1200 } 1201 1202 ret = kvm_riscv_get_regs_csr(cs); 1203 if (ret) { 1204 return ret; 1205 } 1206 1207 ret = kvm_riscv_get_regs_fp(cs); 1208 if (ret) { 1209 return ret; 1210 } 1211 1212 ret = kvm_riscv_get_regs_vector(cs); 1213 if (ret) { 1214 return ret; 1215 } 1216 1217 return ret; 1218 } 1219 1220 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1221 { 1222 if (cap_has_mp_state) { 1223 struct kvm_mp_state mp_state = { 1224 .mp_state = state 1225 }; 1226 1227 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1228 if (ret) { 1229 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1230 __func__, ret, strerror(-ret)); 1231 return -1; 1232 } 1233 } 1234 1235 return 0; 1236 } 1237 1238 int kvm_arch_put_registers(CPUState *cs, int level) 1239 { 1240 int ret = 0; 1241 1242 ret = kvm_riscv_put_regs_core(cs); 1243 if (ret) { 1244 return ret; 1245 } 1246 1247 ret = kvm_riscv_put_regs_csr(cs); 1248 if (ret) { 1249 return ret; 1250 } 1251 1252 ret = kvm_riscv_put_regs_fp(cs); 1253 if (ret) { 1254 return ret; 1255 } 1256 1257 ret = kvm_riscv_put_regs_vector(cs); 1258 if (ret) { 1259 return ret; 1260 } 1261 1262 if (KVM_PUT_RESET_STATE == level) { 1263 RISCVCPU *cpu = RISCV_CPU(cs); 1264 if (cs->cpu_index == 0) { 1265 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1266 } else { 1267 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1268 } 1269 if (ret) { 1270 return ret; 1271 } 1272 } 1273 1274 return ret; 1275 } 1276 1277 int kvm_arch_release_virq_post(int virq) 1278 { 1279 return 0; 1280 } 1281 1282 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1283 uint64_t address, uint32_t data, PCIDevice *dev) 1284 { 1285 return 0; 1286 } 1287 1288 int kvm_arch_destroy_vcpu(CPUState *cs) 1289 { 1290 return 0; 1291 } 1292 1293 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1294 { 1295 return cpu->cpu_index; 1296 } 1297 1298 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1299 RunState state) 1300 { 1301 CPUState *cs = opaque; 1302 1303 if (running) { 1304 kvm_riscv_put_regs_timer(cs); 1305 } else { 1306 kvm_riscv_get_regs_timer(cs); 1307 } 1308 } 1309 1310 void kvm_arch_init_irq_routing(KVMState *s) 1311 { 1312 } 1313 1314 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1315 { 1316 CPURISCVState *env = &cpu->env; 1317 target_ulong reg; 1318 uint64_t id; 1319 int ret; 1320 1321 id = RISCV_CONFIG_REG(env, mvendorid); 1322 /* 1323 * cfg.mvendorid is an uint32 but a target_ulong will 1324 * be written. Assign it to a target_ulong var to avoid 1325 * writing pieces of other cpu->cfg fields in the reg. 1326 */ 1327 reg = cpu->cfg.mvendorid; 1328 ret = kvm_set_one_reg(cs, id, ®); 1329 if (ret != 0) { 1330 return ret; 1331 } 1332 1333 id = RISCV_CONFIG_REG(env, marchid); 1334 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1335 if (ret != 0) { 1336 return ret; 1337 } 1338 1339 id = RISCV_CONFIG_REG(env, mimpid); 1340 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1341 1342 return ret; 1343 } 1344 1345 static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) 1346 { 1347 target_ulong reg = 1; 1348 1349 if (!kvm_sbi_dbcn.supported) { 1350 return 0; 1351 } 1352 1353 return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); 1354 } 1355 1356 int kvm_arch_init_vcpu(CPUState *cs) 1357 { 1358 int ret = 0; 1359 RISCVCPU *cpu = RISCV_CPU(cs); 1360 1361 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1362 1363 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1364 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1365 if (ret != 0) { 1366 return ret; 1367 } 1368 } 1369 1370 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1371 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1372 1373 ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); 1374 1375 return ret; 1376 } 1377 1378 int kvm_arch_msi_data_to_gsi(uint32_t data) 1379 { 1380 abort(); 1381 } 1382 1383 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1384 int vector, PCIDevice *dev) 1385 { 1386 return 0; 1387 } 1388 1389 int kvm_arch_get_default_type(MachineState *ms) 1390 { 1391 return 0; 1392 } 1393 1394 int kvm_arch_init(MachineState *ms, KVMState *s) 1395 { 1396 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1397 return 0; 1398 } 1399 1400 int kvm_arch_irqchip_create(KVMState *s) 1401 { 1402 if (kvm_kernel_irqchip_split()) { 1403 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1404 exit(1); 1405 } 1406 1407 /* 1408 * We can create the VAIA using the newer device control API. 1409 */ 1410 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1411 } 1412 1413 int kvm_arch_process_async_events(CPUState *cs) 1414 { 1415 return 0; 1416 } 1417 1418 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1419 { 1420 } 1421 1422 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1423 { 1424 return MEMTXATTRS_UNSPECIFIED; 1425 } 1426 1427 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1428 { 1429 return true; 1430 } 1431 1432 static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) 1433 { 1434 g_autofree uint8_t *buf = NULL; 1435 RISCVCPU *cpu = RISCV_CPU(cs); 1436 target_ulong num_bytes; 1437 uint64_t addr; 1438 unsigned char ch; 1439 int ret; 1440 1441 switch (run->riscv_sbi.function_id) { 1442 case SBI_EXT_DBCN_CONSOLE_READ: 1443 case SBI_EXT_DBCN_CONSOLE_WRITE: 1444 num_bytes = run->riscv_sbi.args[0]; 1445 1446 if (num_bytes == 0) { 1447 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1448 run->riscv_sbi.ret[1] = 0; 1449 break; 1450 } 1451 1452 addr = run->riscv_sbi.args[1]; 1453 1454 /* 1455 * Handle the case where a 32 bit CPU is running in a 1456 * 64 bit addressing env. 1457 */ 1458 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { 1459 addr |= (uint64_t)run->riscv_sbi.args[2] << 32; 1460 } 1461 1462 buf = g_malloc0(num_bytes); 1463 1464 if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { 1465 ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); 1466 if (ret < 0) { 1467 error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " 1468 "reading chardev"); 1469 exit(1); 1470 } 1471 1472 cpu_physical_memory_write(addr, buf, ret); 1473 } else { 1474 cpu_physical_memory_read(addr, buf, num_bytes); 1475 1476 ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); 1477 if (ret < 0) { 1478 error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " 1479 "writing chardev"); 1480 exit(1); 1481 } 1482 } 1483 1484 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1485 run->riscv_sbi.ret[1] = ret; 1486 break; 1487 case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: 1488 ch = run->riscv_sbi.args[0]; 1489 ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1490 1491 if (ret < 0) { 1492 error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " 1493 "writing chardev"); 1494 exit(1); 1495 } 1496 1497 run->riscv_sbi.ret[0] = SBI_SUCCESS; 1498 run->riscv_sbi.ret[1] = 0; 1499 break; 1500 default: 1501 run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; 1502 } 1503 } 1504 1505 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1506 { 1507 int ret = 0; 1508 unsigned char ch; 1509 switch (run->riscv_sbi.extension_id) { 1510 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1511 ch = run->riscv_sbi.args[0]; 1512 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1513 break; 1514 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1515 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1516 if (ret == sizeof(ch)) { 1517 run->riscv_sbi.ret[0] = ch; 1518 } else { 1519 run->riscv_sbi.ret[0] = -1; 1520 } 1521 ret = 0; 1522 break; 1523 case SBI_EXT_DBCN: 1524 kvm_riscv_handle_sbi_dbcn(cs, run); 1525 break; 1526 default: 1527 qemu_log_mask(LOG_UNIMP, 1528 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1529 __func__, run->riscv_sbi.extension_id); 1530 ret = -1; 1531 break; 1532 } 1533 return ret; 1534 } 1535 1536 static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) 1537 { 1538 target_ulong csr_num = run->riscv_csr.csr_num; 1539 target_ulong new_value = run->riscv_csr.new_value; 1540 target_ulong write_mask = run->riscv_csr.write_mask; 1541 int ret = 0; 1542 1543 switch (csr_num) { 1544 case CSR_SEED: 1545 run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); 1546 break; 1547 default: 1548 qemu_log_mask(LOG_UNIMP, 1549 "%s: un-handled CSR EXIT for CSR %lx\n", 1550 __func__, csr_num); 1551 ret = -1; 1552 break; 1553 } 1554 1555 return ret; 1556 } 1557 1558 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1559 { 1560 int ret = 0; 1561 switch (run->exit_reason) { 1562 case KVM_EXIT_RISCV_SBI: 1563 ret = kvm_riscv_handle_sbi(cs, run); 1564 break; 1565 case KVM_EXIT_RISCV_CSR: 1566 ret = kvm_riscv_handle_csr(cs, run); 1567 break; 1568 default: 1569 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1570 __func__, run->exit_reason); 1571 ret = -1; 1572 break; 1573 } 1574 return ret; 1575 } 1576 1577 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1578 { 1579 CPURISCVState *env = &cpu->env; 1580 int i; 1581 1582 if (!kvm_enabled()) { 1583 return; 1584 } 1585 for (i = 0; i < 32; i++) { 1586 env->gpr[i] = 0; 1587 } 1588 env->pc = cpu->env.kernel_addr; 1589 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1590 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1591 env->satp = 0; 1592 env->mie = 0; 1593 env->stvec = 0; 1594 env->sscratch = 0; 1595 env->sepc = 0; 1596 env->scause = 0; 1597 env->stval = 0; 1598 env->mip = 0; 1599 } 1600 1601 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1602 { 1603 int ret; 1604 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1605 1606 if (irq != IRQ_S_EXT) { 1607 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1608 abort(); 1609 } 1610 1611 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1612 if (ret < 0) { 1613 perror("Set irq failed"); 1614 abort(); 1615 } 1616 } 1617 1618 static int aia_mode; 1619 1620 static const char *kvm_aia_mode_str(uint64_t mode) 1621 { 1622 switch (mode) { 1623 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1624 return "emul"; 1625 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1626 return "hwaccel"; 1627 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1628 default: 1629 return "auto"; 1630 }; 1631 } 1632 1633 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1634 { 1635 return g_strdup(kvm_aia_mode_str(aia_mode)); 1636 } 1637 1638 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1639 { 1640 if (!strcmp(val, "emul")) { 1641 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1642 } else if (!strcmp(val, "hwaccel")) { 1643 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1644 } else if (!strcmp(val, "auto")) { 1645 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1646 } else { 1647 error_setg(errp, "Invalid KVM AIA mode"); 1648 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1649 } 1650 } 1651 1652 void kvm_arch_accel_class_init(ObjectClass *oc) 1653 { 1654 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1655 riscv_set_kvm_aia); 1656 object_class_property_set_description(oc, "riscv-aia", 1657 "Set KVM AIA mode. Valid values are " 1658 "emul, hwaccel, and auto. Default " 1659 "is auto."); 1660 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1661 "auto"); 1662 } 1663 1664 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1665 uint64_t aia_irq_num, uint64_t aia_msi_num, 1666 uint64_t aplic_base, uint64_t imsic_base, 1667 uint64_t guest_num) 1668 { 1669 int ret, i; 1670 int aia_fd = -1; 1671 uint64_t default_aia_mode; 1672 uint64_t socket_count = riscv_socket_count(machine); 1673 uint64_t max_hart_per_socket = 0; 1674 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1675 uint64_t socket_bits, hart_bits, guest_bits; 1676 1677 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1678 1679 if (aia_fd < 0) { 1680 error_report("Unable to create in-kernel irqchip"); 1681 exit(1); 1682 } 1683 1684 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1685 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1686 &default_aia_mode, false, NULL); 1687 if (ret < 0) { 1688 error_report("KVM AIA: failed to get current KVM AIA mode"); 1689 exit(1); 1690 } 1691 qemu_log("KVM AIA: default mode is %s\n", 1692 kvm_aia_mode_str(default_aia_mode)); 1693 1694 if (default_aia_mode != aia_mode) { 1695 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1696 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1697 &aia_mode, true, NULL); 1698 if (ret < 0) 1699 warn_report("KVM AIA: failed to set KVM AIA mode"); 1700 else 1701 qemu_log("KVM AIA: set current mode to %s\n", 1702 kvm_aia_mode_str(aia_mode)); 1703 } 1704 1705 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1706 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1707 &aia_irq_num, true, NULL); 1708 if (ret < 0) { 1709 error_report("KVM AIA: failed to set number of input irq lines"); 1710 exit(1); 1711 } 1712 1713 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1714 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1715 &aia_msi_num, true, NULL); 1716 if (ret < 0) { 1717 error_report("KVM AIA: failed to set number of msi"); 1718 exit(1); 1719 } 1720 1721 1722 if (socket_count > 1) { 1723 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1724 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1725 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1726 &socket_bits, true, NULL); 1727 if (ret < 0) { 1728 error_report("KVM AIA: failed to set group_bits"); 1729 exit(1); 1730 } 1731 1732 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1733 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1734 &group_shift, true, NULL); 1735 if (ret < 0) { 1736 error_report("KVM AIA: failed to set group_shift"); 1737 exit(1); 1738 } 1739 } 1740 1741 guest_bits = guest_num == 0 ? 0 : 1742 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1743 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1744 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1745 &guest_bits, true, NULL); 1746 if (ret < 0) { 1747 error_report("KVM AIA: failed to set guest_bits"); 1748 exit(1); 1749 } 1750 1751 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1752 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1753 &aplic_base, true, NULL); 1754 if (ret < 0) { 1755 error_report("KVM AIA: failed to set the base address of APLIC"); 1756 exit(1); 1757 } 1758 1759 for (socket = 0; socket < socket_count; socket++) { 1760 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1761 hart_count = riscv_socket_hart_count(machine, socket); 1762 base_hart = riscv_socket_first_hartid(machine, socket); 1763 1764 if (max_hart_per_socket < hart_count) { 1765 max_hart_per_socket = hart_count; 1766 } 1767 1768 for (i = 0; i < hart_count; i++) { 1769 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1770 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1771 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1772 &imsic_addr, true, NULL); 1773 if (ret < 0) { 1774 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1775 exit(1); 1776 } 1777 } 1778 } 1779 1780 1781 if (max_hart_per_socket > 1) { 1782 max_hart_per_socket--; 1783 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1784 } else { 1785 hart_bits = 0; 1786 } 1787 1788 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1789 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1790 &hart_bits, true, NULL); 1791 if (ret < 0) { 1792 error_report("KVM AIA: failed to set hart_bits"); 1793 exit(1); 1794 } 1795 1796 if (kvm_has_gsi_routing()) { 1797 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1798 /* KVM AIA only has one APLIC instance */ 1799 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1800 } 1801 kvm_gsi_routing_allowed = true; 1802 kvm_irqchip_commit_routes(kvm_state); 1803 } 1804 1805 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1806 KVM_DEV_RISCV_AIA_CTRL_INIT, 1807 NULL, true, NULL); 1808 if (ret < 0) { 1809 error_report("KVM AIA: initialized fail"); 1810 exit(1); 1811 } 1812 1813 kvm_msi_via_irqfd_allowed = true; 1814 } 1815 1816 static void kvm_cpu_instance_init(CPUState *cs) 1817 { 1818 Object *obj = OBJECT(RISCV_CPU(cs)); 1819 1820 riscv_init_kvm_registers(obj); 1821 1822 kvm_riscv_add_cpu_user_properties(obj); 1823 } 1824 1825 /* 1826 * We'll get here via the following path: 1827 * 1828 * riscv_cpu_realize() 1829 * -> cpu_exec_realizefn() 1830 * -> kvm_cpu_realize() (via accel_cpu_common_realize()) 1831 */ 1832 static bool kvm_cpu_realize(CPUState *cs, Error **errp) 1833 { 1834 RISCVCPU *cpu = RISCV_CPU(cs); 1835 int ret; 1836 1837 if (riscv_has_ext(&cpu->env, RVV)) { 1838 ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); 1839 if (ret) { 1840 error_setg(errp, "Error in prctl PR_RISCV_V_SET_CONTROL, code: %s", 1841 strerrorname_np(errno)); 1842 return false; 1843 } 1844 } 1845 1846 return true; 1847 } 1848 1849 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1850 { 1851 CPURISCVState *env = &cpu->env; 1852 KVMScratchCPU kvmcpu; 1853 struct kvm_one_reg reg; 1854 uint64_t val; 1855 int ret; 1856 1857 /* short-circuit without spinning the scratch CPU */ 1858 if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz && 1859 !riscv_has_ext(env, RVV)) { 1860 return; 1861 } 1862 1863 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 1864 error_setg(errp, "Unable to create scratch KVM cpu"); 1865 return; 1866 } 1867 1868 if (cpu->cfg.ext_zicbom && 1869 riscv_cpu_option_set(kvm_cbom_blocksize.name)) { 1870 1871 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1872 kvm_cbom_blocksize.kvm_reg_id); 1873 reg.addr = (uint64_t)&val; 1874 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1875 if (ret != 0) { 1876 error_setg(errp, "Unable to read cbom_blocksize, error %d", errno); 1877 return; 1878 } 1879 1880 if (cpu->cfg.cbom_blocksize != val) { 1881 error_setg(errp, "Unable to set cbom_blocksize to a different " 1882 "value than the host (%lu)", val); 1883 return; 1884 } 1885 } 1886 1887 if (cpu->cfg.ext_zicboz && 1888 riscv_cpu_option_set(kvm_cboz_blocksize.name)) { 1889 1890 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 1891 kvm_cboz_blocksize.kvm_reg_id); 1892 reg.addr = (uint64_t)&val; 1893 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1894 if (ret != 0) { 1895 error_setg(errp, "Unable to read cboz_blocksize, error %d", errno); 1896 return; 1897 } 1898 1899 if (cpu->cfg.cboz_blocksize != val) { 1900 error_setg(errp, "Unable to set cboz_blocksize to a different " 1901 "value than the host (%lu)", val); 1902 return; 1903 } 1904 } 1905 1906 /* Users are setting vlen, not vlenb */ 1907 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { 1908 if (!kvm_v_vlenb.supported) { 1909 error_setg(errp, "Unable to set 'vlenb': register not supported"); 1910 return; 1911 } 1912 1913 reg.id = kvm_v_vlenb.kvm_reg_id; 1914 reg.addr = (uint64_t)&val; 1915 ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); 1916 if (ret != 0) { 1917 error_setg(errp, "Unable to read vlenb register, error %d", errno); 1918 return; 1919 } 1920 1921 if (cpu->cfg.vlenb != val) { 1922 error_setg(errp, "Unable to set 'vlen' to a different " 1923 "value than the host (%lu)", val * 8); 1924 return; 1925 } 1926 } 1927 1928 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 1929 } 1930 1931 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1932 { 1933 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1934 1935 acc->cpu_instance_init = kvm_cpu_instance_init; 1936 acc->cpu_target_realize = kvm_cpu_realize; 1937 } 1938 1939 static const TypeInfo kvm_cpu_accel_type_info = { 1940 .name = ACCEL_CPU_NAME("kvm"), 1941 1942 .parent = TYPE_ACCEL_CPU, 1943 .class_init = kvm_cpu_accel_class_init, 1944 .abstract = true, 1945 }; 1946 static void kvm_cpu_accel_register_types(void) 1947 { 1948 type_register_static(&kvm_cpu_accel_type_info); 1949 } 1950 type_init(kvm_cpu_accel_register_types); 1951 1952 static void riscv_host_cpu_class_init(ObjectClass *c, void *data) 1953 { 1954 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1955 1956 #if defined(TARGET_RISCV32) 1957 mcc->misa_mxl_max = MXL_RV32; 1958 #elif defined(TARGET_RISCV64) 1959 mcc->misa_mxl_max = MXL_RV64; 1960 #endif 1961 } 1962 1963 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1964 { 1965 .name = TYPE_RISCV_CPU_HOST, 1966 .parent = TYPE_RISCV_CPU, 1967 .class_init = riscv_host_cpu_class_init, 1968 } 1969 }; 1970 1971 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1972