1 /* 2 * QEMU RISC-V CPU -- internal functions and types 3 * 4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef RISCV_CPU_INTERNALS_H 20 #define RISCV_CPU_INTERNALS_H 21 22 #include "hw/registerfields.h" 23 24 /* share data between vector helpers and decode code */ 25 FIELD(VDATA, VM, 0, 1) 26 FIELD(VDATA, LMUL, 1, 3) 27 FIELD(VDATA, VTA, 4, 1) 28 FIELD(VDATA, NF, 5, 4) 29 FIELD(VDATA, WD, 5, 1) 30 31 /* float point classify helpers */ 32 target_ulong fclass_h(uint64_t frs1); 33 target_ulong fclass_s(uint64_t frs1); 34 target_ulong fclass_d(uint64_t frs1); 35 36 #ifndef CONFIG_USER_ONLY 37 extern const VMStateDescription vmstate_riscv_cpu; 38 #endif 39 40 enum { 41 RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */ 42 RISCV_FRM_RTZ = 1, /* Round towards Zero */ 43 RISCV_FRM_RDN = 2, /* Round Down */ 44 RISCV_FRM_RUP = 3, /* Round Up */ 45 RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ 46 RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ 47 RISCV_FRM_ROD = 8, /* Round to Odd */ 48 }; 49 50 static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) 51 { 52 /* the value is sign-extended instead of NaN-boxing for zfinx */ 53 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 54 return (int32_t)f; 55 } else { 56 return f | MAKE_64BIT_MASK(32, 32); 57 } 58 } 59 60 static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) 61 { 62 /* Disable NaN-boxing check when enable zfinx */ 63 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 64 return (uint32_t)f; 65 } 66 67 uint64_t mask = MAKE_64BIT_MASK(32, 32); 68 69 if (likely((f & mask) == mask)) { 70 return (uint32_t)f; 71 } else { 72 return 0x7fc00000u; /* default qnan */ 73 } 74 } 75 76 static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) 77 { 78 /* the value is sign-extended instead of NaN-boxing for zfinx */ 79 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 80 return (int16_t)f; 81 } else { 82 return f | MAKE_64BIT_MASK(16, 48); 83 } 84 } 85 86 static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) 87 { 88 /* Disable nanbox check when enable zfinx */ 89 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 90 return (uint16_t)f; 91 } 92 93 uint64_t mask = MAKE_64BIT_MASK(16, 48); 94 95 if (likely((f & mask) == mask)) { 96 return (uint16_t)f; 97 } else { 98 return 0x7E00u; /* default qnan */ 99 } 100 } 101 102 #endif 103