1 /* 2 * QEMU RISC-V CPU -- internal functions and types 3 * 4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef RISCV_CPU_INTERNALS_H 20 #define RISCV_CPU_INTERNALS_H 21 22 #include "hw/registerfields.h" 23 24 /* 25 * The current MMU Modes are: 26 * - U 0b000 27 * - S 0b001 28 * - S+SUM 0b010 29 * - M 0b011 30 * - HLV/HLVX/HSV adds 0b100 31 */ 32 #define MMUIdx_U 0 33 #define MMUIdx_S 1 34 #define MMUIdx_S_SUM 2 35 #define MMUIdx_M 3 36 #define MMU_HYP_ACCESS_BIT (1 << 2) 37 38 /* share data between vector helpers and decode code */ 39 FIELD(VDATA, VM, 0, 1) 40 FIELD(VDATA, LMUL, 1, 3) 41 FIELD(VDATA, VTA, 4, 1) 42 FIELD(VDATA, VTA_ALL_1S, 5, 1) 43 FIELD(VDATA, VMA, 6, 1) 44 FIELD(VDATA, NF, 7, 4) 45 FIELD(VDATA, WD, 7, 1) 46 47 /* float point classify helpers */ 48 target_ulong fclass_h(uint64_t frs1); 49 target_ulong fclass_s(uint64_t frs1); 50 target_ulong fclass_d(uint64_t frs1); 51 52 #ifndef CONFIG_USER_ONLY 53 extern const VMStateDescription vmstate_riscv_cpu; 54 #endif 55 56 enum { 57 RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */ 58 RISCV_FRM_RTZ = 1, /* Round towards Zero */ 59 RISCV_FRM_RDN = 2, /* Round Down */ 60 RISCV_FRM_RUP = 3, /* Round Up */ 61 RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ 62 RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ 63 RISCV_FRM_ROD = 8, /* Round to Odd */ 64 }; 65 66 static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) 67 { 68 /* the value is sign-extended instead of NaN-boxing for zfinx */ 69 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 70 return (int32_t)f; 71 } else { 72 return f | MAKE_64BIT_MASK(32, 32); 73 } 74 } 75 76 static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) 77 { 78 /* Disable NaN-boxing check when enable zfinx */ 79 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 80 return (uint32_t)f; 81 } 82 83 uint64_t mask = MAKE_64BIT_MASK(32, 32); 84 85 if (likely((f & mask) == mask)) { 86 return (uint32_t)f; 87 } else { 88 return 0x7fc00000u; /* default qnan */ 89 } 90 } 91 92 static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) 93 { 94 /* the value is sign-extended instead of NaN-boxing for zfinx */ 95 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 96 return (int16_t)f; 97 } else { 98 return f | MAKE_64BIT_MASK(16, 48); 99 } 100 } 101 102 static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) 103 { 104 /* Disable nanbox check when enable zfinx */ 105 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 106 return (uint16_t)f; 107 } 108 109 uint64_t mask = MAKE_64BIT_MASK(16, 48); 110 111 if (likely((f & mask) == mask)) { 112 return (uint16_t)f; 113 } else { 114 return 0x7E00u; /* default qnan */ 115 } 116 } 117 118 #endif 119