1 /* 2 * QEMU RISC-V CPU -- internal functions and types 3 * 4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef RISCV_CPU_INTERNALS_H 20 #define RISCV_CPU_INTERNALS_H 21 22 #include "hw/registerfields.h" 23 24 /* 25 * The current MMU Modes are: 26 * - U 0b000 27 * - S 0b001 28 * - S+SUM 0b010 29 * - M 0b011 30 * - U+2STAGE 0b100 31 * - S+2STAGE 0b101 32 * - S+SUM+2STAGE 0b110 33 * - Shadow stack+U 0b1000 34 * - Shadow stack+S 0b1001 35 */ 36 #define MMUIdx_U 0 37 #define MMUIdx_S 1 38 #define MMUIdx_S_SUM 2 39 #define MMUIdx_M 3 40 #define MMU_2STAGE_BIT (1 << 2) 41 #define MMU_IDX_SS_WRITE (1 << 3) 42 43 static inline int mmuidx_priv(int mmu_idx) 44 { 45 int ret = mmu_idx & 3; 46 if (ret == MMUIdx_S_SUM) { 47 ret = PRV_S; 48 } 49 return ret; 50 } 51 52 static inline bool mmuidx_sum(int mmu_idx) 53 { 54 return (mmu_idx & 3) == MMUIdx_S_SUM; 55 } 56 57 static inline bool mmuidx_2stage(int mmu_idx) 58 { 59 return mmu_idx & MMU_2STAGE_BIT; 60 } 61 62 /* share data between vector helpers and decode code */ 63 FIELD(VDATA, VM, 0, 1) 64 FIELD(VDATA, LMUL, 1, 3) 65 FIELD(VDATA, VTA, 4, 1) 66 FIELD(VDATA, VTA_ALL_1S, 5, 1) 67 FIELD(VDATA, VMA, 6, 1) 68 FIELD(VDATA, NF, 7, 4) 69 FIELD(VDATA, WD, 7, 1) 70 71 /* float point classify helpers */ 72 target_ulong fclass_h(uint64_t frs1); 73 target_ulong fclass_s(uint64_t frs1); 74 target_ulong fclass_d(uint64_t frs1); 75 76 #ifndef CONFIG_USER_ONLY 77 extern const VMStateDescription vmstate_riscv_cpu; 78 #endif 79 80 enum { 81 RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */ 82 RISCV_FRM_RTZ = 1, /* Round towards Zero */ 83 RISCV_FRM_RDN = 2, /* Round Down */ 84 RISCV_FRM_RUP = 3, /* Round Up */ 85 RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ 86 RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ 87 RISCV_FRM_ROD = 8, /* Round to Odd */ 88 }; 89 90 static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) 91 { 92 /* the value is sign-extended instead of NaN-boxing for zfinx */ 93 if (env_archcpu(env)->cfg.ext_zfinx) { 94 return (int32_t)f; 95 } else { 96 return f | MAKE_64BIT_MASK(32, 32); 97 } 98 } 99 100 static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) 101 { 102 /* Disable NaN-boxing check when enable zfinx */ 103 if (env_archcpu(env)->cfg.ext_zfinx) { 104 return (uint32_t)f; 105 } 106 107 uint64_t mask = MAKE_64BIT_MASK(32, 32); 108 109 if (likely((f & mask) == mask)) { 110 return (uint32_t)f; 111 } else { 112 return 0x7fc00000u; /* default qnan */ 113 } 114 } 115 116 static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) 117 { 118 /* the value is sign-extended instead of NaN-boxing for zfinx */ 119 if (env_archcpu(env)->cfg.ext_zfinx) { 120 return (int16_t)f; 121 } else { 122 return f | MAKE_64BIT_MASK(16, 48); 123 } 124 } 125 126 static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) 127 { 128 /* Disable nanbox check when enable zfinx */ 129 if (env_archcpu(env)->cfg.ext_zfinx) { 130 return (uint16_t)f; 131 } 132 133 uint64_t mask = MAKE_64BIT_MASK(16, 48); 134 135 if (likely((f & mask) == mask)) { 136 return (uint16_t)f; 137 } else { 138 return 0x7E00u; /* default qnan */ 139 } 140 } 141 142 /* Our implementation of CPUClass::has_work */ 143 bool riscv_cpu_has_work(CPUState *cs); 144 145 #endif 146