1 /* 2 * QEMU RISC-V CPU -- internal functions and types 3 * 4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef RISCV_CPU_INTERNALS_H 20 #define RISCV_CPU_INTERNALS_H 21 22 #include "hw/registerfields.h" 23 24 /* 25 * The current MMU Modes are: 26 * - U 0b000 27 * - S 0b001 28 * - S+SUM 0b010 29 * - M 0b011 30 * - U+2STAGE 0b100 31 * - S+2STAGE 0b101 32 * - S+SUM+2STAGE 0b110 33 */ 34 #define MMUIdx_U 0 35 #define MMUIdx_S 1 36 #define MMUIdx_S_SUM 2 37 #define MMUIdx_M 3 38 #define MMU_2STAGE_BIT (1 << 2) 39 40 static inline bool mmuidx_sum(int mmu_idx) 41 { 42 return (mmu_idx & 3) == MMUIdx_S_SUM; 43 } 44 45 /* share data between vector helpers and decode code */ 46 FIELD(VDATA, VM, 0, 1) 47 FIELD(VDATA, LMUL, 1, 3) 48 FIELD(VDATA, VTA, 4, 1) 49 FIELD(VDATA, VTA_ALL_1S, 5, 1) 50 FIELD(VDATA, VMA, 6, 1) 51 FIELD(VDATA, NF, 7, 4) 52 FIELD(VDATA, WD, 7, 1) 53 54 /* float point classify helpers */ 55 target_ulong fclass_h(uint64_t frs1); 56 target_ulong fclass_s(uint64_t frs1); 57 target_ulong fclass_d(uint64_t frs1); 58 59 #ifndef CONFIG_USER_ONLY 60 extern const VMStateDescription vmstate_riscv_cpu; 61 #endif 62 63 enum { 64 RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */ 65 RISCV_FRM_RTZ = 1, /* Round towards Zero */ 66 RISCV_FRM_RDN = 2, /* Round Down */ 67 RISCV_FRM_RUP = 3, /* Round Up */ 68 RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ 69 RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ 70 RISCV_FRM_ROD = 8, /* Round to Odd */ 71 }; 72 73 static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) 74 { 75 /* the value is sign-extended instead of NaN-boxing for zfinx */ 76 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 77 return (int32_t)f; 78 } else { 79 return f | MAKE_64BIT_MASK(32, 32); 80 } 81 } 82 83 static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) 84 { 85 /* Disable NaN-boxing check when enable zfinx */ 86 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 87 return (uint32_t)f; 88 } 89 90 uint64_t mask = MAKE_64BIT_MASK(32, 32); 91 92 if (likely((f & mask) == mask)) { 93 return (uint32_t)f; 94 } else { 95 return 0x7fc00000u; /* default qnan */ 96 } 97 } 98 99 static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) 100 { 101 /* the value is sign-extended instead of NaN-boxing for zfinx */ 102 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 103 return (int16_t)f; 104 } else { 105 return f | MAKE_64BIT_MASK(16, 48); 106 } 107 } 108 109 static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) 110 { 111 /* Disable nanbox check when enable zfinx */ 112 if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 113 return (uint16_t)f; 114 } 115 116 uint64_t mask = MAKE_64BIT_MASK(16, 48); 117 118 if (likely((f & mask) == mask)) { 119 return (uint16_t)f; 120 } else { 121 return 0x7E00u; /* default qnan */ 122 } 123 } 124 125 #endif 126