1/*
2 * RISC-V translation routines for the Control-Flow Integrity Extension
3 *
4 * Copyright (c) 2024 Rivos Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.  If not, see <http://www.gnu.org/licenses/>.
17 */
18static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a)
19{
20    if (!ctx->bcfi_enabled) {
21        return false;
22    }
23
24    TCGv addr = tcg_temp_new();
25    TCGLabel *skip = gen_new_label();
26    uint32_t tmp = (get_xl(ctx) == MXL_RV64) ? 8 : 4;
27    TCGv data = tcg_temp_new();
28    tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
29    decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
30    tcg_gen_qemu_ld_tl(data, addr, SS_MMU_INDEX(ctx),
31                       mxl_memop(ctx) | MO_ALIGN);
32    TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
33    tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip);
34    tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_BCFI_TVAL),
35                  tcg_env, offsetof(CPURISCVState, sw_check_code));
36    gen_helper_raise_exception(tcg_env,
37                  tcg_constant_i32(RISCV_EXCP_SW_CHECK));
38    gen_set_label(skip);
39    tcg_gen_addi_tl(addr, addr, tmp);
40    tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
41
42    return true;
43}
44
45static bool trans_sspush(DisasContext *ctx, arg_sspush *a)
46{
47    if (!ctx->bcfi_enabled) {
48        return false;
49    }
50
51    TCGv addr = tcg_temp_new();
52    int tmp = (get_xl(ctx) == MXL_RV64) ? -8 : -4;
53    TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
54    decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
55    tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
56    tcg_gen_addi_tl(addr, addr, tmp);
57    tcg_gen_qemu_st_tl(data, addr, SS_MMU_INDEX(ctx),
58                       mxl_memop(ctx) | MO_ALIGN);
59    tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp));
60
61    return true;
62}
63
64static bool trans_ssrdp(DisasContext *ctx, arg_ssrdp *a)
65{
66    if (!ctx->bcfi_enabled || a->rd == 0) {
67        return false;
68    }
69
70    TCGv dest = dest_gpr(ctx, a->rd);
71    tcg_gen_ld_tl(dest, tcg_env, offsetof(CPURISCVState, ssp));
72    gen_set_gpr(ctx, a->rd, dest);
73
74    return true;
75}
76
77static bool trans_ssamoswap_w(DisasContext *ctx, arg_amoswap_w *a)
78{
79    REQUIRE_A_OR_ZAAMO(ctx);
80    if (!ctx->bcfi_enabled) {
81        return false;
82    }
83
84    TCGv dest = dest_gpr(ctx, a->rd);
85    TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
86
87    decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
88    src1 = get_address(ctx, a->rs1, 0);
89
90    tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx),
91                           (MO_ALIGN | MO_TESL));
92    gen_set_gpr(ctx, a->rd, dest);
93    return true;
94}
95
96static bool trans_ssamoswap_d(DisasContext *ctx, arg_amoswap_w *a)
97{
98    REQUIRE_64BIT(ctx);
99    REQUIRE_A_OR_ZAAMO(ctx);
100    if (!ctx->bcfi_enabled) {
101        return false;
102    }
103
104    TCGv dest = dest_gpr(ctx, a->rd);
105    TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
106
107    decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
108    src1 = get_address(ctx, a->rs1, 0);
109
110    tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx),
111                           (MO_ALIGN | MO_TESQ));
112    gen_set_gpr(ctx, a->rd, dest);
113    return true;
114}
115