1/*
2 * RISC-V translation routines for the RV64Zfh Standard Extension.
3 *
4 * Copyright (c) 2020 Chih-Min Chao, chihmin.chao@sifive.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.  If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#define REQUIRE_ZFH(ctx) do { \
20    if (!ctx->ext_zfh) {      \
21        return false;         \
22    }                         \
23} while (0)
24
25static bool trans_flh(DisasContext *ctx, arg_flh *a)
26{
27    TCGv_i64 dest;
28    TCGv t0;
29
30    REQUIRE_FPU;
31    REQUIRE_ZFH(ctx);
32
33    t0 = get_gpr(ctx, a->rs1, EXT_NONE);
34    if (a->imm) {
35        TCGv temp = temp_new(ctx);
36        tcg_gen_addi_tl(temp, t0, a->imm);
37        t0 = temp;
38    }
39
40    dest = cpu_fpr[a->rd];
41    tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TEUW);
42    gen_nanbox_h(dest, dest);
43
44    mark_fs_dirty(ctx);
45    return true;
46}
47
48static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
49{
50    TCGv t0;
51
52    REQUIRE_FPU;
53    REQUIRE_ZFH(ctx);
54
55    t0 = get_gpr(ctx, a->rs1, EXT_NONE);
56    if (a->imm) {
57        TCGv temp = tcg_temp_new();
58        tcg_gen_addi_tl(temp, t0, a->imm);
59        t0 = temp;
60    }
61
62    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW);
63
64    return true;
65}
66