1/*
2 * RISC-V translation routines for the RVV Standard Extension.
3 *
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.  If not, see <http://www.gnu.org/licenses/>.
17 */
18#include "tcg/tcg-op-gvec.h"
19#include "tcg/tcg-gvec-desc.h"
20#include "internals.h"
21
22static inline bool is_overlapped(const int8_t astart, int8_t asize,
23                                 const int8_t bstart, int8_t bsize)
24{
25    const int8_t aend = astart + asize;
26    const int8_t bend = bstart + bsize;
27
28    return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize;
29}
30
31static bool require_rvv(DisasContext *s)
32{
33    return s->mstatus_vs != 0;
34}
35
36static bool require_rvf(DisasContext *s)
37{
38    if (s->mstatus_fs == 0) {
39        return false;
40    }
41
42    switch (s->sew) {
43    case MO_16:
44    case MO_32:
45        return has_ext(s, RVF);
46    case MO_64:
47        return has_ext(s, RVD);
48    default:
49        return false;
50    }
51}
52
53static bool require_scale_rvf(DisasContext *s)
54{
55    if (s->mstatus_fs == 0) {
56        return false;
57    }
58
59    switch (s->sew) {
60    case MO_8:
61    case MO_16:
62        return has_ext(s, RVF);
63    case MO_32:
64        return has_ext(s, RVD);
65    default:
66        return false;
67    }
68}
69
70/* Destination vector register group cannot overlap source mask register. */
71static bool require_vm(int vm, int vd)
72{
73    return (vm != 0 || vd != 0);
74}
75
76static bool require_nf(int vd, int nf, int lmul)
77{
78    int size = nf << MAX(lmul, 0);
79    return size <= 8 && vd + size <= 32;
80}
81
82/*
83 * Vector register should aligned with the passed-in LMUL (EMUL).
84 * If LMUL < 0, i.e. fractional LMUL, any vector register is allowed.
85 */
86static bool require_align(const int8_t val, const int8_t lmul)
87{
88    return lmul <= 0 || extract32(val, 0, lmul) == 0;
89}
90
91/*
92 * A destination vector register group can overlap a source vector
93 * register group only if one of the following holds:
94 *  1. The destination EEW equals the source EEW.
95 *  2. The destination EEW is smaller than the source EEW and the overlap
96 *     is in the lowest-numbered part of the source register group.
97 *  3. The destination EEW is greater than the source EEW, the source EMUL
98 *     is at least 1, and the overlap is in the highest-numbered part of
99 *     the destination register group.
100 * (Section 5.2)
101 *
102 * This function returns true if one of the following holds:
103 *  * Destination vector register group does not overlap a source vector
104 *    register group.
105 *  * Rule 3 met.
106 * For rule 1, overlap is allowed so this function doesn't need to be called.
107 * For rule 2, (vd == vs). Caller has to check whether: (vd != vs) before
108 * calling this function.
109 */
110static bool require_noover(const int8_t dst, const int8_t dst_lmul,
111                           const int8_t src, const int8_t src_lmul)
112{
113    int8_t dst_size = dst_lmul <= 0 ? 1 : 1 << dst_lmul;
114    int8_t src_size = src_lmul <= 0 ? 1 : 1 << src_lmul;
115
116    /* Destination EEW is greater than the source EEW, check rule 3. */
117    if (dst_size > src_size) {
118        if (dst < src &&
119            src_lmul >= 0 &&
120            is_overlapped(dst, dst_size, src, src_size) &&
121            !is_overlapped(dst, dst_size, src + src_size, src_size)) {
122            return true;
123        }
124    }
125
126    return !is_overlapped(dst, dst_size, src, src_size);
127}
128
129static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
130{
131    TCGv s1, dst;
132
133    if (!require_rvv(s) || !has_ext(s, RVV)) {
134        return false;
135    }
136
137    dst = dest_gpr(s, rd);
138
139    if (rd == 0 && rs1 == 0) {
140        s1 = tcg_temp_new();
141        tcg_gen_mov_tl(s1, cpu_vl);
142    } else if (rs1 == 0) {
143        /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
144        s1 = tcg_constant_tl(RV_VLEN_MAX);
145    } else {
146        s1 = get_gpr(s, rs1, EXT_ZERO);
147    }
148
149    gen_helper_vsetvl(dst, cpu_env, s1, s2);
150    gen_set_gpr(s, rd, dst);
151    mark_vs_dirty(s);
152
153    tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
154    tcg_gen_lookup_and_goto_ptr();
155    s->base.is_jmp = DISAS_NORETURN;
156
157    if (rd == 0 && rs1 == 0) {
158        tcg_temp_free(s1);
159    }
160
161    return true;
162}
163
164static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
165{
166    TCGv s2 = get_gpr(s, a->rs2, EXT_ZERO);
167    return do_vsetvl(s, a->rd, a->rs1, s2);
168}
169
170static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a)
171{
172    TCGv s2 = tcg_constant_tl(a->zimm);
173    return do_vsetvl(s, a->rd, a->rs1, s2);
174}
175
176/* vector register offset from env */
177static uint32_t vreg_ofs(DisasContext *s, int reg)
178{
179    return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
180}
181
182/* check functions */
183
184/*
185 * Vector unit-stride, strided, unit-stride segment, strided segment
186 * store check function.
187 *
188 * Rules to be checked here:
189 *   1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3)
190 *   2. Destination vector register number is multiples of EMUL.
191 *      (Section 3.4.2, 7.3)
192 *   3. The EMUL setting must be such that EMUL * NFIELDS ≤ 8. (Section 7.8)
193 *   4. Vector register numbers accessed by the segment load or store
194 *      cannot increment past 31. (Section 7.8)
195 */
196static bool vext_check_store(DisasContext *s, int vd, int nf, uint8_t eew)
197{
198    int8_t emul = eew - s->sew + s->lmul;
199    return (emul >= -3 && emul <= 3) &&
200            require_align(vd, emul) &&
201            require_nf(vd, nf, emul);
202}
203
204/*
205 * Vector unit-stride, strided, unit-stride segment, strided segment
206 * load check function.
207 *
208 * Rules to be checked here:
209 *   1. All rules applies to store instructions are applies
210 *      to load instructions.
211 *   2. Destination vector register group for a masked vector
212 *      instruction cannot overlap the source mask register (v0).
213 *      (Section 5.3)
214 */
215static bool vext_check_load(DisasContext *s, int vd, int nf, int vm,
216                            uint8_t eew)
217{
218    return vext_check_store(s, vd, nf, eew) && require_vm(vm, vd);
219}
220
221/*
222 * Vector indexed, indexed segment store check function.
223 *
224 * Rules to be checked here:
225 *   1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3)
226 *   2. Index vector register number is multiples of EMUL.
227 *      (Section 3.4.2, 7.3)
228 *   3. Destination vector register number is multiples of LMUL.
229 *      (Section 3.4.2, 7.3)
230 *   4. The EMUL setting must be such that EMUL * NFIELDS ≤ 8. (Section 7.8)
231 *   5. Vector register numbers accessed by the segment load or store
232 *      cannot increment past 31. (Section 7.8)
233 */
234static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
235                                uint8_t eew)
236{
237    int8_t emul = eew - s->sew + s->lmul;
238    return (emul >= -3 && emul <= 3) &&
239            require_align(vs2, emul) &&
240            require_align(vd, s->lmul) &&
241            require_nf(vd, nf, s->lmul);
242}
243
244/*
245 * Vector indexed, indexed segment load check function.
246 *
247 * Rules to be checked here:
248 *   1. All rules applies to store instructions are applies
249 *      to load instructions.
250 *   2. Destination vector register group for a masked vector
251 *      instruction cannot overlap the source mask register (v0).
252 *      (Section 5.3)
253 *   3. Destination vector register cannot overlap a source vector
254 *      register (vs2) group.
255 *      (Section 5.2)
256 *   4. Destination vector register groups cannot overlap
257 *      the source vector register (vs2) group for
258 *      indexed segment load instructions. (Section 7.8.3)
259 */
260static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
261                                int nf, int vm, uint8_t eew)
262{
263    int8_t seg_vd;
264    int8_t emul = eew - s->sew + s->lmul;
265    bool ret = vext_check_st_index(s, vd, vs2, nf, eew) &&
266        require_vm(vm, vd);
267
268    /* Each segment register group has to follow overlap rules. */
269    for (int i = 0; i < nf; ++i) {
270        seg_vd = vd + (1 << MAX(s->lmul, 0)) * i;
271
272        if (eew > s->sew) {
273            if (seg_vd != vs2) {
274                ret &= require_noover(seg_vd, s->lmul, vs2, emul);
275            }
276        } else if (eew < s->sew) {
277            ret &= require_noover(seg_vd, s->lmul, vs2, emul);
278        }
279
280        /*
281         * Destination vector register groups cannot overlap
282         * the source vector register (vs2) group for
283         * indexed segment load instructions.
284         */
285        if (nf > 1) {
286            ret &= !is_overlapped(seg_vd, 1 << MAX(s->lmul, 0),
287                                  vs2, 1 << MAX(emul, 0));
288        }
289    }
290    return ret;
291}
292
293static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
294{
295    return require_vm(vm, vd) &&
296        require_align(vd, s->lmul) &&
297        require_align(vs, s->lmul);
298}
299
300/*
301 * Check function for vector instruction with format:
302 * single-width result and single-width sources (SEW = SEW op SEW)
303 *
304 * Rules to be checked here:
305 *   1. Destination vector register group for a masked vector
306 *      instruction cannot overlap the source mask register (v0).
307 *      (Section 5.3)
308 *   2. Destination vector register number is multiples of LMUL.
309 *      (Section 3.4.2)
310 *   3. Source (vs2, vs1) vector register number are multiples of LMUL.
311 *      (Section 3.4.2)
312 */
313static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
314{
315    return vext_check_ss(s, vd, vs2, vm) &&
316        require_align(vs1, s->lmul);
317}
318
319static bool vext_check_ms(DisasContext *s, int vd, int vs)
320{
321    bool ret = require_align(vs, s->lmul);
322    if (vd != vs) {
323        ret &= require_noover(vd, 0, vs, s->lmul);
324    }
325    return ret;
326}
327
328/*
329 * Check function for maskable vector instruction with format:
330 * single-width result and single-width sources (SEW = SEW op SEW)
331 *
332 * Rules to be checked here:
333 *   1. Source (vs2, vs1) vector register number are multiples of LMUL.
334 *      (Section 3.4.2)
335 *   2. Destination vector register cannot overlap a source vector
336 *      register (vs2, vs1) group.
337 *      (Section 5.2)
338 *   3. The destination vector register group for a masked vector
339 *      instruction cannot overlap the source mask register (v0),
340 *      unless the destination vector register is being written
341 *      with a mask value (e.g., comparisons) or the scalar result
342 *      of a reduction. (Section 5.3)
343 */
344static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2)
345{
346    bool ret = vext_check_ms(s, vd, vs2) &&
347        require_align(vs1, s->lmul);
348    if (vd != vs1) {
349        ret &= require_noover(vd, 0, vs1, s->lmul);
350    }
351    return ret;
352}
353
354/*
355 * Common check function for vector widening instructions
356 * of double-width result (2*SEW).
357 *
358 * Rules to be checked here:
359 *   1. The largest vector register group used by an instruction
360 *      can not be greater than 8 vector registers (Section 5.2):
361 *      => LMUL < 8.
362 *      => SEW < 64.
363 *   2. Destination vector register number is multiples of 2 * LMUL.
364 *      (Section 3.4.2)
365 *   3. Destination vector register group for a masked vector
366 *      instruction cannot overlap the source mask register (v0).
367 *      (Section 5.3)
368 */
369static bool vext_wide_check_common(DisasContext *s, int vd, int vm)
370{
371    return (s->lmul <= 2) &&
372           (s->sew < MO_64) &&
373           require_align(vd, s->lmul + 1) &&
374           require_vm(vm, vd);
375}
376
377/*
378 * Common check function for vector narrowing instructions
379 * of single-width result (SEW) and double-width source (2*SEW).
380 *
381 * Rules to be checked here:
382 *   1. The largest vector register group used by an instruction
383 *      can not be greater than 8 vector registers (Section 5.2):
384 *      => LMUL < 8.
385 *      => SEW < 64.
386 *   2. Source vector register number is multiples of 2 * LMUL.
387 *      (Section 3.4.2)
388 *   3. Destination vector register number is multiples of LMUL.
389 *      (Section 3.4.2)
390 *   4. Destination vector register group for a masked vector
391 *      instruction cannot overlap the source mask register (v0).
392 *      (Section 5.3)
393 */
394static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2,
395                                     int vm)
396{
397    return (s->lmul <= 2) &&
398           (s->sew < MO_64) &&
399           require_align(vs2, s->lmul + 1) &&
400           require_align(vd, s->lmul) &&
401           require_vm(vm, vd);
402}
403
404static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm)
405{
406    return vext_wide_check_common(s, vd, vm) &&
407        require_align(vs, s->lmul) &&
408        require_noover(vd, s->lmul + 1, vs, s->lmul);
409}
410
411static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
412{
413    return vext_wide_check_common(s, vd, vm) &&
414        require_align(vs, s->lmul + 1);
415}
416
417/*
418 * Check function for vector instruction with format:
419 * double-width result and single-width sources (2*SEW = SEW op SEW)
420 *
421 * Rules to be checked here:
422 *   1. All rules in defined in widen common rules are applied.
423 *   2. Source (vs2, vs1) vector register number are multiples of LMUL.
424 *      (Section 3.4.2)
425 *   3. Destination vector register cannot overlap a source vector
426 *      register (vs2, vs1) group.
427 *      (Section 5.2)
428 */
429static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
430{
431    return vext_check_ds(s, vd, vs2, vm) &&
432        require_align(vs1, s->lmul) &&
433        require_noover(vd, s->lmul + 1, vs1, s->lmul);
434}
435
436/*
437 * Check function for vector instruction with format:
438 * double-width result and double-width source1 and single-width
439 * source2 (2*SEW = 2*SEW op SEW)
440 *
441 * Rules to be checked here:
442 *   1. All rules in defined in widen common rules are applied.
443 *   2. Source 1 (vs2) vector register number is multiples of 2 * LMUL.
444 *      (Section 3.4.2)
445 *   3. Source 2 (vs1) vector register number is multiples of LMUL.
446 *      (Section 3.4.2)
447 *   4. Destination vector register cannot overlap a source vector
448 *      register (vs1) group.
449 *      (Section 5.2)
450 */
451static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
452{
453    return vext_check_ds(s, vd, vs1, vm) &&
454        require_align(vs2, s->lmul + 1);
455}
456
457static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
458{
459    bool ret = vext_narrow_check_common(s, vd, vs, vm);
460    if (vd != vs) {
461        ret &= require_noover(vd, s->lmul, vs, s->lmul + 1);
462    }
463    return ret;
464}
465
466/*
467 * Check function for vector instruction with format:
468 * single-width result and double-width source 1 and single-width
469 * source 2 (SEW = 2*SEW op SEW)
470 *
471 * Rules to be checked here:
472 *   1. All rules in defined in narrow common rules are applied.
473 *   2. Destination vector register cannot overlap a source vector
474 *      register (vs2) group.
475 *      (Section 5.2)
476 *   3. Source 2 (vs1) vector register number is multiples of LMUL.
477 *      (Section 3.4.2)
478 */
479static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
480{
481    return vext_check_sd(s, vd, vs2, vm) &&
482        require_align(vs1, s->lmul);
483}
484
485/*
486 * Check function for vector reduction instructions.
487 *
488 * Rules to be checked here:
489 *   1. Source 1 (vs2) vector register number is multiples of LMUL.
490 *      (Section 3.4.2)
491 */
492static bool vext_check_reduction(DisasContext *s, int vs2)
493{
494    return require_align(vs2, s->lmul);
495}
496
497/*
498 * Check function for vector slide instructions.
499 *
500 * Rules to be checked here:
501 *   1. Source 1 (vs2) vector register number is multiples of LMUL.
502 *      (Section 3.4.2)
503 *   2. Destination vector register number is multiples of LMUL.
504 *      (Section 3.4.2)
505 *   3. Destination vector register group for a masked vector
506 *      instruction cannot overlap the source mask register (v0).
507 *      (Section 5.3)
508 *   4. The destination vector register group for vslideup, vslide1up,
509 *      vfslide1up, cannot overlap the source vector register (vs2) group.
510 *      (Section 5.2, 16.3.1, 16.3.3)
511 */
512static bool vext_check_slide(DisasContext *s, int vd, int vs2,
513                             int vm, bool is_over)
514{
515    bool ret = require_align(vs2, s->lmul) &&
516               require_align(vd, s->lmul) &&
517               require_vm(vm, vd);
518    if (is_over) {
519        ret &= (vd != vs2);
520    }
521    return ret;
522}
523
524/*
525 * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
526 * So RVV is also be checked in this function.
527 */
528static bool vext_check_isa_ill(DisasContext *s)
529{
530    return !s->vill;
531}
532
533/* common translation macro */
534#define GEN_VEXT_TRANS(NAME, EEW, ARGTYPE, OP, CHECK)        \
535static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \
536{                                                            \
537    if (CHECK(s, a, EEW)) {                                  \
538        return OP(s, a, EEW);                                \
539    }                                                        \
540    return false;                                            \
541}
542
543static uint8_t vext_get_emul(DisasContext *s, uint8_t eew)
544{
545    int8_t emul = eew - s->sew + s->lmul;
546    return emul < 0 ? 0 : emul;
547}
548
549/*
550 *** unit stride load and store
551 */
552typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv,
553                                TCGv_env, TCGv_i32);
554
555static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
556                          gen_helper_ldst_us *fn, DisasContext *s,
557                          bool is_store)
558{
559    TCGv_ptr dest, mask;
560    TCGv base;
561    TCGv_i32 desc;
562
563    TCGLabel *over = gen_new_label();
564    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
565
566    dest = tcg_temp_new_ptr();
567    mask = tcg_temp_new_ptr();
568    base = get_gpr(s, rs1, EXT_NONE);
569
570    /*
571     * As simd_desc supports at most 256 bytes, and in this implementation,
572     * the max vector group length is 2048 bytes. So split it into two parts.
573     *
574     * The first part is vlen in bytes, encoded in maxsz of simd_desc.
575     * The second part is lmul, encoded in data of simd_desc.
576     */
577    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
578
579    tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
580    tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
581
582    fn(dest, mask, base, cpu_env, desc);
583
584    tcg_temp_free_ptr(dest);
585    tcg_temp_free_ptr(mask);
586
587    if (!is_store) {
588        mark_vs_dirty(s);
589    }
590
591    gen_set_label(over);
592    return true;
593}
594
595static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
596{
597    uint32_t data = 0;
598    gen_helper_ldst_us *fn;
599    static gen_helper_ldst_us * const fns[2][4] = {
600        /* masked unit stride load */
601        { gen_helper_vle8_v_mask, gen_helper_vle16_v_mask,
602          gen_helper_vle32_v_mask, gen_helper_vle64_v_mask },
603        /* unmasked unit stride load */
604        { gen_helper_vle8_v, gen_helper_vle16_v,
605          gen_helper_vle32_v, gen_helper_vle64_v }
606    };
607
608    fn =  fns[a->vm][eew];
609    if (fn == NULL) {
610        return false;
611    }
612
613    /*
614     * Vector load/store instructions have the EEW encoded
615     * directly in the instructions. The maximum vector size is
616     * calculated with EMUL rather than LMUL.
617     */
618    uint8_t emul = vext_get_emul(s, eew);
619    data = FIELD_DP32(data, VDATA, VM, a->vm);
620    data = FIELD_DP32(data, VDATA, LMUL, emul);
621    data = FIELD_DP32(data, VDATA, NF, a->nf);
622    return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
623}
624
625static bool ld_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew)
626{
627    return require_rvv(s) &&
628           vext_check_isa_ill(s) &&
629           vext_check_load(s, a->rd, a->nf, a->vm, eew);
630}
631
632GEN_VEXT_TRANS(vle8_v,  MO_8,  r2nfvm, ld_us_op, ld_us_check)
633GEN_VEXT_TRANS(vle16_v, MO_16, r2nfvm, ld_us_op, ld_us_check)
634GEN_VEXT_TRANS(vle32_v, MO_32, r2nfvm, ld_us_op, ld_us_check)
635GEN_VEXT_TRANS(vle64_v, MO_64, r2nfvm, ld_us_op, ld_us_check)
636
637static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
638{
639    uint32_t data = 0;
640    gen_helper_ldst_us *fn;
641    static gen_helper_ldst_us * const fns[2][4] = {
642        /* masked unit stride store */
643        { gen_helper_vse8_v_mask, gen_helper_vse16_v_mask,
644          gen_helper_vse32_v_mask, gen_helper_vse64_v_mask },
645        /* unmasked unit stride store */
646        { gen_helper_vse8_v, gen_helper_vse16_v,
647          gen_helper_vse32_v, gen_helper_vse64_v }
648    };
649
650    fn =  fns[a->vm][eew];
651    if (fn == NULL) {
652        return false;
653    }
654
655    uint8_t emul = vext_get_emul(s, eew);
656    data = FIELD_DP32(data, VDATA, VM, a->vm);
657    data = FIELD_DP32(data, VDATA, LMUL, emul);
658    data = FIELD_DP32(data, VDATA, NF, a->nf);
659    return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
660}
661
662static bool st_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew)
663{
664    return require_rvv(s) &&
665           vext_check_isa_ill(s) &&
666           vext_check_store(s, a->rd, a->nf, eew);
667}
668
669GEN_VEXT_TRANS(vse8_v,  MO_8,  r2nfvm, st_us_op, st_us_check)
670GEN_VEXT_TRANS(vse16_v, MO_16, r2nfvm, st_us_op, st_us_check)
671GEN_VEXT_TRANS(vse32_v, MO_32, r2nfvm, st_us_op, st_us_check)
672GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check)
673
674/*
675 *** stride load and store
676 */
677typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
678                                    TCGv, TCGv_env, TCGv_i32);
679
680static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
681                              uint32_t data, gen_helper_ldst_stride *fn,
682                              DisasContext *s, bool is_store)
683{
684    TCGv_ptr dest, mask;
685    TCGv base, stride;
686    TCGv_i32 desc;
687
688    TCGLabel *over = gen_new_label();
689    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
690
691    dest = tcg_temp_new_ptr();
692    mask = tcg_temp_new_ptr();
693    base = get_gpr(s, rs1, EXT_NONE);
694    stride = get_gpr(s, rs2, EXT_NONE);
695    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
696
697    tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
698    tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
699
700    fn(dest, mask, base, stride, cpu_env, desc);
701
702    tcg_temp_free_ptr(dest);
703    tcg_temp_free_ptr(mask);
704
705    if (!is_store) {
706        mark_vs_dirty(s);
707    }
708
709    gen_set_label(over);
710    return true;
711}
712
713static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
714{
715    uint32_t data = 0;
716    gen_helper_ldst_stride *fn;
717    static gen_helper_ldst_stride * const fns[4] = {
718        gen_helper_vlse8_v, gen_helper_vlse16_v,
719        gen_helper_vlse32_v, gen_helper_vlse64_v
720    };
721
722    fn = fns[eew];
723    if (fn == NULL) {
724        return false;
725    }
726
727    uint8_t emul = vext_get_emul(s, eew);
728    data = FIELD_DP32(data, VDATA, VM, a->vm);
729    data = FIELD_DP32(data, VDATA, LMUL, emul);
730    data = FIELD_DP32(data, VDATA, NF, a->nf);
731    return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
732}
733
734static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
735{
736    return require_rvv(s) &&
737           vext_check_isa_ill(s) &&
738           vext_check_load(s, a->rd, a->nf, a->vm, eew);
739}
740
741GEN_VEXT_TRANS(vlse8_v,  MO_8,  rnfvm, ld_stride_op, ld_stride_check)
742GEN_VEXT_TRANS(vlse16_v, MO_16, rnfvm, ld_stride_op, ld_stride_check)
743GEN_VEXT_TRANS(vlse32_v, MO_32, rnfvm, ld_stride_op, ld_stride_check)
744GEN_VEXT_TRANS(vlse64_v, MO_64, rnfvm, ld_stride_op, ld_stride_check)
745
746static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
747{
748    uint32_t data = 0;
749    gen_helper_ldst_stride *fn;
750    static gen_helper_ldst_stride * const fns[4] = {
751        /* masked stride store */
752        gen_helper_vsse8_v,  gen_helper_vsse16_v,
753        gen_helper_vsse32_v,  gen_helper_vsse64_v
754    };
755
756    uint8_t emul = vext_get_emul(s, eew);
757    data = FIELD_DP32(data, VDATA, VM, a->vm);
758    data = FIELD_DP32(data, VDATA, LMUL, emul);
759    data = FIELD_DP32(data, VDATA, NF, a->nf);
760    fn = fns[eew];
761    if (fn == NULL) {
762        return false;
763    }
764
765    return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
766}
767
768static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
769{
770    return require_rvv(s) &&
771           vext_check_isa_ill(s) &&
772           vext_check_store(s, a->rd, a->nf, eew);
773}
774
775GEN_VEXT_TRANS(vsse8_v,  MO_8,  rnfvm, st_stride_op, st_stride_check)
776GEN_VEXT_TRANS(vsse16_v, MO_16, rnfvm, st_stride_op, st_stride_check)
777GEN_VEXT_TRANS(vsse32_v, MO_32, rnfvm, st_stride_op, st_stride_check)
778GEN_VEXT_TRANS(vsse64_v, MO_64, rnfvm, st_stride_op, st_stride_check)
779
780/*
781 *** index load and store
782 */
783typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
784                                   TCGv_ptr, TCGv_env, TCGv_i32);
785
786static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
787                             uint32_t data, gen_helper_ldst_index *fn,
788                             DisasContext *s, bool is_store)
789{
790    TCGv_ptr dest, mask, index;
791    TCGv base;
792    TCGv_i32 desc;
793
794    TCGLabel *over = gen_new_label();
795    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
796
797    dest = tcg_temp_new_ptr();
798    mask = tcg_temp_new_ptr();
799    index = tcg_temp_new_ptr();
800    base = get_gpr(s, rs1, EXT_NONE);
801    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
802
803    tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
804    tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
805    tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
806
807    fn(dest, mask, base, index, cpu_env, desc);
808
809    tcg_temp_free_ptr(dest);
810    tcg_temp_free_ptr(mask);
811    tcg_temp_free_ptr(index);
812
813    if (!is_store) {
814        mark_vs_dirty(s);
815    }
816
817    gen_set_label(over);
818    return true;
819}
820
821static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
822{
823    uint32_t data = 0;
824    gen_helper_ldst_index *fn;
825    static gen_helper_ldst_index * const fns[4][4] = {
826        /*
827         * offset vector register group EEW = 8,
828         * data vector register group EEW = SEW
829         */
830        { gen_helper_vlxei8_8_v,  gen_helper_vlxei8_16_v,
831          gen_helper_vlxei8_32_v, gen_helper_vlxei8_64_v },
832        /*
833         * offset vector register group EEW = 16,
834         * data vector register group EEW = SEW
835         */
836        { gen_helper_vlxei16_8_v, gen_helper_vlxei16_16_v,
837          gen_helper_vlxei16_32_v, gen_helper_vlxei16_64_v },
838        /*
839         * offset vector register group EEW = 32,
840         * data vector register group EEW = SEW
841         */
842        { gen_helper_vlxei32_8_v, gen_helper_vlxei32_16_v,
843          gen_helper_vlxei32_32_v, gen_helper_vlxei32_64_v },
844        /*
845         * offset vector register group EEW = 64,
846         * data vector register group EEW = SEW
847         */
848        { gen_helper_vlxei64_8_v, gen_helper_vlxei64_16_v,
849          gen_helper_vlxei64_32_v, gen_helper_vlxei64_64_v }
850    };
851
852    fn = fns[eew][s->sew];
853
854    uint8_t emul = vext_get_emul(s, s->sew);
855    data = FIELD_DP32(data, VDATA, VM, a->vm);
856    data = FIELD_DP32(data, VDATA, LMUL, emul);
857    data = FIELD_DP32(data, VDATA, NF, a->nf);
858    return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
859}
860
861static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
862{
863    return require_rvv(s) &&
864           vext_check_isa_ill(s) &&
865           vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew);
866}
867
868GEN_VEXT_TRANS(vlxei8_v,  MO_8,  rnfvm, ld_index_op, ld_index_check)
869GEN_VEXT_TRANS(vlxei16_v, MO_16, rnfvm, ld_index_op, ld_index_check)
870GEN_VEXT_TRANS(vlxei32_v, MO_32, rnfvm, ld_index_op, ld_index_check)
871GEN_VEXT_TRANS(vlxei64_v, MO_64, rnfvm, ld_index_op, ld_index_check)
872
873static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
874{
875    uint32_t data = 0;
876    gen_helper_ldst_index *fn;
877    static gen_helper_ldst_index * const fns[4][4] = {
878        /*
879         * offset vector register group EEW = 8,
880         * data vector register group EEW = SEW
881         */
882        { gen_helper_vsxei8_8_v,  gen_helper_vsxei8_16_v,
883          gen_helper_vsxei8_32_v, gen_helper_vsxei8_64_v },
884        /*
885         * offset vector register group EEW = 16,
886         * data vector register group EEW = SEW
887         */
888        { gen_helper_vsxei16_8_v, gen_helper_vsxei16_16_v,
889          gen_helper_vsxei16_32_v, gen_helper_vsxei16_64_v },
890        /*
891         * offset vector register group EEW = 32,
892         * data vector register group EEW = SEW
893         */
894        { gen_helper_vsxei32_8_v, gen_helper_vsxei32_16_v,
895          gen_helper_vsxei32_32_v, gen_helper_vsxei32_64_v },
896        /*
897         * offset vector register group EEW = 64,
898         * data vector register group EEW = SEW
899         */
900        { gen_helper_vsxei64_8_v, gen_helper_vsxei64_16_v,
901          gen_helper_vsxei64_32_v, gen_helper_vsxei64_64_v }
902    };
903
904    fn = fns[eew][s->sew];
905
906    uint8_t emul = vext_get_emul(s, s->sew);
907    data = FIELD_DP32(data, VDATA, VM, a->vm);
908    data = FIELD_DP32(data, VDATA, LMUL, emul);
909    data = FIELD_DP32(data, VDATA, NF, a->nf);
910    return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
911}
912
913static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
914{
915    return require_rvv(s) &&
916           vext_check_isa_ill(s) &&
917           vext_check_st_index(s, a->rd, a->rs2, a->nf, eew);
918}
919
920GEN_VEXT_TRANS(vsxei8_v,  MO_8,  rnfvm, st_index_op, st_index_check)
921GEN_VEXT_TRANS(vsxei16_v, MO_16, rnfvm, st_index_op, st_index_check)
922GEN_VEXT_TRANS(vsxei32_v, MO_32, rnfvm, st_index_op, st_index_check)
923GEN_VEXT_TRANS(vsxei64_v, MO_64, rnfvm, st_index_op, st_index_check)
924
925/*
926 *** unit stride fault-only-first load
927 */
928static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
929                       gen_helper_ldst_us *fn, DisasContext *s)
930{
931    TCGv_ptr dest, mask;
932    TCGv base;
933    TCGv_i32 desc;
934
935    TCGLabel *over = gen_new_label();
936    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
937
938    dest = tcg_temp_new_ptr();
939    mask = tcg_temp_new_ptr();
940    base = get_gpr(s, rs1, EXT_NONE);
941    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
942
943    tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
944    tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
945
946    fn(dest, mask, base, cpu_env, desc);
947
948    tcg_temp_free_ptr(dest);
949    tcg_temp_free_ptr(mask);
950    mark_vs_dirty(s);
951    gen_set_label(over);
952    return true;
953}
954
955static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
956{
957    uint32_t data = 0;
958    gen_helper_ldst_us *fn;
959    static gen_helper_ldst_us * const fns[4] = {
960        gen_helper_vle8ff_v, gen_helper_vle16ff_v,
961        gen_helper_vle32ff_v, gen_helper_vle64ff_v
962    };
963
964    fn = fns[eew];
965    if (fn == NULL) {
966        return false;
967    }
968
969    uint8_t emul = vext_get_emul(s, eew);
970    data = FIELD_DP32(data, VDATA, VM, a->vm);
971    data = FIELD_DP32(data, VDATA, LMUL, emul);
972    data = FIELD_DP32(data, VDATA, NF, a->nf);
973    return ldff_trans(a->rd, a->rs1, data, fn, s);
974}
975
976GEN_VEXT_TRANS(vle8ff_v,  MO_8,  r2nfvm, ldff_op, ld_us_check)
977GEN_VEXT_TRANS(vle16ff_v, MO_16, r2nfvm, ldff_op, ld_us_check)
978GEN_VEXT_TRANS(vle32ff_v, MO_32, r2nfvm, ldff_op, ld_us_check)
979GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check)
980
981/*
982 * load and store whole register instructions
983 */
984typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
985
986static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
987                             gen_helper_ldst_whole *fn, DisasContext *s,
988                             bool is_store)
989{
990    TCGv_ptr dest;
991    TCGv base;
992    TCGv_i32 desc;
993
994    uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
995    dest = tcg_temp_new_ptr();
996    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
997
998    base = get_gpr(s, rs1, EXT_NONE);
999    tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
1000
1001    fn(dest, base, cpu_env, desc);
1002
1003    tcg_temp_free_ptr(dest);
1004
1005    if (!is_store) {
1006        mark_vs_dirty(s);
1007    }
1008
1009    return true;
1010}
1011
1012/*
1013 * load and store whole register instructions ignore vtype and vl setting.
1014 * Thus, we don't need to check vill bit. (Section 7.9)
1015 */
1016#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, IS_STORE)                      \
1017static bool trans_##NAME(DisasContext *s, arg_##NAME * a)                 \
1018{                                                                         \
1019    if (require_rvv(s) &&                                                 \
1020        QEMU_IS_ALIGNED(a->rd, ARG_NF)) {                                 \
1021        return ldst_whole_trans(a->rd, a->rs1, ARG_NF, gen_helper_##NAME, \
1022                                s, IS_STORE);                             \
1023    }                                                                     \
1024    return false;                                                         \
1025}
1026
1027GEN_LDST_WHOLE_TRANS(vl1re8_v,  1, false)
1028GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, false)
1029GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, false)
1030GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, false)
1031GEN_LDST_WHOLE_TRANS(vl2re8_v,  2, false)
1032GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, false)
1033GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, false)
1034GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, false)
1035GEN_LDST_WHOLE_TRANS(vl4re8_v,  4, false)
1036GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, false)
1037GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, false)
1038GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, false)
1039GEN_LDST_WHOLE_TRANS(vl8re8_v,  8, false)
1040GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, false)
1041GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, false)
1042GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, false)
1043
1044GEN_LDST_WHOLE_TRANS(vs1r_v, 1, true)
1045GEN_LDST_WHOLE_TRANS(vs2r_v, 2, true)
1046GEN_LDST_WHOLE_TRANS(vs4r_v, 4, true)
1047GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
1048
1049/*
1050 *** Vector Integer Arithmetic Instructions
1051 */
1052#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
1053
1054static bool opivv_check(DisasContext *s, arg_rmrr *a)
1055{
1056    return require_rvv(s) &&
1057           vext_check_isa_ill(s) &&
1058           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
1059}
1060
1061typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
1062                        uint32_t, uint32_t, uint32_t);
1063
1064static inline bool
1065do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
1066              gen_helper_gvec_4_ptr *fn)
1067{
1068    TCGLabel *over = gen_new_label();
1069    if (!opivv_check(s, a)) {
1070        return false;
1071    }
1072
1073    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1074
1075    if (a->vm && s->vl_eq_vlmax) {
1076        gvec_fn(s->sew, vreg_ofs(s, a->rd),
1077                vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
1078                MAXSZ(s), MAXSZ(s));
1079    } else {
1080        uint32_t data = 0;
1081
1082        data = FIELD_DP32(data, VDATA, VM, a->vm);
1083        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1084        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
1085                           vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
1086                           cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
1087    }
1088    mark_vs_dirty(s);
1089    gen_set_label(over);
1090    return true;
1091}
1092
1093/* OPIVV with GVEC IR */
1094#define GEN_OPIVV_GVEC_TRANS(NAME, SUF) \
1095static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
1096{                                                                  \
1097    static gen_helper_gvec_4_ptr * const fns[4] = {                \
1098        gen_helper_##NAME##_b, gen_helper_##NAME##_h,              \
1099        gen_helper_##NAME##_w, gen_helper_##NAME##_d,              \
1100    };                                                             \
1101    return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]);   \
1102}
1103
1104GEN_OPIVV_GVEC_TRANS(vadd_vv, add)
1105GEN_OPIVV_GVEC_TRANS(vsub_vv, sub)
1106
1107typedef void gen_helper_opivx(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
1108                              TCGv_env, TCGv_i32);
1109
1110static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
1111                        gen_helper_opivx *fn, DisasContext *s)
1112{
1113    TCGv_ptr dest, src2, mask;
1114    TCGv src1;
1115    TCGv_i32 desc;
1116    uint32_t data = 0;
1117
1118    TCGLabel *over = gen_new_label();
1119    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1120
1121    dest = tcg_temp_new_ptr();
1122    mask = tcg_temp_new_ptr();
1123    src2 = tcg_temp_new_ptr();
1124    src1 = get_gpr(s, rs1, EXT_NONE);
1125
1126    data = FIELD_DP32(data, VDATA, VM, vm);
1127    data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1128    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
1129
1130    tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
1131    tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
1132    tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
1133
1134    fn(dest, mask, src1, src2, cpu_env, desc);
1135
1136    tcg_temp_free_ptr(dest);
1137    tcg_temp_free_ptr(mask);
1138    tcg_temp_free_ptr(src2);
1139    mark_vs_dirty(s);
1140    gen_set_label(over);
1141    return true;
1142}
1143
1144static bool opivx_check(DisasContext *s, arg_rmrr *a)
1145{
1146    return require_rvv(s) &&
1147           vext_check_isa_ill(s) &&
1148           vext_check_ss(s, a->rd, a->rs2, a->vm);
1149}
1150
1151typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64,
1152                         uint32_t, uint32_t);
1153
1154static inline bool
1155do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
1156              gen_helper_opivx *fn)
1157{
1158    if (!opivx_check(s, a)) {
1159        return false;
1160    }
1161
1162    if (a->vm && s->vl_eq_vlmax) {
1163        TCGv_i64 src1 = tcg_temp_new_i64();
1164
1165        tcg_gen_ext_tl_i64(src1, get_gpr(s, a->rs1, EXT_SIGN));
1166        gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
1167                src1, MAXSZ(s), MAXSZ(s));
1168
1169        tcg_temp_free_i64(src1);
1170        mark_vs_dirty(s);
1171        return true;
1172    }
1173    return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
1174}
1175
1176/* OPIVX with GVEC IR */
1177#define GEN_OPIVX_GVEC_TRANS(NAME, SUF) \
1178static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
1179{                                                                  \
1180    static gen_helper_opivx * const fns[4] = {                     \
1181        gen_helper_##NAME##_b, gen_helper_##NAME##_h,              \
1182        gen_helper_##NAME##_w, gen_helper_##NAME##_d,              \
1183    };                                                             \
1184    return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]);   \
1185}
1186
1187GEN_OPIVX_GVEC_TRANS(vadd_vx, adds)
1188GEN_OPIVX_GVEC_TRANS(vsub_vx, subs)
1189
1190static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1191{
1192    tcg_gen_vec_sub8_i64(d, b, a);
1193}
1194
1195static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
1196{
1197    tcg_gen_vec_sub16_i64(d, b, a);
1198}
1199
1200static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1201{
1202    tcg_gen_sub_i32(ret, arg2, arg1);
1203}
1204
1205static void gen_rsub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1206{
1207    tcg_gen_sub_i64(ret, arg2, arg1);
1208}
1209
1210static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
1211{
1212    tcg_gen_sub_vec(vece, r, b, a);
1213}
1214
1215static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
1216                               TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
1217{
1218    static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
1219    static const GVecGen2s rsub_op[4] = {
1220        { .fni8 = gen_vec_rsub8_i64,
1221          .fniv = gen_rsub_vec,
1222          .fno = gen_helper_vec_rsubs8,
1223          .opt_opc = vecop_list,
1224          .vece = MO_8 },
1225        { .fni8 = gen_vec_rsub16_i64,
1226          .fniv = gen_rsub_vec,
1227          .fno = gen_helper_vec_rsubs16,
1228          .opt_opc = vecop_list,
1229          .vece = MO_16 },
1230        { .fni4 = gen_rsub_i32,
1231          .fniv = gen_rsub_vec,
1232          .fno = gen_helper_vec_rsubs32,
1233          .opt_opc = vecop_list,
1234          .vece = MO_32 },
1235        { .fni8 = gen_rsub_i64,
1236          .fniv = gen_rsub_vec,
1237          .fno = gen_helper_vec_rsubs64,
1238          .opt_opc = vecop_list,
1239          .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1240          .vece = MO_64 },
1241    };
1242
1243    tcg_debug_assert(vece <= MO_64);
1244    tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]);
1245}
1246
1247GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs)
1248
1249typedef enum {
1250    IMM_ZX,         /* Zero-extended */
1251    IMM_SX,         /* Sign-extended */
1252    IMM_TRUNC_SEW,  /* Truncate to log(SEW) bits */
1253    IMM_TRUNC_2SEW, /* Truncate to log(2*SEW) bits */
1254} imm_mode_t;
1255
1256static int64_t extract_imm(DisasContext *s, uint32_t imm, imm_mode_t imm_mode)
1257{
1258    switch (imm_mode) {
1259    case IMM_ZX:
1260        return extract64(imm, 0, 5);
1261    case IMM_SX:
1262        return sextract64(imm, 0, 5);
1263    case IMM_TRUNC_SEW:
1264        return extract64(imm, 0, s->sew + 3);
1265    case IMM_TRUNC_2SEW:
1266        return extract64(imm, 0, s->sew + 4);
1267    default:
1268        g_assert_not_reached();
1269    }
1270}
1271
1272static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
1273                        gen_helper_opivx *fn, DisasContext *s,
1274                        imm_mode_t imm_mode)
1275{
1276    TCGv_ptr dest, src2, mask;
1277    TCGv src1;
1278    TCGv_i32 desc;
1279    uint32_t data = 0;
1280
1281    TCGLabel *over = gen_new_label();
1282    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1283
1284    dest = tcg_temp_new_ptr();
1285    mask = tcg_temp_new_ptr();
1286    src2 = tcg_temp_new_ptr();
1287    src1 = tcg_constant_tl(extract_imm(s, imm, imm_mode));
1288
1289    data = FIELD_DP32(data, VDATA, VM, vm);
1290    data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1291    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
1292
1293    tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
1294    tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
1295    tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
1296
1297    fn(dest, mask, src1, src2, cpu_env, desc);
1298
1299    tcg_temp_free_ptr(dest);
1300    tcg_temp_free_ptr(mask);
1301    tcg_temp_free_ptr(src2);
1302    mark_vs_dirty(s);
1303    gen_set_label(over);
1304    return true;
1305}
1306
1307typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
1308                         uint32_t, uint32_t);
1309
1310static inline bool
1311do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
1312              gen_helper_opivx *fn, imm_mode_t imm_mode)
1313{
1314    if (!opivx_check(s, a)) {
1315        return false;
1316    }
1317
1318    if (a->vm && s->vl_eq_vlmax) {
1319        gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
1320                extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s));
1321        mark_vs_dirty(s);
1322        return true;
1323    }
1324    return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, imm_mode);
1325}
1326
1327/* OPIVI with GVEC IR */
1328#define GEN_OPIVI_GVEC_TRANS(NAME, IMM_MODE, OPIVX, SUF) \
1329static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
1330{                                                                  \
1331    static gen_helper_opivx * const fns[4] = {                     \
1332        gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h,            \
1333        gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d,            \
1334    };                                                             \
1335    return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF,                 \
1336                         fns[s->sew], IMM_MODE);                   \
1337}
1338
1339GEN_OPIVI_GVEC_TRANS(vadd_vi, IMM_SX, vadd_vx, addi)
1340
1341static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
1342                               int64_t c, uint32_t oprsz, uint32_t maxsz)
1343{
1344    TCGv_i64 tmp = tcg_constant_i64(c);
1345    tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz);
1346}
1347
1348GEN_OPIVI_GVEC_TRANS(vrsub_vi, IMM_SX, vrsub_vx, rsubi)
1349
1350/* Vector Widening Integer Add/Subtract */
1351
1352/* OPIVV with WIDEN */
1353static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
1354{
1355    return require_rvv(s) &&
1356           vext_check_isa_ill(s) &&
1357           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
1358}
1359
1360static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
1361                           gen_helper_gvec_4_ptr *fn,
1362                           bool (*checkfn)(DisasContext *, arg_rmrr *))
1363{
1364    if (checkfn(s, a)) {
1365        uint32_t data = 0;
1366        TCGLabel *over = gen_new_label();
1367        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1368
1369        data = FIELD_DP32(data, VDATA, VM, a->vm);
1370        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1371        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
1372                           vreg_ofs(s, a->rs1),
1373                           vreg_ofs(s, a->rs2),
1374                           cpu_env, s->vlen / 8, s->vlen / 8,
1375                           data, fn);
1376        mark_vs_dirty(s);
1377        gen_set_label(over);
1378        return true;
1379    }
1380    return false;
1381}
1382
1383#define GEN_OPIVV_WIDEN_TRANS(NAME, CHECK) \
1384static bool trans_##NAME(DisasContext *s, arg_rmrr *a)       \
1385{                                                            \
1386    static gen_helper_gvec_4_ptr * const fns[3] = {          \
1387        gen_helper_##NAME##_b,                               \
1388        gen_helper_##NAME##_h,                               \
1389        gen_helper_##NAME##_w                                \
1390    };                                                       \
1391    return do_opivv_widen(s, a, fns[s->sew], CHECK);         \
1392}
1393
1394GEN_OPIVV_WIDEN_TRANS(vwaddu_vv, opivv_widen_check)
1395GEN_OPIVV_WIDEN_TRANS(vwadd_vv, opivv_widen_check)
1396GEN_OPIVV_WIDEN_TRANS(vwsubu_vv, opivv_widen_check)
1397GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check)
1398
1399/* OPIVX with WIDEN */
1400static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
1401{
1402    return require_rvv(s) &&
1403           vext_check_isa_ill(s) &&
1404           vext_check_ds(s, a->rd, a->rs2, a->vm);
1405}
1406
1407static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
1408                           gen_helper_opivx *fn)
1409{
1410    if (opivx_widen_check(s, a)) {
1411        return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
1412    }
1413    return false;
1414}
1415
1416#define GEN_OPIVX_WIDEN_TRANS(NAME) \
1417static bool trans_##NAME(DisasContext *s, arg_rmrr *a)       \
1418{                                                            \
1419    static gen_helper_opivx * const fns[3] = {               \
1420        gen_helper_##NAME##_b,                               \
1421        gen_helper_##NAME##_h,                               \
1422        gen_helper_##NAME##_w                                \
1423    };                                                       \
1424    return do_opivx_widen(s, a, fns[s->sew]);                \
1425}
1426
1427GEN_OPIVX_WIDEN_TRANS(vwaddu_vx)
1428GEN_OPIVX_WIDEN_TRANS(vwadd_vx)
1429GEN_OPIVX_WIDEN_TRANS(vwsubu_vx)
1430GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
1431
1432/* WIDEN OPIVV with WIDEN */
1433static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
1434{
1435    return require_rvv(s) &&
1436           vext_check_isa_ill(s) &&
1437           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
1438}
1439
1440static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
1441                           gen_helper_gvec_4_ptr *fn)
1442{
1443    if (opiwv_widen_check(s, a)) {
1444        uint32_t data = 0;
1445        TCGLabel *over = gen_new_label();
1446        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1447
1448        data = FIELD_DP32(data, VDATA, VM, a->vm);
1449        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
1450        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
1451                           vreg_ofs(s, a->rs1),
1452                           vreg_ofs(s, a->rs2),
1453                           cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
1454        mark_vs_dirty(s);
1455        gen_set_label(over);
1456        return true;
1457    }
1458    return false;
1459}
1460
1461#define GEN_OPIWV_WIDEN_TRANS(NAME) \
1462static bool trans_##NAME(DisasContext *s, arg_rmrr *a)       \
1463{                                                            \
1464    static gen_helper_gvec_4_ptr * const fns[3] = {          \
1465        gen_helper_##NAME##_b,                               \
1466        gen_helper_##NAME##_h,                               \
1467        gen_helper_##NAME##_w                                \
1468    };                                                       \
1469    return do_opiwv_widen(s, a, fns[s->sew]);                \
1470}
1471
1472GEN_OPIWV_WIDEN_TRANS(vwaddu_wv)
1473GEN_OPIWV_WIDEN_TRANS(vwadd_wv)
1474GEN_OPIWV_WIDEN_TRANS(vwsubu_wv)
1475GEN_OPIWV_WIDEN_TRANS(vwsub_wv)
1476
1477/* WIDEN OPIVX with WIDEN */
1478static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a)
1479{
1480    return require_rvv(s) &&
1481           vext_check_isa_ill(s) &&
1482           vext_check_dd(s, a->rd, a->rs2, a->vm);
1483}
1484
1485static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
1486                           gen_helper_opivx *fn)
1487{
1488    if (opiwx_widen_check(s, a)) {
1489        return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
1490    }
1491    return false;
1492}
1493
1494#define GEN_OPIWX_WIDEN_TRANS(NAME) \
1495static bool trans_##NAME(DisasContext *s, arg_rmrr *a)       \
1496{                                                            \
1497    static gen_helper_opivx * const fns[3] = {               \
1498        gen_helper_##NAME##_b,                               \
1499        gen_helper_##NAME##_h,                               \
1500        gen_helper_##NAME##_w                                \
1501    };                                                       \
1502    return do_opiwx_widen(s, a, fns[s->sew]);                \
1503}
1504
1505GEN_OPIWX_WIDEN_TRANS(vwaddu_wx)
1506GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
1507GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
1508GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
1509
1510/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
1511/* OPIVV without GVEC IR */
1512#define GEN_OPIVV_TRANS(NAME, CHECK)                               \
1513static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
1514{                                                                  \
1515    if (CHECK(s, a)) {                                             \
1516        uint32_t data = 0;                                         \
1517        static gen_helper_gvec_4_ptr * const fns[4] = {            \
1518            gen_helper_##NAME##_b, gen_helper_##NAME##_h,          \
1519            gen_helper_##NAME##_w, gen_helper_##NAME##_d,          \
1520        };                                                         \
1521        TCGLabel *over = gen_new_label();                          \
1522        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
1523                                                                   \
1524        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
1525        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
1526        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
1527                           vreg_ofs(s, a->rs1),                    \
1528                           vreg_ofs(s, a->rs2), cpu_env,           \
1529                           s->vlen / 8, s->vlen / 8, data,         \
1530                           fns[s->sew]);                           \
1531        mark_vs_dirty(s);                                          \
1532        gen_set_label(over);                                       \
1533        return true;                                               \
1534    }                                                              \
1535    return false;                                                  \
1536}
1537
1538/*
1539 * For vadc and vsbc, an illegal instruction exception is raised if the
1540 * destination vector register is v0 and LMUL > 1. (Section 12.3)
1541 */
1542static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
1543{
1544    return require_rvv(s) &&
1545           vext_check_isa_ill(s) &&
1546           (a->rd != 0) &&
1547           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
1548}
1549
1550GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check)
1551GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check)
1552
1553/*
1554 * For vmadc and vmsbc, an illegal instruction exception is raised if the
1555 * destination vector register overlaps a source vector register group.
1556 */
1557static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
1558{
1559    return require_rvv(s) &&
1560           vext_check_isa_ill(s) &&
1561           vext_check_mss(s, a->rd, a->rs1, a->rs2);
1562}
1563
1564GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
1565GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check)
1566
1567static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a)
1568{
1569    return require_rvv(s) &&
1570           vext_check_isa_ill(s) &&
1571           (a->rd != 0) &&
1572           vext_check_ss(s, a->rd, a->rs2, a->vm);
1573}
1574
1575/* OPIVX without GVEC IR */
1576#define GEN_OPIVX_TRANS(NAME, CHECK)                                     \
1577static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
1578{                                                                        \
1579    if (CHECK(s, a)) {                                                   \
1580        static gen_helper_opivx * const fns[4] = {                       \
1581            gen_helper_##NAME##_b, gen_helper_##NAME##_h,                \
1582            gen_helper_##NAME##_w, gen_helper_##NAME##_d,                \
1583        };                                                               \
1584                                                                         \
1585        return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
1586    }                                                                    \
1587    return false;                                                        \
1588}
1589
1590GEN_OPIVX_TRANS(vadc_vxm, opivx_vadc_check)
1591GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check)
1592
1593static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
1594{
1595    return require_rvv(s) &&
1596           vext_check_isa_ill(s) &&
1597           vext_check_ms(s, a->rd, a->rs2);
1598}
1599
1600GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
1601GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check)
1602
1603/* OPIVI without GVEC IR */
1604#define GEN_OPIVI_TRANS(NAME, IMM_MODE, OPIVX, CHECK)                    \
1605static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
1606{                                                                        \
1607    if (CHECK(s, a)) {                                                   \
1608        static gen_helper_opivx * const fns[4] = {                       \
1609            gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h,              \
1610            gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d,              \
1611        };                                                               \
1612        return opivi_trans(a->rd, a->rs1, a->rs2, a->vm,                 \
1613                           fns[s->sew], s, IMM_MODE);                    \
1614    }                                                                    \
1615    return false;                                                        \
1616}
1617
1618GEN_OPIVI_TRANS(vadc_vim, IMM_SX, vadc_vxm, opivx_vadc_check)
1619GEN_OPIVI_TRANS(vmadc_vim, IMM_SX, vmadc_vxm, opivx_vmadc_check)
1620
1621/* Vector Bitwise Logical Instructions */
1622GEN_OPIVV_GVEC_TRANS(vand_vv, and)
1623GEN_OPIVV_GVEC_TRANS(vor_vv,  or)
1624GEN_OPIVV_GVEC_TRANS(vxor_vv, xor)
1625GEN_OPIVX_GVEC_TRANS(vand_vx, ands)
1626GEN_OPIVX_GVEC_TRANS(vor_vx,  ors)
1627GEN_OPIVX_GVEC_TRANS(vxor_vx, xors)
1628GEN_OPIVI_GVEC_TRANS(vand_vi, IMM_SX, vand_vx, andi)
1629GEN_OPIVI_GVEC_TRANS(vor_vi, IMM_SX, vor_vx,  ori)
1630GEN_OPIVI_GVEC_TRANS(vxor_vi, IMM_SX, vxor_vx, xori)
1631
1632/* Vector Single-Width Bit Shift Instructions */
1633GEN_OPIVV_GVEC_TRANS(vsll_vv,  shlv)
1634GEN_OPIVV_GVEC_TRANS(vsrl_vv,  shrv)
1635GEN_OPIVV_GVEC_TRANS(vsra_vv,  sarv)
1636
1637typedef void GVecGen2sFn32(unsigned, uint32_t, uint32_t, TCGv_i32,
1638                           uint32_t, uint32_t);
1639
1640static inline bool
1641do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
1642                    gen_helper_opivx *fn)
1643{
1644    if (!opivx_check(s, a)) {
1645        return false;
1646    }
1647
1648    if (a->vm && s->vl_eq_vlmax) {
1649        TCGv_i32 src1 = tcg_temp_new_i32();
1650
1651        tcg_gen_trunc_tl_i32(src1, get_gpr(s, a->rs1, EXT_NONE));
1652        tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
1653        gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
1654                src1, MAXSZ(s), MAXSZ(s));
1655
1656        tcg_temp_free_i32(src1);
1657        mark_vs_dirty(s);
1658        return true;
1659    }
1660    return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
1661}
1662
1663#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, SUF) \
1664static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                    \
1665{                                                                         \
1666    static gen_helper_opivx * const fns[4] = {                            \
1667        gen_helper_##NAME##_b, gen_helper_##NAME##_h,                     \
1668        gen_helper_##NAME##_w, gen_helper_##NAME##_d,                     \
1669    };                                                                    \
1670                                                                          \
1671    return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]);    \
1672}
1673
1674GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx,  shls)
1675GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx,  shrs)
1676GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx,  sars)
1677
1678GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli)
1679GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri)
1680GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari)
1681
1682/* Vector Narrowing Integer Right Shift Instructions */
1683static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
1684{
1685    return require_rvv(s) &&
1686           vext_check_isa_ill(s) &&
1687           vext_check_sds(s, a->rd, a->rs1, a->rs2, a->vm);
1688}
1689
1690/* OPIVV with NARROW */
1691#define GEN_OPIVV_NARROW_TRANS(NAME)                               \
1692static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
1693{                                                                  \
1694    if (opivv_narrow_check(s, a)) {                                \
1695        uint32_t data = 0;                                         \
1696        static gen_helper_gvec_4_ptr * const fns[3] = {            \
1697            gen_helper_##NAME##_b,                                 \
1698            gen_helper_##NAME##_h,                                 \
1699            gen_helper_##NAME##_w,                                 \
1700        };                                                         \
1701        TCGLabel *over = gen_new_label();                          \
1702        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
1703                                                                   \
1704        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
1705        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
1706        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
1707                           vreg_ofs(s, a->rs1),                    \
1708                           vreg_ofs(s, a->rs2), cpu_env,           \
1709                           s->vlen / 8, s->vlen / 8, data,         \
1710                           fns[s->sew]);                           \
1711        mark_vs_dirty(s);                                          \
1712        gen_set_label(over);                                       \
1713        return true;                                               \
1714    }                                                              \
1715    return false;                                                  \
1716}
1717GEN_OPIVV_NARROW_TRANS(vnsra_vv)
1718GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
1719
1720static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
1721{
1722    return require_rvv(s) &&
1723           vext_check_isa_ill(s) &&
1724           vext_check_sd(s, a->rd, a->rs2, a->vm);
1725}
1726
1727/* OPIVX with NARROW */
1728#define GEN_OPIVX_NARROW_TRANS(NAME)                                     \
1729static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
1730{                                                                        \
1731    if (opivx_narrow_check(s, a)) {                                      \
1732        static gen_helper_opivx * const fns[3] = {                       \
1733            gen_helper_##NAME##_b,                                       \
1734            gen_helper_##NAME##_h,                                       \
1735            gen_helper_##NAME##_w,                                       \
1736        };                                                               \
1737        return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
1738    }                                                                    \
1739    return false;                                                        \
1740}
1741
1742GEN_OPIVX_NARROW_TRANS(vnsra_vx)
1743GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
1744
1745/* OPIVI with NARROW */
1746#define GEN_OPIVI_NARROW_TRANS(NAME, IMM_MODE, OPIVX)                    \
1747static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
1748{                                                                        \
1749    if (opivx_narrow_check(s, a)) {                                      \
1750        static gen_helper_opivx * const fns[3] = {                       \
1751            gen_helper_##OPIVX##_b,                                      \
1752            gen_helper_##OPIVX##_h,                                      \
1753            gen_helper_##OPIVX##_w,                                      \
1754        };                                                               \
1755        return opivi_trans(a->rd, a->rs1, a->rs2, a->vm,                 \
1756                           fns[s->sew], s, IMM_MODE);                    \
1757    }                                                                    \
1758    return false;                                                        \
1759}
1760
1761GEN_OPIVI_NARROW_TRANS(vnsra_vi, IMM_ZX, vnsra_vx)
1762GEN_OPIVI_NARROW_TRANS(vnsrl_vi, IMM_ZX, vnsrl_vx)
1763
1764/* Vector Integer Comparison Instructions */
1765/*
1766 * For all comparison instructions, an illegal instruction exception is raised
1767 * if the destination vector register overlaps a source vector register group
1768 * and LMUL > 1.
1769 */
1770static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
1771{
1772    return require_rvv(s) &&
1773           vext_check_isa_ill(s) &&
1774           vext_check_mss(s, a->rd, a->rs1, a->rs2);
1775}
1776
1777GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
1778GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check)
1779GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check)
1780GEN_OPIVV_TRANS(vmslt_vv, opivv_cmp_check)
1781GEN_OPIVV_TRANS(vmsleu_vv, opivv_cmp_check)
1782GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check)
1783
1784static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
1785{
1786    return require_rvv(s) &&
1787           vext_check_isa_ill(s) &&
1788           vext_check_ms(s, a->rd, a->rs2);
1789}
1790
1791GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
1792GEN_OPIVX_TRANS(vmsne_vx, opivx_cmp_check)
1793GEN_OPIVX_TRANS(vmsltu_vx, opivx_cmp_check)
1794GEN_OPIVX_TRANS(vmslt_vx, opivx_cmp_check)
1795GEN_OPIVX_TRANS(vmsleu_vx, opivx_cmp_check)
1796GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check)
1797GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check)
1798GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
1799
1800GEN_OPIVI_TRANS(vmseq_vi, IMM_SX, vmseq_vx, opivx_cmp_check)
1801GEN_OPIVI_TRANS(vmsne_vi, IMM_SX, vmsne_vx, opivx_cmp_check)
1802GEN_OPIVI_TRANS(vmsleu_vi, IMM_ZX, vmsleu_vx, opivx_cmp_check)
1803GEN_OPIVI_TRANS(vmsle_vi, IMM_SX, vmsle_vx, opivx_cmp_check)
1804GEN_OPIVI_TRANS(vmsgtu_vi, IMM_ZX, vmsgtu_vx, opivx_cmp_check)
1805GEN_OPIVI_TRANS(vmsgt_vi, IMM_SX, vmsgt_vx, opivx_cmp_check)
1806
1807/* Vector Integer Min/Max Instructions */
1808GEN_OPIVV_GVEC_TRANS(vminu_vv, umin)
1809GEN_OPIVV_GVEC_TRANS(vmin_vv,  smin)
1810GEN_OPIVV_GVEC_TRANS(vmaxu_vv, umax)
1811GEN_OPIVV_GVEC_TRANS(vmax_vv,  smax)
1812GEN_OPIVX_TRANS(vminu_vx, opivx_check)
1813GEN_OPIVX_TRANS(vmin_vx,  opivx_check)
1814GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
1815GEN_OPIVX_TRANS(vmax_vx,  opivx_check)
1816
1817/* Vector Single-Width Integer Multiply Instructions */
1818GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
1819GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
1820GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
1821GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
1822GEN_OPIVX_GVEC_TRANS(vmul_vx,  muls)
1823GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
1824GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
1825GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
1826
1827/* Vector Integer Divide Instructions */
1828GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
1829GEN_OPIVV_TRANS(vdiv_vv, opivv_check)
1830GEN_OPIVV_TRANS(vremu_vv, opivv_check)
1831GEN_OPIVV_TRANS(vrem_vv, opivv_check)
1832GEN_OPIVX_TRANS(vdivu_vx, opivx_check)
1833GEN_OPIVX_TRANS(vdiv_vx, opivx_check)
1834GEN_OPIVX_TRANS(vremu_vx, opivx_check)
1835GEN_OPIVX_TRANS(vrem_vx, opivx_check)
1836
1837/* Vector Widening Integer Multiply Instructions */
1838GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
1839GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
1840GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
1841GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
1842GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
1843GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
1844
1845/* Vector Single-Width Integer Multiply-Add Instructions */
1846GEN_OPIVV_TRANS(vmacc_vv, opivv_check)
1847GEN_OPIVV_TRANS(vnmsac_vv, opivv_check)
1848GEN_OPIVV_TRANS(vmadd_vv, opivv_check)
1849GEN_OPIVV_TRANS(vnmsub_vv, opivv_check)
1850GEN_OPIVX_TRANS(vmacc_vx, opivx_check)
1851GEN_OPIVX_TRANS(vnmsac_vx, opivx_check)
1852GEN_OPIVX_TRANS(vmadd_vx, opivx_check)
1853GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
1854
1855/* Vector Widening Integer Multiply-Add Instructions */
1856GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
1857GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
1858GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
1859GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
1860GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
1861GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
1862GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
1863
1864/* Vector Integer Merge and Move Instructions */
1865static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
1866{
1867    if (require_rvv(s) &&
1868        vext_check_isa_ill(s) &&
1869        /* vmv.v.v has rs2 = 0 and vm = 1 */
1870        vext_check_sss(s, a->rd, a->rs1, 0, 1)) {
1871        if (s->vl_eq_vlmax) {
1872            tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
1873                             vreg_ofs(s, a->rs1),
1874                             MAXSZ(s), MAXSZ(s));
1875        } else {
1876            uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
1877            static gen_helper_gvec_2_ptr * const fns[4] = {
1878                gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
1879                gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
1880            };
1881            TCGLabel *over = gen_new_label();
1882            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1883
1884            tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
1885                               cpu_env, s->vlen / 8, s->vlen / 8, data,
1886                               fns[s->sew]);
1887            gen_set_label(over);
1888        }
1889        mark_vs_dirty(s);
1890        return true;
1891    }
1892    return false;
1893}
1894
1895typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
1896static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
1897{
1898    if (require_rvv(s) &&
1899        vext_check_isa_ill(s) &&
1900        /* vmv.v.x has rs2 = 0 and vm = 1 */
1901        vext_check_ss(s, a->rd, 0, 1)) {
1902        TCGv s1;
1903        TCGLabel *over = gen_new_label();
1904        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1905
1906        s1 = get_gpr(s, a->rs1, EXT_SIGN);
1907
1908        if (s->vl_eq_vlmax) {
1909            tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
1910                                MAXSZ(s), MAXSZ(s), s1);
1911        } else {
1912            TCGv_i32 desc;
1913            TCGv_i64 s1_i64 = tcg_temp_new_i64();
1914            TCGv_ptr dest = tcg_temp_new_ptr();
1915            uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
1916            static gen_helper_vmv_vx * const fns[4] = {
1917                gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
1918                gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
1919            };
1920
1921            tcg_gen_ext_tl_i64(s1_i64, s1);
1922            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
1923            tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
1924            fns[s->sew](dest, s1_i64, cpu_env, desc);
1925
1926            tcg_temp_free_ptr(dest);
1927            tcg_temp_free_i64(s1_i64);
1928        }
1929
1930        mark_vs_dirty(s);
1931        gen_set_label(over);
1932        return true;
1933    }
1934    return false;
1935}
1936
1937static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
1938{
1939    if (require_rvv(s) &&
1940        vext_check_isa_ill(s) &&
1941        /* vmv.v.i has rs2 = 0 and vm = 1 */
1942        vext_check_ss(s, a->rd, 0, 1)) {
1943        int64_t simm = sextract64(a->rs1, 0, 5);
1944        if (s->vl_eq_vlmax) {
1945            tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
1946                                 MAXSZ(s), MAXSZ(s), simm);
1947            mark_vs_dirty(s);
1948        } else {
1949            TCGv_i32 desc;
1950            TCGv_i64 s1;
1951            TCGv_ptr dest;
1952            uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
1953            static gen_helper_vmv_vx * const fns[4] = {
1954                gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
1955                gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
1956            };
1957            TCGLabel *over = gen_new_label();
1958            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
1959
1960            s1 = tcg_constant_i64(simm);
1961            dest = tcg_temp_new_ptr();
1962            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
1963            tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
1964            fns[s->sew](dest, s1, cpu_env, desc);
1965
1966            tcg_temp_free_ptr(dest);
1967            mark_vs_dirty(s);
1968            gen_set_label(over);
1969        }
1970        return true;
1971    }
1972    return false;
1973}
1974
1975GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check)
1976GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check)
1977GEN_OPIVI_TRANS(vmerge_vim, IMM_SX, vmerge_vxm, opivx_vadc_check)
1978
1979/*
1980 *** Vector Fixed-Point Arithmetic Instructions
1981 */
1982
1983/* Vector Single-Width Saturating Add and Subtract */
1984GEN_OPIVV_TRANS(vsaddu_vv, opivv_check)
1985GEN_OPIVV_TRANS(vsadd_vv,  opivv_check)
1986GEN_OPIVV_TRANS(vssubu_vv, opivv_check)
1987GEN_OPIVV_TRANS(vssub_vv,  opivv_check)
1988GEN_OPIVX_TRANS(vsaddu_vx,  opivx_check)
1989GEN_OPIVX_TRANS(vsadd_vx,  opivx_check)
1990GEN_OPIVX_TRANS(vssubu_vx,  opivx_check)
1991GEN_OPIVX_TRANS(vssub_vx,  opivx_check)
1992GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check)
1993GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check)
1994
1995/* Vector Single-Width Averaging Add and Subtract */
1996GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
1997GEN_OPIVV_TRANS(vasub_vv, opivv_check)
1998GEN_OPIVX_TRANS(vaadd_vx,  opivx_check)
1999GEN_OPIVX_TRANS(vasub_vx,  opivx_check)
2000GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
2001
2002/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
2003GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
2004GEN_OPIVX_TRANS(vsmul_vx,  opivx_check)
2005
2006/* Vector Widening Saturating Scaled Multiply-Add */
2007GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
2008GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
2009GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
2010GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
2011GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
2012GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
2013GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
2014
2015/* Vector Single-Width Scaling Shift Instructions */
2016GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
2017GEN_OPIVV_TRANS(vssra_vv, opivv_check)
2018GEN_OPIVX_TRANS(vssrl_vx,  opivx_check)
2019GEN_OPIVX_TRANS(vssra_vx,  opivx_check)
2020GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check)
2021GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check)
2022
2023/* Vector Narrowing Fixed-Point Clip Instructions */
2024GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
2025GEN_OPIVV_NARROW_TRANS(vnclip_vv)
2026GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
2027GEN_OPIVX_NARROW_TRANS(vnclip_vx)
2028GEN_OPIVI_NARROW_TRANS(vnclipu_vi, IMM_ZX, vnclipu_vx)
2029GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx)
2030
2031/*
2032 *** Vector Float Point Arithmetic Instructions
2033 */
2034
2035/*
2036 * As RVF-only cpus always have values NaN-boxed to 64-bits,
2037 * RVF and RVD can be treated equally.
2038 * We don't have to deal with the cases of: SEW > FLEN.
2039 *
2040 * If SEW < FLEN, check whether input fp register is a valid
2041 * NaN-boxed value, in which case the least-significant SEW bits
2042 * of the f regsiter are used, else the canonical NaN value is used.
2043 */
2044static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
2045{
2046    switch (s->sew) {
2047    case 1:
2048        gen_check_nanbox_h(out, in);
2049        break;
2050    case 2:
2051        gen_check_nanbox_s(out, in);
2052        break;
2053    case 3:
2054        tcg_gen_mov_i64(out, in);
2055        break;
2056    default:
2057        g_assert_not_reached();
2058    }
2059}
2060
2061/* Vector Single-Width Floating-Point Add/Subtract Instructions */
2062
2063/*
2064 * If the current SEW does not correspond to a supported IEEE floating-point
2065 * type, an illegal instruction exception is raised.
2066 */
2067static bool opfvv_check(DisasContext *s, arg_rmrr *a)
2068{
2069    return require_rvv(s) &&
2070           require_rvf(s) &&
2071           vext_check_isa_ill(s) &&
2072           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
2073}
2074
2075/* OPFVV without GVEC IR */
2076#define GEN_OPFVV_TRANS(NAME, CHECK)                               \
2077static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
2078{                                                                  \
2079    if (CHECK(s, a)) {                                             \
2080        uint32_t data = 0;                                         \
2081        static gen_helper_gvec_4_ptr * const fns[3] = {            \
2082            gen_helper_##NAME##_h,                                 \
2083            gen_helper_##NAME##_w,                                 \
2084            gen_helper_##NAME##_d,                                 \
2085        };                                                         \
2086        TCGLabel *over = gen_new_label();                          \
2087        gen_set_rm(s, 7);                                          \
2088        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
2089                                                                   \
2090        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
2091        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
2092        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
2093                           vreg_ofs(s, a->rs1),                    \
2094                           vreg_ofs(s, a->rs2), cpu_env,           \
2095                           s->vlen / 8, s->vlen / 8, data,         \
2096                           fns[s->sew - 1]);                       \
2097        mark_vs_dirty(s);                                          \
2098        gen_set_label(over);                                       \
2099        return true;                                               \
2100    }                                                              \
2101    return false;                                                  \
2102}
2103GEN_OPFVV_TRANS(vfadd_vv, opfvv_check)
2104GEN_OPFVV_TRANS(vfsub_vv, opfvv_check)
2105
2106typedef void gen_helper_opfvf(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr,
2107                              TCGv_env, TCGv_i32);
2108
2109static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
2110                        uint32_t data, gen_helper_opfvf *fn, DisasContext *s)
2111{
2112    TCGv_ptr dest, src2, mask;
2113    TCGv_i32 desc;
2114    TCGv_i64 t1;
2115
2116    TCGLabel *over = gen_new_label();
2117    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2118
2119    dest = tcg_temp_new_ptr();
2120    mask = tcg_temp_new_ptr();
2121    src2 = tcg_temp_new_ptr();
2122    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
2123
2124    tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
2125    tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
2126    tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
2127
2128    /* NaN-box f[rs1] */
2129    t1 = tcg_temp_new_i64();
2130    do_nanbox(s, t1, cpu_fpr[rs1]);
2131
2132    fn(dest, mask, t1, src2, cpu_env, desc);
2133
2134    tcg_temp_free_ptr(dest);
2135    tcg_temp_free_ptr(mask);
2136    tcg_temp_free_ptr(src2);
2137    tcg_temp_free_i64(t1);
2138    mark_vs_dirty(s);
2139    gen_set_label(over);
2140    return true;
2141}
2142
2143/*
2144 * If the current SEW does not correspond to a supported IEEE floating-point
2145 * type, an illegal instruction exception is raised
2146 */
2147static bool opfvf_check(DisasContext *s, arg_rmrr *a)
2148{
2149    return require_rvv(s) &&
2150           require_rvf(s) &&
2151           vext_check_isa_ill(s) &&
2152           vext_check_ss(s, a->rd, a->rs2, a->vm);
2153}
2154
2155/* OPFVF without GVEC IR */
2156#define GEN_OPFVF_TRANS(NAME, CHECK)                              \
2157static bool trans_##NAME(DisasContext *s, arg_rmrr *a)            \
2158{                                                                 \
2159    if (CHECK(s, a)) {                                            \
2160        uint32_t data = 0;                                        \
2161        static gen_helper_opfvf *const fns[3] = {                 \
2162            gen_helper_##NAME##_h,                                \
2163            gen_helper_##NAME##_w,                                \
2164            gen_helper_##NAME##_d,                                \
2165        };                                                        \
2166        gen_set_rm(s, 7);                                         \
2167        data = FIELD_DP32(data, VDATA, VM, a->vm);                \
2168        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);            \
2169        return opfvf_trans(a->rd, a->rs1, a->rs2, data,           \
2170                           fns[s->sew - 1], s);                   \
2171    }                                                             \
2172    return false;                                                 \
2173}
2174
2175GEN_OPFVF_TRANS(vfadd_vf,  opfvf_check)
2176GEN_OPFVF_TRANS(vfsub_vf,  opfvf_check)
2177GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
2178
2179/* Vector Widening Floating-Point Add/Subtract Instructions */
2180static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
2181{
2182    return require_rvv(s) &&
2183           require_rvf(s) &&
2184           vext_check_isa_ill(s) &&
2185           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
2186}
2187
2188/* OPFVV with WIDEN */
2189#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK)                       \
2190static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
2191{                                                                \
2192    if (CHECK(s, a)) {                                           \
2193        uint32_t data = 0;                                       \
2194        static gen_helper_gvec_4_ptr * const fns[2] = {          \
2195            gen_helper_##NAME##_h, gen_helper_##NAME##_w,        \
2196        };                                                       \
2197        TCGLabel *over = gen_new_label();                        \
2198        gen_set_rm(s, 7);                                        \
2199        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);        \
2200                                                                 \
2201        data = FIELD_DP32(data, VDATA, VM, a->vm);               \
2202        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
2203        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),   \
2204                           vreg_ofs(s, a->rs1),                  \
2205                           vreg_ofs(s, a->rs2), cpu_env,         \
2206                           s->vlen / 8, s->vlen / 8, data,       \
2207                           fns[s->sew - 1]);                     \
2208        mark_vs_dirty(s);                                        \
2209        gen_set_label(over);                                     \
2210        return true;                                             \
2211    }                                                            \
2212    return false;                                                \
2213}
2214
2215GEN_OPFVV_WIDEN_TRANS(vfwadd_vv, opfvv_widen_check)
2216GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
2217
2218static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
2219{
2220    return require_rvv(s) &&
2221           require_rvf(s) &&
2222           vext_check_isa_ill(s) &&
2223           vext_check_ds(s, a->rd, a->rs2, a->vm);
2224}
2225
2226/* OPFVF with WIDEN */
2227#define GEN_OPFVF_WIDEN_TRANS(NAME)                              \
2228static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
2229{                                                                \
2230    if (opfvf_widen_check(s, a)) {                               \
2231        uint32_t data = 0;                                       \
2232        static gen_helper_opfvf *const fns[2] = {                \
2233            gen_helper_##NAME##_h, gen_helper_##NAME##_w,        \
2234        };                                                       \
2235        gen_set_rm(s, 7);                                        \
2236        data = FIELD_DP32(data, VDATA, VM, a->vm);               \
2237        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
2238        return opfvf_trans(a->rd, a->rs1, a->rs2, data,          \
2239                           fns[s->sew - 1], s);                  \
2240    }                                                            \
2241    return false;                                                \
2242}
2243
2244GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
2245GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
2246
2247static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
2248{
2249    return require_rvv(s) &&
2250           require_rvf(s) &&
2251           vext_check_isa_ill(s) &&
2252           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
2253}
2254
2255/* WIDEN OPFVV with WIDEN */
2256#define GEN_OPFWV_WIDEN_TRANS(NAME)                                \
2257static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
2258{                                                                  \
2259    if (opfwv_widen_check(s, a)) {                                 \
2260        uint32_t data = 0;                                         \
2261        static gen_helper_gvec_4_ptr * const fns[2] = {            \
2262            gen_helper_##NAME##_h, gen_helper_##NAME##_w,          \
2263        };                                                         \
2264        TCGLabel *over = gen_new_label();                          \
2265        gen_set_rm(s, 7);                                          \
2266        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
2267                                                                   \
2268        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
2269        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
2270        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
2271                           vreg_ofs(s, a->rs1),                    \
2272                           vreg_ofs(s, a->rs2), cpu_env,           \
2273                           s->vlen / 8, s->vlen / 8, data,         \
2274                           fns[s->sew - 1]);                       \
2275        mark_vs_dirty(s);                                          \
2276        gen_set_label(over);                                       \
2277        return true;                                               \
2278    }                                                              \
2279    return false;                                                  \
2280}
2281
2282GEN_OPFWV_WIDEN_TRANS(vfwadd_wv)
2283GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
2284
2285static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
2286{
2287    return require_rvv(s) &&
2288           require_rvf(s) &&
2289           vext_check_isa_ill(s) &&
2290           vext_check_dd(s, a->rd, a->rs2, a->vm);
2291}
2292
2293/* WIDEN OPFVF with WIDEN */
2294#define GEN_OPFWF_WIDEN_TRANS(NAME)                              \
2295static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
2296{                                                                \
2297    if (opfwf_widen_check(s, a)) {                               \
2298        uint32_t data = 0;                                       \
2299        static gen_helper_opfvf *const fns[2] = {                \
2300            gen_helper_##NAME##_h, gen_helper_##NAME##_w,        \
2301        };                                                       \
2302        gen_set_rm(s, 7);                                        \
2303        data = FIELD_DP32(data, VDATA, VM, a->vm);               \
2304        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);           \
2305        return opfvf_trans(a->rd, a->rs1, a->rs2, data,          \
2306                           fns[s->sew - 1], s);                  \
2307    }                                                            \
2308    return false;                                                \
2309}
2310
2311GEN_OPFWF_WIDEN_TRANS(vfwadd_wf)
2312GEN_OPFWF_WIDEN_TRANS(vfwsub_wf)
2313
2314/* Vector Single-Width Floating-Point Multiply/Divide Instructions */
2315GEN_OPFVV_TRANS(vfmul_vv, opfvv_check)
2316GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check)
2317GEN_OPFVF_TRANS(vfmul_vf,  opfvf_check)
2318GEN_OPFVF_TRANS(vfdiv_vf,  opfvf_check)
2319GEN_OPFVF_TRANS(vfrdiv_vf,  opfvf_check)
2320
2321/* Vector Widening Floating-Point Multiply */
2322GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
2323GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
2324
2325/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
2326GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
2327GEN_OPFVV_TRANS(vfnmacc_vv, opfvv_check)
2328GEN_OPFVV_TRANS(vfmsac_vv, opfvv_check)
2329GEN_OPFVV_TRANS(vfnmsac_vv, opfvv_check)
2330GEN_OPFVV_TRANS(vfmadd_vv, opfvv_check)
2331GEN_OPFVV_TRANS(vfnmadd_vv, opfvv_check)
2332GEN_OPFVV_TRANS(vfmsub_vv, opfvv_check)
2333GEN_OPFVV_TRANS(vfnmsub_vv, opfvv_check)
2334GEN_OPFVF_TRANS(vfmacc_vf, opfvf_check)
2335GEN_OPFVF_TRANS(vfnmacc_vf, opfvf_check)
2336GEN_OPFVF_TRANS(vfmsac_vf, opfvf_check)
2337GEN_OPFVF_TRANS(vfnmsac_vf, opfvf_check)
2338GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check)
2339GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check)
2340GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
2341GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
2342
2343/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
2344GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
2345GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
2346GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
2347GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
2348GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
2349GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
2350GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
2351GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
2352
2353/* Vector Floating-Point Square-Root Instruction */
2354
2355/*
2356 * If the current SEW does not correspond to a supported IEEE floating-point
2357 * type, an illegal instruction exception is raised
2358 */
2359static bool opfv_check(DisasContext *s, arg_rmr *a)
2360{
2361    return require_rvv(s) &&
2362           require_rvf(s) &&
2363           vext_check_isa_ill(s) &&
2364           /* OPFV instructions ignore vs1 check */
2365           vext_check_ss(s, a->rd, a->rs2, a->vm);
2366}
2367
2368#define GEN_OPFV_TRANS(NAME, CHECK)                                \
2369static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
2370{                                                                  \
2371    if (CHECK(s, a)) {                                             \
2372        uint32_t data = 0;                                         \
2373        static gen_helper_gvec_3_ptr * const fns[3] = {            \
2374            gen_helper_##NAME##_h,                                 \
2375            gen_helper_##NAME##_w,                                 \
2376            gen_helper_##NAME##_d,                                 \
2377        };                                                         \
2378        TCGLabel *over = gen_new_label();                          \
2379        gen_set_rm(s, 7);                                          \
2380        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
2381                                                                   \
2382        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
2383        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
2384        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
2385                           vreg_ofs(s, a->rs2), cpu_env,           \
2386                           s->vlen / 8, s->vlen / 8, data,         \
2387                           fns[s->sew - 1]);                       \
2388        mark_vs_dirty(s);                                          \
2389        gen_set_label(over);                                       \
2390        return true;                                               \
2391    }                                                              \
2392    return false;                                                  \
2393}
2394
2395GEN_OPFV_TRANS(vfsqrt_v, opfv_check)
2396
2397/* Vector Floating-Point MIN/MAX Instructions */
2398GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
2399GEN_OPFVV_TRANS(vfmax_vv, opfvv_check)
2400GEN_OPFVF_TRANS(vfmin_vf, opfvf_check)
2401GEN_OPFVF_TRANS(vfmax_vf, opfvf_check)
2402
2403/* Vector Floating-Point Sign-Injection Instructions */
2404GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check)
2405GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check)
2406GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check)
2407GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check)
2408GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check)
2409GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
2410
2411/* Vector Floating-Point Compare Instructions */
2412static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
2413{
2414    return require_rvv(s) &&
2415           require_rvf(s) &&
2416           vext_check_isa_ill(s) &&
2417           vext_check_mss(s, a->rd, a->rs1, a->rs2);
2418}
2419
2420GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
2421GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
2422GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
2423GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
2424GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
2425
2426static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
2427{
2428    return require_rvv(s) &&
2429           require_rvf(s) &&
2430           vext_check_isa_ill(s) &&
2431           vext_check_ms(s, a->rd, a->rs2);
2432}
2433
2434GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
2435GEN_OPFVF_TRANS(vmfne_vf, opfvf_cmp_check)
2436GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
2437GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
2438GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
2439GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
2440GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
2441
2442/* Vector Floating-Point Classify Instruction */
2443GEN_OPFV_TRANS(vfclass_v, opfv_check)
2444
2445/* Vector Floating-Point Merge Instruction */
2446GEN_OPFVF_TRANS(vfmerge_vfm,  opfvf_check)
2447
2448static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
2449{
2450    if (require_rvv(s) &&
2451        require_rvf(s) &&
2452        vext_check_isa_ill(s) &&
2453        require_align(a->rd, s->lmul)) {
2454        if (s->vl_eq_vlmax) {
2455            tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
2456                                 MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
2457            mark_vs_dirty(s);
2458        } else {
2459            TCGv_ptr dest;
2460            TCGv_i32 desc;
2461            uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
2462            static gen_helper_vmv_vx * const fns[3] = {
2463                gen_helper_vmv_v_x_h,
2464                gen_helper_vmv_v_x_w,
2465                gen_helper_vmv_v_x_d,
2466            };
2467            TCGLabel *over = gen_new_label();
2468            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2469
2470            dest = tcg_temp_new_ptr();
2471            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
2472            tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
2473            fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
2474
2475            tcg_temp_free_ptr(dest);
2476            mark_vs_dirty(s);
2477            gen_set_label(over);
2478        }
2479        return true;
2480    }
2481    return false;
2482}
2483
2484/* Single-Width Floating-Point/Integer Type-Convert Instructions */
2485GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
2486GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
2487GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
2488GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
2489
2490/* Widening Floating-Point/Integer Type-Convert Instructions */
2491
2492/*
2493 * If the current SEW does not correspond to a supported IEEE floating-point
2494 * type, an illegal instruction exception is raised
2495 */
2496static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
2497{
2498    return require_rvv(s) &&
2499           require_scale_rvf(s) &&
2500           (s->sew != MO_8) &&
2501           vext_check_isa_ill(s) &&
2502           vext_check_ds(s, a->rd, a->rs2, a->vm);
2503}
2504
2505#define GEN_OPFV_WIDEN_TRANS(NAME)                                 \
2506static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
2507{                                                                  \
2508    if (opfv_widen_check(s, a)) {                                  \
2509        uint32_t data = 0;                                         \
2510        static gen_helper_gvec_3_ptr * const fns[2] = {            \
2511            gen_helper_##NAME##_h,                                 \
2512            gen_helper_##NAME##_w,                                 \
2513        };                                                         \
2514        TCGLabel *over = gen_new_label();                          \
2515        gen_set_rm(s, 7);                                          \
2516        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
2517                                                                   \
2518        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
2519        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
2520        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
2521                           vreg_ofs(s, a->rs2), cpu_env,           \
2522                           s->vlen / 8, s->vlen / 8, data,         \
2523                           fns[s->sew - 1]);                       \
2524        mark_vs_dirty(s);                                          \
2525        gen_set_label(over);                                       \
2526        return true;                                               \
2527    }                                                              \
2528    return false;                                                  \
2529}
2530
2531GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v)
2532GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
2533GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
2534GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
2535GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
2536
2537/* Narrowing Floating-Point/Integer Type-Convert Instructions */
2538
2539/*
2540 * If the current SEW does not correspond to a supported IEEE floating-point
2541 * type, an illegal instruction exception is raised
2542 */
2543static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
2544{
2545    return require_rvv(s) &&
2546           require_rvf(s) &&
2547           (s->sew != MO_64) &&
2548           vext_check_isa_ill(s) &&
2549           /* OPFV narrowing instructions ignore vs1 check */
2550           vext_check_sd(s, a->rd, a->rs2, a->vm);
2551}
2552
2553#define GEN_OPFV_NARROW_TRANS(NAME)                                \
2554static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
2555{                                                                  \
2556    if (opfv_narrow_check(s, a)) {                                 \
2557        uint32_t data = 0;                                         \
2558        static gen_helper_gvec_3_ptr * const fns[2] = {            \
2559            gen_helper_##NAME##_h,                                 \
2560            gen_helper_##NAME##_w,                                 \
2561        };                                                         \
2562        TCGLabel *over = gen_new_label();                          \
2563        gen_set_rm(s, 7);                                          \
2564        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
2565                                                                   \
2566        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
2567        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
2568        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
2569                           vreg_ofs(s, a->rs2), cpu_env,           \
2570                           s->vlen / 8, s->vlen / 8, data,         \
2571                           fns[s->sew - 1]);                       \
2572        mark_vs_dirty(s);                                          \
2573        gen_set_label(over);                                       \
2574        return true;                                               \
2575    }                                                              \
2576    return false;                                                  \
2577}
2578
2579GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
2580GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
2581GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
2582GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
2583GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
2584
2585/*
2586 *** Vector Reduction Operations
2587 */
2588/* Vector Single-Width Integer Reduction Instructions */
2589static bool reduction_check(DisasContext *s, arg_rmrr *a)
2590{
2591    return require_rvv(s) &&
2592           vext_check_isa_ill(s) &&
2593           vext_check_reduction(s, a->rs2);
2594}
2595
2596GEN_OPIVV_TRANS(vredsum_vs, reduction_check)
2597GEN_OPIVV_TRANS(vredmaxu_vs, reduction_check)
2598GEN_OPIVV_TRANS(vredmax_vs, reduction_check)
2599GEN_OPIVV_TRANS(vredminu_vs, reduction_check)
2600GEN_OPIVV_TRANS(vredmin_vs, reduction_check)
2601GEN_OPIVV_TRANS(vredand_vs, reduction_check)
2602GEN_OPIVV_TRANS(vredor_vs, reduction_check)
2603GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
2604
2605/* Vector Widening Integer Reduction Instructions */
2606static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
2607{
2608    return reduction_check(s, a) && (s->sew < MO_64);
2609}
2610
2611GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
2612GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
2613
2614/* Vector Single-Width Floating-Point Reduction Instructions */
2615GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
2616GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
2617GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
2618
2619/* Vector Widening Floating-Point Reduction Instructions */
2620GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
2621
2622/*
2623 *** Vector Mask Operations
2624 */
2625
2626/* Vector Mask-Register Logical Instructions */
2627#define GEN_MM_TRANS(NAME)                                         \
2628static bool trans_##NAME(DisasContext *s, arg_r *a)                \
2629{                                                                  \
2630    if (vext_check_isa_ill(s)) {                                   \
2631        uint32_t data = 0;                                         \
2632        gen_helper_gvec_4_ptr *fn = gen_helper_##NAME;             \
2633        TCGLabel *over = gen_new_label();                          \
2634        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
2635                                                                   \
2636        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
2637        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
2638                           vreg_ofs(s, a->rs1),                    \
2639                           vreg_ofs(s, a->rs2), cpu_env,           \
2640                           s->vlen / 8, s->vlen / 8, data, fn);    \
2641        mark_vs_dirty(s);                                          \
2642        gen_set_label(over);                                       \
2643        return true;                                               \
2644    }                                                              \
2645    return false;                                                  \
2646}
2647
2648GEN_MM_TRANS(vmand_mm)
2649GEN_MM_TRANS(vmnand_mm)
2650GEN_MM_TRANS(vmandnot_mm)
2651GEN_MM_TRANS(vmxor_mm)
2652GEN_MM_TRANS(vmor_mm)
2653GEN_MM_TRANS(vmnor_mm)
2654GEN_MM_TRANS(vmornot_mm)
2655GEN_MM_TRANS(vmxnor_mm)
2656
2657/* Vector mask population count vmpopc */
2658static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
2659{
2660    if (require_rvv(s) &&
2661        vext_check_isa_ill(s)) {
2662        TCGv_ptr src2, mask;
2663        TCGv dst;
2664        TCGv_i32 desc;
2665        uint32_t data = 0;
2666        data = FIELD_DP32(data, VDATA, VM, a->vm);
2667        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2668
2669        mask = tcg_temp_new_ptr();
2670        src2 = tcg_temp_new_ptr();
2671        dst = dest_gpr(s, a->rd);
2672        desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
2673
2674        tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
2675        tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
2676
2677        gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
2678        gen_set_gpr(s, a->rd, dst);
2679
2680        tcg_temp_free_ptr(mask);
2681        tcg_temp_free_ptr(src2);
2682        return true;
2683    }
2684    return false;
2685}
2686
2687/* vmfirst find-first-set mask bit */
2688static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
2689{
2690    if (require_rvv(s) &&
2691        vext_check_isa_ill(s)) {
2692        TCGv_ptr src2, mask;
2693        TCGv dst;
2694        TCGv_i32 desc;
2695        uint32_t data = 0;
2696        data = FIELD_DP32(data, VDATA, VM, a->vm);
2697        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2698
2699        mask = tcg_temp_new_ptr();
2700        src2 = tcg_temp_new_ptr();
2701        dst = dest_gpr(s, a->rd);
2702        desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
2703
2704        tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
2705        tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
2706
2707        gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
2708        gen_set_gpr(s, a->rd, dst);
2709
2710        tcg_temp_free_ptr(mask);
2711        tcg_temp_free_ptr(src2);
2712        return true;
2713    }
2714    return false;
2715}
2716
2717/* vmsbf.m set-before-first mask bit */
2718/* vmsif.m set-includ-first mask bit */
2719/* vmsof.m set-only-first mask bit */
2720#define GEN_M_TRANS(NAME)                                          \
2721static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
2722{                                                                  \
2723    if (vext_check_isa_ill(s)) {                                   \
2724        uint32_t data = 0;                                         \
2725        gen_helper_gvec_3_ptr *fn = gen_helper_##NAME;             \
2726        TCGLabel *over = gen_new_label();                          \
2727        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
2728                                                                   \
2729        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
2730        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
2731        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd),                     \
2732                           vreg_ofs(s, 0), vreg_ofs(s, a->rs2),    \
2733                           cpu_env, s->vlen / 8, s->vlen / 8,      \
2734                           data, fn);                              \
2735        mark_vs_dirty(s);                                          \
2736        gen_set_label(over);                                       \
2737        return true;                                               \
2738    }                                                              \
2739    return false;                                                  \
2740}
2741
2742GEN_M_TRANS(vmsbf_m)
2743GEN_M_TRANS(vmsif_m)
2744GEN_M_TRANS(vmsof_m)
2745
2746/* Vector Iota Instruction */
2747static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
2748{
2749    if (require_rvv(s) &&
2750        vext_check_isa_ill(s) &&
2751        require_noover(a->rd, s->lmul, a->rs2, 0) &&
2752        require_vm(a->vm, a->rd) &&
2753        require_align(a->rd, s->lmul)) {
2754        uint32_t data = 0;
2755        TCGLabel *over = gen_new_label();
2756        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2757
2758        data = FIELD_DP32(data, VDATA, VM, a->vm);
2759        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2760        static gen_helper_gvec_3_ptr * const fns[4] = {
2761            gen_helper_viota_m_b, gen_helper_viota_m_h,
2762            gen_helper_viota_m_w, gen_helper_viota_m_d,
2763        };
2764        tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
2765                           vreg_ofs(s, a->rs2), cpu_env,
2766                           s->vlen / 8, s->vlen / 8, data, fns[s->sew]);
2767        mark_vs_dirty(s);
2768        gen_set_label(over);
2769        return true;
2770    }
2771    return false;
2772}
2773
2774/* Vector Element Index Instruction */
2775static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
2776{
2777    if (require_rvv(s) &&
2778        vext_check_isa_ill(s) &&
2779        require_align(a->rd, s->lmul) &&
2780        require_vm(a->vm, a->rd)) {
2781        uint32_t data = 0;
2782        TCGLabel *over = gen_new_label();
2783        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2784
2785        data = FIELD_DP32(data, VDATA, VM, a->vm);
2786        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
2787        static gen_helper_gvec_2_ptr * const fns[4] = {
2788            gen_helper_vid_v_b, gen_helper_vid_v_h,
2789            gen_helper_vid_v_w, gen_helper_vid_v_d,
2790        };
2791        tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
2792                           cpu_env, s->vlen / 8, s->vlen / 8,
2793                           data, fns[s->sew]);
2794        mark_vs_dirty(s);
2795        gen_set_label(over);
2796        return true;
2797    }
2798    return false;
2799}
2800
2801/*
2802 *** Vector Permutation Instructions
2803 */
2804
2805/* Integer Extract Instruction */
2806
2807static void load_element(TCGv_i64 dest, TCGv_ptr base,
2808                         int ofs, int sew)
2809{
2810    switch (sew) {
2811    case MO_8:
2812        tcg_gen_ld8u_i64(dest, base, ofs);
2813        break;
2814    case MO_16:
2815        tcg_gen_ld16u_i64(dest, base, ofs);
2816        break;
2817    case MO_32:
2818        tcg_gen_ld32u_i64(dest, base, ofs);
2819        break;
2820    case MO_64:
2821        tcg_gen_ld_i64(dest, base, ofs);
2822        break;
2823    default:
2824        g_assert_not_reached();
2825        break;
2826    }
2827}
2828
2829/* offset of the idx element with base regsiter r */
2830static uint32_t endian_ofs(DisasContext *s, int r, int idx)
2831{
2832#ifdef HOST_WORDS_BIGENDIAN
2833    return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
2834#else
2835    return vreg_ofs(s, r) + (idx << s->sew);
2836#endif
2837}
2838
2839/* adjust the index according to the endian */
2840static void endian_adjust(TCGv_i32 ofs, int sew)
2841{
2842#ifdef HOST_WORDS_BIGENDIAN
2843    tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
2844#endif
2845}
2846
2847/* Load idx >= VLMAX ? 0 : vreg[idx] */
2848static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
2849                              int vreg, TCGv idx, int vlmax)
2850{
2851    TCGv_i32 ofs = tcg_temp_new_i32();
2852    TCGv_ptr base = tcg_temp_new_ptr();
2853    TCGv_i64 t_idx = tcg_temp_new_i64();
2854    TCGv_i64 t_vlmax, t_zero;
2855
2856    /*
2857     * Mask the index to the length so that we do
2858     * not produce an out-of-range load.
2859     */
2860    tcg_gen_trunc_tl_i32(ofs, idx);
2861    tcg_gen_andi_i32(ofs, ofs, vlmax - 1);
2862
2863    /* Convert the index to an offset. */
2864    endian_adjust(ofs, s->sew);
2865    tcg_gen_shli_i32(ofs, ofs, s->sew);
2866
2867    /* Convert the index to a pointer. */
2868    tcg_gen_ext_i32_ptr(base, ofs);
2869    tcg_gen_add_ptr(base, base, cpu_env);
2870
2871    /* Perform the load. */
2872    load_element(dest, base,
2873                 vreg_ofs(s, vreg), s->sew);
2874    tcg_temp_free_ptr(base);
2875    tcg_temp_free_i32(ofs);
2876
2877    /* Flush out-of-range indexing to zero.  */
2878    t_vlmax = tcg_constant_i64(vlmax);
2879    t_zero = tcg_constant_i64(0);
2880    tcg_gen_extu_tl_i64(t_idx, idx);
2881
2882    tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx,
2883                        t_vlmax, dest, t_zero);
2884
2885    tcg_temp_free_i64(t_idx);
2886}
2887
2888static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
2889                              int vreg, int idx)
2890{
2891    load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
2892}
2893
2894static bool trans_vext_x_v(DisasContext *s, arg_r *a)
2895{
2896    TCGv_i64 tmp = tcg_temp_new_i64();
2897    TCGv dest = dest_gpr(s, a->rd);
2898
2899    if (a->rs1 == 0) {
2900        /* Special case vmv.x.s rd, vs2. */
2901        vec_element_loadi(s, tmp, a->rs2, 0);
2902    } else {
2903        /* This instruction ignores LMUL and vector register groups */
2904        int vlmax = s->vlen >> (3 + s->sew);
2905        vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
2906    }
2907
2908    tcg_gen_trunc_i64_tl(dest, tmp);
2909    gen_set_gpr(s, a->rd, dest);
2910
2911    tcg_temp_free_i64(tmp);
2912    return true;
2913}
2914
2915/* Integer Scalar Move Instruction */
2916
2917static void store_element(TCGv_i64 val, TCGv_ptr base,
2918                          int ofs, int sew)
2919{
2920    switch (sew) {
2921    case MO_8:
2922        tcg_gen_st8_i64(val, base, ofs);
2923        break;
2924    case MO_16:
2925        tcg_gen_st16_i64(val, base, ofs);
2926        break;
2927    case MO_32:
2928        tcg_gen_st32_i64(val, base, ofs);
2929        break;
2930    case MO_64:
2931        tcg_gen_st_i64(val, base, ofs);
2932        break;
2933    default:
2934        g_assert_not_reached();
2935        break;
2936    }
2937}
2938
2939/*
2940 * Store vreg[idx] = val.
2941 * The index must be in range of VLMAX.
2942 */
2943static void vec_element_storei(DisasContext *s, int vreg,
2944                               int idx, TCGv_i64 val)
2945{
2946    store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
2947}
2948
2949/* vmv.s.x vd, rs1 # vd[0] = rs1 */
2950static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
2951{
2952    if (vext_check_isa_ill(s)) {
2953        /* This instruction ignores LMUL and vector register groups */
2954        int maxsz = s->vlen >> 3;
2955        TCGv_i64 t1;
2956        TCGLabel *over = gen_new_label();
2957
2958        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2959        tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
2960        if (a->rs1 == 0) {
2961            goto done;
2962        }
2963
2964        t1 = tcg_temp_new_i64();
2965        tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
2966        vec_element_storei(s, a->rd, 0, t1);
2967        tcg_temp_free_i64(t1);
2968        mark_vs_dirty(s);
2969    done:
2970        gen_set_label(over);
2971        return true;
2972    }
2973    return false;
2974}
2975
2976/* Floating-Point Scalar Move Instructions */
2977static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
2978{
2979    if (!s->vill && has_ext(s, RVF) &&
2980        (s->mstatus_fs != 0) && (s->sew != 0)) {
2981        unsigned int len = 8 << s->sew;
2982
2983        vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
2984        if (len < 64) {
2985            tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
2986                            MAKE_64BIT_MASK(len, 64 - len));
2987        }
2988
2989        mark_fs_dirty(s);
2990        return true;
2991    }
2992    return false;
2993}
2994
2995/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
2996static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
2997{
2998    if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
2999        TCGv_i64 t1;
3000        /* The instructions ignore LMUL and vector register group. */
3001        uint32_t vlmax = s->vlen >> 3;
3002
3003        /* if vl == 0, skip vector register write back */
3004        TCGLabel *over = gen_new_label();
3005        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
3006
3007        /* zeroed all elements */
3008        tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
3009
3010        /* NaN-box f[rs1] as necessary for SEW */
3011        t1 = tcg_temp_new_i64();
3012        if (s->sew == MO_64 && !has_ext(s, RVD)) {
3013            tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
3014        } else {
3015            tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
3016        }
3017        vec_element_storei(s, a->rd, 0, t1);
3018        tcg_temp_free_i64(t1);
3019        mark_vs_dirty(s);
3020        gen_set_label(over);
3021        return true;
3022    }
3023    return false;
3024}
3025
3026/* Vector Slide Instructions */
3027static bool slideup_check(DisasContext *s, arg_rmrr *a)
3028{
3029    return require_rvv(s) &&
3030           vext_check_isa_ill(s) &&
3031           vext_check_slide(s, a->rd, a->rs2, a->vm, true);
3032}
3033
3034GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
3035GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
3036GEN_OPIVI_TRANS(vslideup_vi, IMM_ZX, vslideup_vx, slideup_check)
3037
3038static bool slidedown_check(DisasContext *s, arg_rmrr *a)
3039{
3040    return require_rvv(s) &&
3041           vext_check_isa_ill(s) &&
3042           vext_check_slide(s, a->rd, a->rs2, a->vm, false);
3043}
3044
3045GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check)
3046GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check)
3047GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
3048
3049/* Vector Register Gather Instruction */
3050static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
3051{
3052    return require_rvv(s) &&
3053           vext_check_isa_ill(s) &&
3054           require_align(a->rd, s->lmul) &&
3055           require_align(a->rs1, s->lmul) &&
3056           require_align(a->rs2, s->lmul) &&
3057           (a->rd != a->rs2 && a->rd != a->rs1) &&
3058           require_vm(a->vm, a->rd);
3059}
3060
3061GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
3062
3063static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
3064{
3065    return require_rvv(s) &&
3066           vext_check_isa_ill(s) &&
3067           require_align(a->rd, s->lmul) &&
3068           require_align(a->rs2, s->lmul) &&
3069           (a->rd != a->rs2) &&
3070           require_vm(a->vm, a->rd);
3071}
3072
3073/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
3074static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
3075{
3076    if (!vrgather_vx_check(s, a)) {
3077        return false;
3078    }
3079
3080    if (a->vm && s->vl_eq_vlmax) {
3081        int vlmax = s->vlen;
3082        TCGv_i64 dest = tcg_temp_new_i64();
3083
3084        if (a->rs1 == 0) {
3085            vec_element_loadi(s, dest, a->rs2, 0);
3086        } else {
3087            vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
3088        }
3089
3090        tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
3091                             MAXSZ(s), MAXSZ(s), dest);
3092        tcg_temp_free_i64(dest);
3093        mark_vs_dirty(s);
3094    } else {
3095        static gen_helper_opivx * const fns[4] = {
3096            gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
3097            gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
3098        };
3099        return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);
3100    }
3101    return true;
3102}
3103
3104/* vrgather.vi vd, vs2, imm, vm # vd[i] = (imm >= VLMAX) ? 0 : vs2[imm] */
3105static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
3106{
3107    if (!vrgather_vx_check(s, a)) {
3108        return false;
3109    }
3110
3111    if (a->vm && s->vl_eq_vlmax) {
3112        if (a->rs1 >= s->vlen) {
3113            tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
3114                                 MAXSZ(s), MAXSZ(s), 0);
3115        } else {
3116            tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd),
3117                                 endian_ofs(s, a->rs2, a->rs1),
3118                                 MAXSZ(s), MAXSZ(s));
3119        }
3120        mark_vs_dirty(s);
3121    } else {
3122        static gen_helper_opivx * const fns[4] = {
3123            gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
3124            gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
3125        };
3126        return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew],
3127                           s, IMM_ZX);
3128    }
3129    return true;
3130}
3131
3132/*
3133 * Vector Compress Instruction
3134 *
3135 * The destination vector register group cannot overlap the
3136 * source vector register group or the source mask register.
3137 */
3138static bool vcompress_vm_check(DisasContext *s, arg_r *a)
3139{
3140    return require_rvv(s) &&
3141           vext_check_isa_ill(s) &&
3142           require_align(a->rd, s->lmul) &&
3143           require_align(a->rs2, s->lmul) &&
3144           (a->rd != a->rs2) &&
3145           !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1);
3146}
3147
3148static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
3149{
3150    if (vcompress_vm_check(s, a)) {
3151        uint32_t data = 0;
3152        static gen_helper_gvec_4_ptr * const fns[4] = {
3153            gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
3154            gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
3155        };
3156        TCGLabel *over = gen_new_label();
3157        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
3158
3159        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
3160        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
3161                           vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
3162                           cpu_env, s->vlen / 8, s->vlen / 8, data,
3163                           fns[s->sew]);
3164        mark_vs_dirty(s);
3165        gen_set_label(over);
3166        return true;
3167    }
3168    return false;
3169}
3170