1/*
2 * RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21static bool trans_illegal(DisasContext *ctx, arg_empty *a)
22{
23    gen_exception_illegal(ctx);
24    return true;
25}
26
27static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
28{
29     REQUIRE_64BIT(ctx);
30     return trans_illegal(ctx, a);
31}
32
33static bool trans_lui(DisasContext *ctx, arg_lui *a)
34{
35    if (a->rd != 0) {
36        tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
37    }
38    return true;
39}
40
41static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
42{
43    if (a->rd != 0) {
44        tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
45    }
46    return true;
47}
48
49static bool trans_jal(DisasContext *ctx, arg_jal *a)
50{
51    gen_jal(ctx, a->rd, a->imm);
52    return true;
53}
54
55static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
56{
57    /* no chaining with JALR */
58    TCGLabel *misaligned = NULL;
59    TCGv t0 = tcg_temp_new();
60
61
62    gen_get_gpr(cpu_pc, a->rs1);
63    tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
64    tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
65
66    if (!has_ext(ctx, RVC)) {
67        misaligned = gen_new_label();
68        tcg_gen_andi_tl(t0, cpu_pc, 0x2);
69        tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
70    }
71
72    if (a->rd != 0) {
73        tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
74    }
75    lookup_and_goto_ptr(ctx);
76
77    if (misaligned) {
78        gen_set_label(misaligned);
79        gen_exception_inst_addr_mis(ctx);
80    }
81    ctx->base.is_jmp = DISAS_NORETURN;
82
83    tcg_temp_free(t0);
84    return true;
85}
86
87static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
88{
89    TCGLabel *l = gen_new_label();
90    TCGv source1, source2;
91    source1 = tcg_temp_new();
92    source2 = tcg_temp_new();
93    gen_get_gpr(source1, a->rs1);
94    gen_get_gpr(source2, a->rs2);
95
96    tcg_gen_brcond_tl(cond, source1, source2, l);
97    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
98    gen_set_label(l); /* branch taken */
99
100    if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
101        /* misaligned */
102        gen_exception_inst_addr_mis(ctx);
103    } else {
104        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
105    }
106    ctx->base.is_jmp = DISAS_NORETURN;
107
108    tcg_temp_free(source1);
109    tcg_temp_free(source2);
110
111    return true;
112}
113
114static bool trans_beq(DisasContext *ctx, arg_beq *a)
115{
116    return gen_branch(ctx, a, TCG_COND_EQ);
117}
118
119static bool trans_bne(DisasContext *ctx, arg_bne *a)
120{
121    return gen_branch(ctx, a, TCG_COND_NE);
122}
123
124static bool trans_blt(DisasContext *ctx, arg_blt *a)
125{
126    return gen_branch(ctx, a, TCG_COND_LT);
127}
128
129static bool trans_bge(DisasContext *ctx, arg_bge *a)
130{
131    return gen_branch(ctx, a, TCG_COND_GE);
132}
133
134static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
135{
136    return gen_branch(ctx, a, TCG_COND_LTU);
137}
138
139static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
140{
141    return gen_branch(ctx, a, TCG_COND_GEU);
142}
143
144static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
145{
146    TCGv t0 = tcg_temp_new();
147    TCGv t1 = tcg_temp_new();
148    gen_get_gpr(t0, a->rs1);
149    tcg_gen_addi_tl(t0, t0, a->imm);
150
151    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
152    gen_set_gpr(a->rd, t1);
153    tcg_temp_free(t0);
154    tcg_temp_free(t1);
155    return true;
156}
157
158static bool trans_lb(DisasContext *ctx, arg_lb *a)
159{
160    return gen_load(ctx, a, MO_SB);
161}
162
163static bool trans_lh(DisasContext *ctx, arg_lh *a)
164{
165    return gen_load(ctx, a, MO_TESW);
166}
167
168static bool trans_lw(DisasContext *ctx, arg_lw *a)
169{
170    return gen_load(ctx, a, MO_TESL);
171}
172
173static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
174{
175    return gen_load(ctx, a, MO_UB);
176}
177
178static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
179{
180    return gen_load(ctx, a, MO_TEUW);
181}
182
183static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
184{
185    TCGv t0 = tcg_temp_new();
186    TCGv dat = tcg_temp_new();
187    gen_get_gpr(t0, a->rs1);
188    tcg_gen_addi_tl(t0, t0, a->imm);
189    gen_get_gpr(dat, a->rs2);
190
191    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
192    tcg_temp_free(t0);
193    tcg_temp_free(dat);
194    return true;
195}
196
197
198static bool trans_sb(DisasContext *ctx, arg_sb *a)
199{
200    return gen_store(ctx, a, MO_SB);
201}
202
203static bool trans_sh(DisasContext *ctx, arg_sh *a)
204{
205    return gen_store(ctx, a, MO_TESW);
206}
207
208static bool trans_sw(DisasContext *ctx, arg_sw *a)
209{
210    return gen_store(ctx, a, MO_TESL);
211}
212
213static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
214{
215    REQUIRE_64BIT(ctx);
216    return gen_load(ctx, a, MO_TEUL);
217}
218
219static bool trans_ld(DisasContext *ctx, arg_ld *a)
220{
221    REQUIRE_64BIT(ctx);
222    return gen_load(ctx, a, MO_TEQ);
223}
224
225static bool trans_sd(DisasContext *ctx, arg_sd *a)
226{
227    REQUIRE_64BIT(ctx);
228    return gen_store(ctx, a, MO_TEQ);
229}
230
231static bool trans_addi(DisasContext *ctx, arg_addi *a)
232{
233    return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
234}
235
236static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
237{
238    tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
239}
240
241static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
242{
243    tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
244}
245
246
247static bool trans_slti(DisasContext *ctx, arg_slti *a)
248{
249    return gen_arith_imm_tl(ctx, a, &gen_slt);
250}
251
252static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
253{
254    return gen_arith_imm_tl(ctx, a, &gen_sltu);
255}
256
257static bool trans_xori(DisasContext *ctx, arg_xori *a)
258{
259    return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
260}
261static bool trans_ori(DisasContext *ctx, arg_ori *a)
262{
263    return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
264}
265static bool trans_andi(DisasContext *ctx, arg_andi *a)
266{
267    return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
268}
269static bool trans_slli(DisasContext *ctx, arg_slli *a)
270{
271    return gen_shifti(ctx, a, tcg_gen_shl_tl);
272}
273
274static bool trans_srli(DisasContext *ctx, arg_srli *a)
275{
276    return gen_shifti(ctx, a, tcg_gen_shr_tl);
277}
278
279static bool trans_srai(DisasContext *ctx, arg_srai *a)
280{
281    return gen_shifti(ctx, a, tcg_gen_sar_tl);
282}
283
284static bool trans_add(DisasContext *ctx, arg_add *a)
285{
286    return gen_arith(ctx, a, &tcg_gen_add_tl);
287}
288
289static bool trans_sub(DisasContext *ctx, arg_sub *a)
290{
291    return gen_arith(ctx, a, &tcg_gen_sub_tl);
292}
293
294static bool trans_sll(DisasContext *ctx, arg_sll *a)
295{
296    return gen_shift(ctx, a, &tcg_gen_shl_tl);
297}
298
299static bool trans_slt(DisasContext *ctx, arg_slt *a)
300{
301    return gen_arith(ctx, a, &gen_slt);
302}
303
304static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
305{
306    return gen_arith(ctx, a, &gen_sltu);
307}
308
309static bool trans_xor(DisasContext *ctx, arg_xor *a)
310{
311    return gen_arith(ctx, a, &tcg_gen_xor_tl);
312}
313
314static bool trans_srl(DisasContext *ctx, arg_srl *a)
315{
316    return gen_shift(ctx, a, &tcg_gen_shr_tl);
317}
318
319static bool trans_sra(DisasContext *ctx, arg_sra *a)
320{
321    return gen_shift(ctx, a, &tcg_gen_sar_tl);
322}
323
324static bool trans_or(DisasContext *ctx, arg_or *a)
325{
326    return gen_arith(ctx, a, &tcg_gen_or_tl);
327}
328
329static bool trans_and(DisasContext *ctx, arg_and *a)
330{
331    return gen_arith(ctx, a, &tcg_gen_and_tl);
332}
333
334static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
335{
336    REQUIRE_64BIT(ctx);
337    return gen_arith_imm_tl(ctx, a, &gen_addw);
338}
339
340static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
341{
342    REQUIRE_64BIT(ctx);
343    return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
344}
345
346static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
347{
348    REQUIRE_64BIT(ctx);
349    TCGv t = tcg_temp_new();
350    gen_get_gpr(t, a->rs1);
351    tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
352    /* sign-extend for W instructions */
353    tcg_gen_ext32s_tl(t, t);
354    gen_set_gpr(a->rd, t);
355    tcg_temp_free(t);
356    return true;
357}
358
359static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
360{
361    REQUIRE_64BIT(ctx);
362    TCGv t = tcg_temp_new();
363    gen_get_gpr(t, a->rs1);
364    tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
365    gen_set_gpr(a->rd, t);
366    tcg_temp_free(t);
367    return true;
368}
369
370static bool trans_addw(DisasContext *ctx, arg_addw *a)
371{
372    REQUIRE_64BIT(ctx);
373    return gen_arith(ctx, a, &gen_addw);
374}
375
376static bool trans_subw(DisasContext *ctx, arg_subw *a)
377{
378    REQUIRE_64BIT(ctx);
379    return gen_arith(ctx, a, &gen_subw);
380}
381
382static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
383{
384    REQUIRE_64BIT(ctx);
385    TCGv source1 = tcg_temp_new();
386    TCGv source2 = tcg_temp_new();
387
388    gen_get_gpr(source1, a->rs1);
389    gen_get_gpr(source2, a->rs2);
390
391    tcg_gen_andi_tl(source2, source2, 0x1F);
392    tcg_gen_shl_tl(source1, source1, source2);
393
394    tcg_gen_ext32s_tl(source1, source1);
395    gen_set_gpr(a->rd, source1);
396    tcg_temp_free(source1);
397    tcg_temp_free(source2);
398    return true;
399}
400
401static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
402{
403    REQUIRE_64BIT(ctx);
404    TCGv source1 = tcg_temp_new();
405    TCGv source2 = tcg_temp_new();
406
407    gen_get_gpr(source1, a->rs1);
408    gen_get_gpr(source2, a->rs2);
409
410    /* clear upper 32 */
411    tcg_gen_ext32u_tl(source1, source1);
412    tcg_gen_andi_tl(source2, source2, 0x1F);
413    tcg_gen_shr_tl(source1, source1, source2);
414
415    tcg_gen_ext32s_tl(source1, source1);
416    gen_set_gpr(a->rd, source1);
417    tcg_temp_free(source1);
418    tcg_temp_free(source2);
419    return true;
420}
421
422static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
423{
424    REQUIRE_64BIT(ctx);
425    TCGv source1 = tcg_temp_new();
426    TCGv source2 = tcg_temp_new();
427
428    gen_get_gpr(source1, a->rs1);
429    gen_get_gpr(source2, a->rs2);
430
431    /*
432     * first, trick to get it to act like working on 32 bits (get rid of
433     * upper 32, sign extend to fill space)
434     */
435    tcg_gen_ext32s_tl(source1, source1);
436    tcg_gen_andi_tl(source2, source2, 0x1F);
437    tcg_gen_sar_tl(source1, source1, source2);
438
439    gen_set_gpr(a->rd, source1);
440    tcg_temp_free(source1);
441    tcg_temp_free(source2);
442
443    return true;
444}
445
446static bool trans_fence(DisasContext *ctx, arg_fence *a)
447{
448    /* FENCE is a full memory barrier. */
449    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
450    return true;
451}
452
453static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
454{
455    if (!ctx->ext_ifencei) {
456        return false;
457    }
458
459    /*
460     * FENCE_I is a no-op in QEMU,
461     * however we need to end the translation block
462     */
463    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
464    exit_tb(ctx);
465    ctx->base.is_jmp = DISAS_NORETURN;
466    return true;
467}
468
469#define RISCV_OP_CSR_PRE do {\
470    source1 = tcg_temp_new(); \
471    csr_store = tcg_temp_new(); \
472    dest = tcg_temp_new(); \
473    rs1_pass = tcg_temp_new(); \
474    gen_get_gpr(source1, a->rs1); \
475    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
476    tcg_gen_movi_tl(rs1_pass, a->rs1); \
477    tcg_gen_movi_tl(csr_store, a->csr); \
478    gen_io_start();\
479} while (0)
480
481#define RISCV_OP_CSR_POST do {\
482    gen_set_gpr(a->rd, dest); \
483    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
484    exit_tb(ctx); \
485    ctx->base.is_jmp = DISAS_NORETURN; \
486    tcg_temp_free(source1); \
487    tcg_temp_free(csr_store); \
488    tcg_temp_free(dest); \
489    tcg_temp_free(rs1_pass); \
490} while (0)
491
492
493static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
494{
495    TCGv source1, csr_store, dest, rs1_pass;
496    RISCV_OP_CSR_PRE;
497    gen_helper_csrrw(dest, cpu_env, source1, csr_store);
498    RISCV_OP_CSR_POST;
499    return true;
500}
501
502static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
503{
504    TCGv source1, csr_store, dest, rs1_pass;
505    RISCV_OP_CSR_PRE;
506    gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
507    RISCV_OP_CSR_POST;
508    return true;
509}
510
511static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
512{
513    TCGv source1, csr_store, dest, rs1_pass;
514    RISCV_OP_CSR_PRE;
515    gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
516    RISCV_OP_CSR_POST;
517    return true;
518}
519
520static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
521{
522    TCGv source1, csr_store, dest, rs1_pass;
523    RISCV_OP_CSR_PRE;
524    gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
525    RISCV_OP_CSR_POST;
526    return true;
527}
528
529static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
530{
531    TCGv source1, csr_store, dest, rs1_pass;
532    RISCV_OP_CSR_PRE;
533    gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
534    RISCV_OP_CSR_POST;
535    return true;
536}
537
538static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
539{
540    TCGv source1, csr_store, dest, rs1_pass;
541    RISCV_OP_CSR_PRE;
542    gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
543    RISCV_OP_CSR_POST;
544    return true;
545}
546