1/*
2 * RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21static bool trans_illegal(DisasContext *ctx, arg_empty *a)
22{
23    gen_exception_illegal(ctx);
24    return true;
25}
26
27static bool trans_lui(DisasContext *ctx, arg_lui *a)
28{
29    if (a->rd != 0) {
30        tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
31    }
32    return true;
33}
34
35static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
36{
37    if (a->rd != 0) {
38        tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
39    }
40    return true;
41}
42
43static bool trans_jal(DisasContext *ctx, arg_jal *a)
44{
45    gen_jal(ctx, a->rd, a->imm);
46    return true;
47}
48
49static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
50{
51    /* no chaining with JALR */
52    TCGLabel *misaligned = NULL;
53    TCGv t0 = tcg_temp_new();
54
55
56    gen_get_gpr(cpu_pc, a->rs1);
57    tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
58    tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
59
60    if (!has_ext(ctx, RVC)) {
61        misaligned = gen_new_label();
62        tcg_gen_andi_tl(t0, cpu_pc, 0x2);
63        tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
64    }
65
66    if (a->rd != 0) {
67        tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
68    }
69    lookup_and_goto_ptr(ctx);
70
71    if (misaligned) {
72        gen_set_label(misaligned);
73        gen_exception_inst_addr_mis(ctx);
74    }
75    ctx->base.is_jmp = DISAS_NORETURN;
76
77    tcg_temp_free(t0);
78    return true;
79}
80
81static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
82{
83    TCGLabel *l = gen_new_label();
84    TCGv source1, source2;
85    source1 = tcg_temp_new();
86    source2 = tcg_temp_new();
87    gen_get_gpr(source1, a->rs1);
88    gen_get_gpr(source2, a->rs2);
89
90    tcg_gen_brcond_tl(cond, source1, source2, l);
91    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
92    gen_set_label(l); /* branch taken */
93
94    if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
95        /* misaligned */
96        gen_exception_inst_addr_mis(ctx);
97    } else {
98        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
99    }
100    ctx->base.is_jmp = DISAS_NORETURN;
101
102    tcg_temp_free(source1);
103    tcg_temp_free(source2);
104
105    return true;
106}
107
108static bool trans_beq(DisasContext *ctx, arg_beq *a)
109{
110    return gen_branch(ctx, a, TCG_COND_EQ);
111}
112
113static bool trans_bne(DisasContext *ctx, arg_bne *a)
114{
115    return gen_branch(ctx, a, TCG_COND_NE);
116}
117
118static bool trans_blt(DisasContext *ctx, arg_blt *a)
119{
120    return gen_branch(ctx, a, TCG_COND_LT);
121}
122
123static bool trans_bge(DisasContext *ctx, arg_bge *a)
124{
125    return gen_branch(ctx, a, TCG_COND_GE);
126}
127
128static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
129{
130    return gen_branch(ctx, a, TCG_COND_LTU);
131}
132
133static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
134{
135    return gen_branch(ctx, a, TCG_COND_GEU);
136}
137
138static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
139{
140    TCGv t0 = tcg_temp_new();
141    TCGv t1 = tcg_temp_new();
142    gen_get_gpr(t0, a->rs1);
143    tcg_gen_addi_tl(t0, t0, a->imm);
144
145    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
146    gen_set_gpr(a->rd, t1);
147    tcg_temp_free(t0);
148    tcg_temp_free(t1);
149    return true;
150}
151
152static bool trans_lb(DisasContext *ctx, arg_lb *a)
153{
154    return gen_load(ctx, a, MO_SB);
155}
156
157static bool trans_lh(DisasContext *ctx, arg_lh *a)
158{
159    return gen_load(ctx, a, MO_TESW);
160}
161
162static bool trans_lw(DisasContext *ctx, arg_lw *a)
163{
164    return gen_load(ctx, a, MO_TESL);
165}
166
167static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
168{
169    return gen_load(ctx, a, MO_UB);
170}
171
172static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
173{
174    return gen_load(ctx, a, MO_TEUW);
175}
176
177static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
178{
179    TCGv t0 = tcg_temp_new();
180    TCGv dat = tcg_temp_new();
181    gen_get_gpr(t0, a->rs1);
182    tcg_gen_addi_tl(t0, t0, a->imm);
183    gen_get_gpr(dat, a->rs2);
184
185    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
186    tcg_temp_free(t0);
187    tcg_temp_free(dat);
188    return true;
189}
190
191
192static bool trans_sb(DisasContext *ctx, arg_sb *a)
193{
194    return gen_store(ctx, a, MO_SB);
195}
196
197static bool trans_sh(DisasContext *ctx, arg_sh *a)
198{
199    return gen_store(ctx, a, MO_TESW);
200}
201
202static bool trans_sw(DisasContext *ctx, arg_sw *a)
203{
204    return gen_store(ctx, a, MO_TESL);
205}
206
207static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
208{
209    REQUIRE_64BIT(ctx);
210    return gen_load(ctx, a, MO_TEUL);
211}
212
213static bool trans_ld(DisasContext *ctx, arg_ld *a)
214{
215    REQUIRE_64BIT(ctx);
216    return gen_load(ctx, a, MO_TEQ);
217}
218
219static bool trans_sd(DisasContext *ctx, arg_sd *a)
220{
221    REQUIRE_64BIT(ctx);
222    return gen_store(ctx, a, MO_TEQ);
223}
224
225static bool trans_addi(DisasContext *ctx, arg_addi *a)
226{
227    return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
228}
229
230static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
231{
232    tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
233}
234
235static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
236{
237    tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
238}
239
240
241static bool trans_slti(DisasContext *ctx, arg_slti *a)
242{
243    return gen_arith_imm_tl(ctx, a, &gen_slt);
244}
245
246static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
247{
248    return gen_arith_imm_tl(ctx, a, &gen_sltu);
249}
250
251static bool trans_xori(DisasContext *ctx, arg_xori *a)
252{
253    return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
254}
255static bool trans_ori(DisasContext *ctx, arg_ori *a)
256{
257    return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
258}
259static bool trans_andi(DisasContext *ctx, arg_andi *a)
260{
261    return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
262}
263static bool trans_slli(DisasContext *ctx, arg_slli *a)
264{
265    if (a->shamt >= TARGET_LONG_BITS) {
266        return false;
267    }
268
269    if (a->rd != 0) {
270        TCGv t = tcg_temp_new();
271        gen_get_gpr(t, a->rs1);
272
273        tcg_gen_shli_tl(t, t, a->shamt);
274
275        gen_set_gpr(a->rd, t);
276        tcg_temp_free(t);
277    } /* NOP otherwise */
278    return true;
279}
280
281static bool trans_srli(DisasContext *ctx, arg_srli *a)
282{
283    if (a->shamt >= TARGET_LONG_BITS) {
284        return false;
285    }
286
287    if (a->rd != 0) {
288        TCGv t = tcg_temp_new();
289        gen_get_gpr(t, a->rs1);
290
291        tcg_gen_shri_tl(t, t, a->shamt);
292        gen_set_gpr(a->rd, t);
293        tcg_temp_free(t);
294    } /* NOP otherwise */
295    return true;
296}
297
298static bool trans_srai(DisasContext *ctx, arg_srai *a)
299{
300    if (a->shamt >= TARGET_LONG_BITS) {
301        return false;
302    }
303
304    if (a->rd != 0) {
305        TCGv t = tcg_temp_new();
306        gen_get_gpr(t, a->rs1);
307
308        tcg_gen_sari_tl(t, t, a->shamt);
309        gen_set_gpr(a->rd, t);
310        tcg_temp_free(t);
311    } /* NOP otherwise */
312    return true;
313}
314
315static bool trans_add(DisasContext *ctx, arg_add *a)
316{
317    return gen_arith(ctx, a, &tcg_gen_add_tl);
318}
319
320static bool trans_sub(DisasContext *ctx, arg_sub *a)
321{
322    return gen_arith(ctx, a, &tcg_gen_sub_tl);
323}
324
325static bool trans_sll(DisasContext *ctx, arg_sll *a)
326{
327    return gen_shift(ctx, a, &tcg_gen_shl_tl);
328}
329
330static bool trans_slt(DisasContext *ctx, arg_slt *a)
331{
332    return gen_arith(ctx, a, &gen_slt);
333}
334
335static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
336{
337    return gen_arith(ctx, a, &gen_sltu);
338}
339
340static bool trans_xor(DisasContext *ctx, arg_xor *a)
341{
342    return gen_arith(ctx, a, &tcg_gen_xor_tl);
343}
344
345static bool trans_srl(DisasContext *ctx, arg_srl *a)
346{
347    return gen_shift(ctx, a, &tcg_gen_shr_tl);
348}
349
350static bool trans_sra(DisasContext *ctx, arg_sra *a)
351{
352    return gen_shift(ctx, a, &tcg_gen_sar_tl);
353}
354
355static bool trans_or(DisasContext *ctx, arg_or *a)
356{
357    return gen_arith(ctx, a, &tcg_gen_or_tl);
358}
359
360static bool trans_and(DisasContext *ctx, arg_and *a)
361{
362    return gen_arith(ctx, a, &tcg_gen_and_tl);
363}
364
365static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
366{
367    REQUIRE_64BIT(ctx);
368    return gen_arith_imm_tl(ctx, a, &gen_addw);
369}
370
371static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
372{
373    REQUIRE_64BIT(ctx);
374    TCGv source1;
375    source1 = tcg_temp_new();
376    gen_get_gpr(source1, a->rs1);
377
378    tcg_gen_shli_tl(source1, source1, a->shamt);
379    tcg_gen_ext32s_tl(source1, source1);
380    gen_set_gpr(a->rd, source1);
381
382    tcg_temp_free(source1);
383    return true;
384}
385
386static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
387{
388    REQUIRE_64BIT(ctx);
389    TCGv t = tcg_temp_new();
390    gen_get_gpr(t, a->rs1);
391    tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
392    /* sign-extend for W instructions */
393    tcg_gen_ext32s_tl(t, t);
394    gen_set_gpr(a->rd, t);
395    tcg_temp_free(t);
396    return true;
397}
398
399static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
400{
401    REQUIRE_64BIT(ctx);
402    TCGv t = tcg_temp_new();
403    gen_get_gpr(t, a->rs1);
404    tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
405    gen_set_gpr(a->rd, t);
406    tcg_temp_free(t);
407    return true;
408}
409
410static bool trans_addw(DisasContext *ctx, arg_addw *a)
411{
412    REQUIRE_64BIT(ctx);
413    return gen_arith(ctx, a, &gen_addw);
414}
415
416static bool trans_subw(DisasContext *ctx, arg_subw *a)
417{
418    REQUIRE_64BIT(ctx);
419    return gen_arith(ctx, a, &gen_subw);
420}
421
422static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
423{
424    REQUIRE_64BIT(ctx);
425    TCGv source1 = tcg_temp_new();
426    TCGv source2 = tcg_temp_new();
427
428    gen_get_gpr(source1, a->rs1);
429    gen_get_gpr(source2, a->rs2);
430
431    tcg_gen_andi_tl(source2, source2, 0x1F);
432    tcg_gen_shl_tl(source1, source1, source2);
433
434    tcg_gen_ext32s_tl(source1, source1);
435    gen_set_gpr(a->rd, source1);
436    tcg_temp_free(source1);
437    tcg_temp_free(source2);
438    return true;
439}
440
441static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
442{
443    REQUIRE_64BIT(ctx);
444    TCGv source1 = tcg_temp_new();
445    TCGv source2 = tcg_temp_new();
446
447    gen_get_gpr(source1, a->rs1);
448    gen_get_gpr(source2, a->rs2);
449
450    /* clear upper 32 */
451    tcg_gen_ext32u_tl(source1, source1);
452    tcg_gen_andi_tl(source2, source2, 0x1F);
453    tcg_gen_shr_tl(source1, source1, source2);
454
455    tcg_gen_ext32s_tl(source1, source1);
456    gen_set_gpr(a->rd, source1);
457    tcg_temp_free(source1);
458    tcg_temp_free(source2);
459    return true;
460}
461
462static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
463{
464    REQUIRE_64BIT(ctx);
465    TCGv source1 = tcg_temp_new();
466    TCGv source2 = tcg_temp_new();
467
468    gen_get_gpr(source1, a->rs1);
469    gen_get_gpr(source2, a->rs2);
470
471    /*
472     * first, trick to get it to act like working on 32 bits (get rid of
473     * upper 32, sign extend to fill space)
474     */
475    tcg_gen_ext32s_tl(source1, source1);
476    tcg_gen_andi_tl(source2, source2, 0x1F);
477    tcg_gen_sar_tl(source1, source1, source2);
478
479    gen_set_gpr(a->rd, source1);
480    tcg_temp_free(source1);
481    tcg_temp_free(source2);
482
483    return true;
484}
485
486static bool trans_fence(DisasContext *ctx, arg_fence *a)
487{
488    /* FENCE is a full memory barrier. */
489    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
490    return true;
491}
492
493static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
494{
495    if (!ctx->ext_ifencei) {
496        return false;
497    }
498
499    /*
500     * FENCE_I is a no-op in QEMU,
501     * however we need to end the translation block
502     */
503    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
504    exit_tb(ctx);
505    ctx->base.is_jmp = DISAS_NORETURN;
506    return true;
507}
508
509#define RISCV_OP_CSR_PRE do {\
510    source1 = tcg_temp_new(); \
511    csr_store = tcg_temp_new(); \
512    dest = tcg_temp_new(); \
513    rs1_pass = tcg_temp_new(); \
514    gen_get_gpr(source1, a->rs1); \
515    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
516    tcg_gen_movi_tl(rs1_pass, a->rs1); \
517    tcg_gen_movi_tl(csr_store, a->csr); \
518    gen_io_start();\
519} while (0)
520
521#define RISCV_OP_CSR_POST do {\
522    gen_set_gpr(a->rd, dest); \
523    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
524    exit_tb(ctx); \
525    ctx->base.is_jmp = DISAS_NORETURN; \
526    tcg_temp_free(source1); \
527    tcg_temp_free(csr_store); \
528    tcg_temp_free(dest); \
529    tcg_temp_free(rs1_pass); \
530} while (0)
531
532
533static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
534{
535    TCGv source1, csr_store, dest, rs1_pass;
536    RISCV_OP_CSR_PRE;
537    gen_helper_csrrw(dest, cpu_env, source1, csr_store);
538    RISCV_OP_CSR_POST;
539    return true;
540}
541
542static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
543{
544    TCGv source1, csr_store, dest, rs1_pass;
545    RISCV_OP_CSR_PRE;
546    gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
547    RISCV_OP_CSR_POST;
548    return true;
549}
550
551static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
552{
553    TCGv source1, csr_store, dest, rs1_pass;
554    RISCV_OP_CSR_PRE;
555    gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
556    RISCV_OP_CSR_POST;
557    return true;
558}
559
560static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
561{
562    TCGv source1, csr_store, dest, rs1_pass;
563    RISCV_OP_CSR_PRE;
564    gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
565    RISCV_OP_CSR_POST;
566    return true;
567}
568
569static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
570{
571    TCGv source1, csr_store, dest, rs1_pass;
572    RISCV_OP_CSR_PRE;
573    gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
574    RISCV_OP_CSR_POST;
575    return true;
576}
577
578static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
579{
580    TCGv source1, csr_store, dest, rs1_pass;
581    RISCV_OP_CSR_PRE;
582    gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
583    RISCV_OP_CSR_POST;
584    return true;
585}
586