1/*
2 * RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21static bool trans_illegal(DisasContext *ctx, arg_empty *a)
22{
23    gen_exception_illegal(ctx);
24    return true;
25}
26
27static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
28{
29    REQUIRE_64_OR_128BIT(ctx);
30    return trans_illegal(ctx, a);
31}
32
33static bool trans_lui(DisasContext *ctx, arg_lui *a)
34{
35    if (a->rd != 0) {
36        gen_set_gpri(ctx, a->rd, a->imm);
37    }
38    return true;
39}
40
41static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
42{
43    if (a->rd != 0) {
44        gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
45    }
46    return true;
47}
48
49static bool trans_jal(DisasContext *ctx, arg_jal *a)
50{
51    gen_jal(ctx, a->rd, a->imm);
52    return true;
53}
54
55static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
56{
57    TCGLabel *misaligned = NULL;
58
59    tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
60    tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
61
62    if (!has_ext(ctx, RVC)) {
63        TCGv t0 = tcg_temp_new();
64
65        misaligned = gen_new_label();
66        tcg_gen_andi_tl(t0, cpu_pc, 0x2);
67        tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
68        tcg_temp_free(t0);
69    }
70
71    gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
72    tcg_gen_lookup_and_goto_ptr();
73
74    if (misaligned) {
75        gen_set_label(misaligned);
76        gen_exception_inst_addr_mis(ctx);
77    }
78    ctx->base.is_jmp = DISAS_NORETURN;
79
80    return true;
81}
82
83static TCGCond gen_compare_i128(bool bz, TCGv rl,
84                                TCGv al, TCGv ah, TCGv bl, TCGv bh,
85                                TCGCond cond)
86{
87    TCGv rh = tcg_temp_new();
88    bool invert = false;
89
90    switch (cond) {
91    case TCG_COND_EQ:
92    case TCG_COND_NE:
93        if (bz) {
94            tcg_gen_or_tl(rl, al, ah);
95        } else {
96            tcg_gen_xor_tl(rl, al, bl);
97            tcg_gen_xor_tl(rh, ah, bh);
98            tcg_gen_or_tl(rl, rl, rh);
99        }
100        break;
101
102    case TCG_COND_GE:
103    case TCG_COND_LT:
104        if (bz) {
105            tcg_gen_mov_tl(rl, ah);
106        } else {
107            TCGv tmp = tcg_temp_new();
108
109            tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh);
110            tcg_gen_xor_tl(rl, rh, ah);
111            tcg_gen_xor_tl(tmp, ah, bh);
112            tcg_gen_and_tl(rl, rl, tmp);
113            tcg_gen_xor_tl(rl, rh, rl);
114
115            tcg_temp_free(tmp);
116        }
117        break;
118
119    case TCG_COND_LTU:
120        invert = true;
121        /* fallthrough */
122    case TCG_COND_GEU:
123        {
124            TCGv tmp = tcg_temp_new();
125            TCGv zero = tcg_constant_tl(0);
126            TCGv one = tcg_constant_tl(1);
127
128            cond = TCG_COND_NE;
129            /* borrow in to second word */
130            tcg_gen_setcond_tl(TCG_COND_LTU, tmp, al, bl);
131            /* seed third word with 1, which will be result */
132            tcg_gen_sub2_tl(tmp, rh, ah, one, tmp, zero);
133            tcg_gen_sub2_tl(tmp, rl, tmp, rh, bh, zero);
134
135            tcg_temp_free(tmp);
136        }
137        break;
138
139    default:
140        g_assert_not_reached();
141    }
142
143    if (invert) {
144        cond = tcg_invert_cond(cond);
145    }
146
147    tcg_temp_free(rh);
148    return cond;
149}
150
151static void gen_setcond_i128(TCGv rl, TCGv rh,
152                             TCGv src1l, TCGv src1h,
153                             TCGv src2l, TCGv src2h,
154                             TCGCond cond)
155{
156    cond = gen_compare_i128(false, rl, src1l, src1h, src2l, src2h, cond);
157    tcg_gen_setcondi_tl(cond, rl, rl, 0);
158    tcg_gen_movi_tl(rh, 0);
159}
160
161static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
162{
163    TCGLabel *l = gen_new_label();
164    TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
165    TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
166
167    if (get_xl(ctx) == MXL_RV128) {
168        TCGv src1h = get_gprh(ctx, a->rs1);
169        TCGv src2h = get_gprh(ctx, a->rs2);
170        TCGv tmp = tcg_temp_new();
171
172        cond = gen_compare_i128(a->rs2 == 0,
173                                tmp, src1, src1h, src2, src2h, cond);
174        tcg_gen_brcondi_tl(cond, tmp, 0, l);
175
176        tcg_temp_free(tmp);
177    } else {
178        tcg_gen_brcond_tl(cond, src1, src2, l);
179    }
180    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
181
182    gen_set_label(l); /* branch taken */
183
184    if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
185        /* misaligned */
186        gen_exception_inst_addr_mis(ctx);
187    } else {
188        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
189    }
190    ctx->base.is_jmp = DISAS_NORETURN;
191
192    return true;
193}
194
195static bool trans_beq(DisasContext *ctx, arg_beq *a)
196{
197    return gen_branch(ctx, a, TCG_COND_EQ);
198}
199
200static bool trans_bne(DisasContext *ctx, arg_bne *a)
201{
202    return gen_branch(ctx, a, TCG_COND_NE);
203}
204
205static bool trans_blt(DisasContext *ctx, arg_blt *a)
206{
207    return gen_branch(ctx, a, TCG_COND_LT);
208}
209
210static bool trans_bge(DisasContext *ctx, arg_bge *a)
211{
212    return gen_branch(ctx, a, TCG_COND_GE);
213}
214
215static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
216{
217    return gen_branch(ctx, a, TCG_COND_LTU);
218}
219
220static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
221{
222    return gen_branch(ctx, a, TCG_COND_GEU);
223}
224
225static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
226{
227    TCGv dest = dest_gpr(ctx, a->rd);
228    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
229
230    if (a->imm) {
231        TCGv temp = temp_new(ctx);
232        tcg_gen_addi_tl(temp, addr, a->imm);
233        addr = temp;
234    }
235    addr = gen_pm_adjust_address(ctx, addr);
236
237    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
238    gen_set_gpr(ctx, a->rd, dest);
239    return true;
240}
241
242/* Compute only 64-bit addresses to use the address translation mechanism */
243static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
244{
245    TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
246    TCGv destl = dest_gpr(ctx, a->rd);
247    TCGv desth = dest_gprh(ctx, a->rd);
248    TCGv addrl = tcg_temp_new();
249
250    tcg_gen_addi_tl(addrl, src1l, a->imm);
251
252    if ((memop & MO_SIZE) <= MO_64) {
253        tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop);
254        if (memop & MO_SIGN) {
255            tcg_gen_sari_tl(desth, destl, 63);
256        } else {
257            tcg_gen_movi_tl(desth, 0);
258        }
259    } else {
260        /* assume little-endian memory access for now */
261        tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ);
262        tcg_gen_addi_tl(addrl, addrl, 8);
263        tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ);
264    }
265
266    gen_set_gpr128(ctx, a->rd, destl, desth);
267
268    tcg_temp_free(addrl);
269    return true;
270}
271
272static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
273{
274    if (get_xl(ctx) == MXL_RV128) {
275        return gen_load_i128(ctx, a, memop);
276    } else {
277        return gen_load_tl(ctx, a, memop);
278    }
279}
280
281static bool trans_lb(DisasContext *ctx, arg_lb *a)
282{
283    return gen_load(ctx, a, MO_SB);
284}
285
286static bool trans_lh(DisasContext *ctx, arg_lh *a)
287{
288    return gen_load(ctx, a, MO_TESW);
289}
290
291static bool trans_lw(DisasContext *ctx, arg_lw *a)
292{
293    return gen_load(ctx, a, MO_TESL);
294}
295
296static bool trans_ld(DisasContext *ctx, arg_ld *a)
297{
298    REQUIRE_64_OR_128BIT(ctx);
299    return gen_load(ctx, a, MO_TESQ);
300}
301
302static bool trans_lq(DisasContext *ctx, arg_lq *a)
303{
304    REQUIRE_128BIT(ctx);
305    return gen_load(ctx, a, MO_TEUO);
306}
307
308static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
309{
310    return gen_load(ctx, a, MO_UB);
311}
312
313static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
314{
315    return gen_load(ctx, a, MO_TEUW);
316}
317
318static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
319{
320    REQUIRE_64_OR_128BIT(ctx);
321    return gen_load(ctx, a, MO_TEUL);
322}
323
324static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
325{
326    REQUIRE_128BIT(ctx);
327    return gen_load(ctx, a, MO_TEUQ);
328}
329
330static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
331{
332    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
333    TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
334
335    if (a->imm) {
336        TCGv temp = temp_new(ctx);
337        tcg_gen_addi_tl(temp, addr, a->imm);
338        addr = temp;
339    }
340    addr = gen_pm_adjust_address(ctx, addr);
341
342    tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
343    return true;
344}
345
346static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
347{
348    TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
349    TCGv src2l = get_gpr(ctx, a->rs2, EXT_NONE);
350    TCGv src2h = get_gprh(ctx, a->rs2);
351    TCGv addrl = tcg_temp_new();
352
353    tcg_gen_addi_tl(addrl, src1l, a->imm);
354
355    if ((memop & MO_SIZE) <= MO_64) {
356        tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop);
357    } else {
358        /* little-endian memory access assumed for now */
359        tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, MO_TEUQ);
360        tcg_gen_addi_tl(addrl, addrl, 8);
361        tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ);
362    }
363
364    tcg_temp_free(addrl);
365    return true;
366}
367
368static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
369{
370    if (get_xl(ctx) == MXL_RV128) {
371        return gen_store_i128(ctx, a, memop);
372    } else {
373        return gen_store_tl(ctx, a, memop);
374    }
375}
376
377static bool trans_sb(DisasContext *ctx, arg_sb *a)
378{
379    return gen_store(ctx, a, MO_SB);
380}
381
382static bool trans_sh(DisasContext *ctx, arg_sh *a)
383{
384    return gen_store(ctx, a, MO_TESW);
385}
386
387static bool trans_sw(DisasContext *ctx, arg_sw *a)
388{
389    return gen_store(ctx, a, MO_TESL);
390}
391
392static bool trans_sd(DisasContext *ctx, arg_sd *a)
393{
394    REQUIRE_64_OR_128BIT(ctx);
395    return gen_store(ctx, a, MO_TEUQ);
396}
397
398static bool trans_sq(DisasContext *ctx, arg_sq *a)
399{
400    REQUIRE_128BIT(ctx);
401    return gen_store(ctx, a, MO_TEUO);
402}
403
404static bool trans_addd(DisasContext *ctx, arg_addd *a)
405{
406    REQUIRE_128BIT(ctx);
407    ctx->ol = MXL_RV64;
408    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, NULL);
409}
410
411static bool trans_addid(DisasContext *ctx, arg_addid *a)
412{
413    REQUIRE_128BIT(ctx);
414    ctx->ol = MXL_RV64;
415    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, NULL);
416}
417
418static bool trans_subd(DisasContext *ctx, arg_subd *a)
419{
420    REQUIRE_128BIT(ctx);
421    ctx->ol = MXL_RV64;
422    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, NULL);
423}
424
425static void gen_addi2_i128(TCGv retl, TCGv reth,
426                           TCGv srcl, TCGv srch, target_long imm)
427{
428    TCGv imml  = tcg_constant_tl(imm);
429    TCGv immh  = tcg_constant_tl(-(imm < 0));
430    tcg_gen_add2_tl(retl, reth, srcl, srch, imml, immh);
431}
432
433static bool trans_addi(DisasContext *ctx, arg_addi *a)
434{
435    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, gen_addi2_i128);
436}
437
438static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
439{
440    tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
441}
442
443static void gen_slt_i128(TCGv retl, TCGv reth,
444                         TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h)
445{
446    gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LT);
447}
448
449static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
450{
451    tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
452}
453
454static void gen_sltu_i128(TCGv retl, TCGv reth,
455                          TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h)
456{
457    gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LTU);
458}
459
460static bool trans_slti(DisasContext *ctx, arg_slti *a)
461{
462    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt, gen_slt_i128);
463}
464
465static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
466{
467    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu, gen_sltu_i128);
468}
469
470static bool trans_xori(DisasContext *ctx, arg_xori *a)
471{
472    return gen_logic_imm_fn(ctx, a, tcg_gen_xori_tl);
473}
474
475static bool trans_ori(DisasContext *ctx, arg_ori *a)
476{
477    return gen_logic_imm_fn(ctx, a, tcg_gen_ori_tl);
478}
479
480static bool trans_andi(DisasContext *ctx, arg_andi *a)
481{
482    return gen_logic_imm_fn(ctx, a, tcg_gen_andi_tl);
483}
484
485static void gen_slli_i128(TCGv retl, TCGv reth,
486                          TCGv src1l, TCGv src1h,
487                          target_long shamt)
488{
489    if (shamt >= 64) {
490        tcg_gen_shli_tl(reth, src1l, shamt - 64);
491        tcg_gen_movi_tl(retl, 0);
492    } else {
493        tcg_gen_extract2_tl(reth, src1l, src1h, 64 - shamt);
494        tcg_gen_shli_tl(retl, src1l, shamt);
495    }
496}
497
498static bool trans_slli(DisasContext *ctx, arg_slli *a)
499{
500    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, gen_slli_i128);
501}
502
503static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
504{
505    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
506}
507
508static void gen_srli_i128(TCGv retl, TCGv reth,
509                          TCGv src1l, TCGv src1h,
510                          target_long shamt)
511{
512    if (shamt >= 64) {
513        tcg_gen_shri_tl(retl, src1h, shamt - 64);
514        tcg_gen_movi_tl(reth, 0);
515    } else {
516        tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
517        tcg_gen_shri_tl(reth, src1h, shamt);
518    }
519}
520
521static bool trans_srli(DisasContext *ctx, arg_srli *a)
522{
523    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
524                                   tcg_gen_shri_tl, gen_srliw, gen_srli_i128);
525}
526
527static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
528{
529    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
530}
531
532static void gen_srai_i128(TCGv retl, TCGv reth,
533                          TCGv src1l, TCGv src1h,
534                          target_long shamt)
535{
536    if (shamt >= 64) {
537        tcg_gen_sari_tl(retl, src1h, shamt - 64);
538        tcg_gen_sari_tl(reth, src1h, 63);
539    } else {
540        tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
541        tcg_gen_sari_tl(reth, src1h, shamt);
542    }
543}
544
545static bool trans_srai(DisasContext *ctx, arg_srai *a)
546{
547    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
548                                   tcg_gen_sari_tl, gen_sraiw, gen_srai_i128);
549}
550
551static bool trans_add(DisasContext *ctx, arg_add *a)
552{
553    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, tcg_gen_add2_tl);
554}
555
556static bool trans_sub(DisasContext *ctx, arg_sub *a)
557{
558    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, tcg_gen_sub2_tl);
559}
560
561static void gen_sll_i128(TCGv destl, TCGv desth,
562                         TCGv src1l, TCGv src1h, TCGv shamt)
563{
564    TCGv ls = tcg_temp_new();
565    TCGv rs = tcg_temp_new();
566    TCGv hs = tcg_temp_new();
567    TCGv ll = tcg_temp_new();
568    TCGv lr = tcg_temp_new();
569    TCGv h0 = tcg_temp_new();
570    TCGv h1 = tcg_temp_new();
571    TCGv zero = tcg_constant_tl(0);
572
573    tcg_gen_andi_tl(hs, shamt, 64);
574    tcg_gen_andi_tl(ls, shamt, 63);
575    tcg_gen_neg_tl(shamt, shamt);
576    tcg_gen_andi_tl(rs, shamt, 63);
577
578    tcg_gen_shl_tl(ll, src1l, ls);
579    tcg_gen_shl_tl(h0, src1h, ls);
580    tcg_gen_shr_tl(lr, src1l, rs);
581    tcg_gen_movcond_tl(TCG_COND_NE, lr, shamt, zero, lr, zero);
582    tcg_gen_or_tl(h1, h0, lr);
583
584    tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, zero, ll);
585    tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, ll, h1);
586
587    tcg_temp_free(ls);
588    tcg_temp_free(rs);
589    tcg_temp_free(hs);
590    tcg_temp_free(ll);
591    tcg_temp_free(lr);
592    tcg_temp_free(h0);
593    tcg_temp_free(h1);
594}
595
596static bool trans_sll(DisasContext *ctx, arg_sll *a)
597{
598    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, gen_sll_i128);
599}
600
601static bool trans_slt(DisasContext *ctx, arg_slt *a)
602{
603    return gen_arith(ctx, a, EXT_SIGN, gen_slt, gen_slt_i128);
604}
605
606static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
607{
608    return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu_i128);
609}
610
611static void gen_srl_i128(TCGv destl, TCGv desth,
612                         TCGv src1l, TCGv src1h, TCGv shamt)
613{
614    TCGv ls = tcg_temp_new();
615    TCGv rs = tcg_temp_new();
616    TCGv hs = tcg_temp_new();
617    TCGv ll = tcg_temp_new();
618    TCGv lr = tcg_temp_new();
619    TCGv h0 = tcg_temp_new();
620    TCGv h1 = tcg_temp_new();
621    TCGv zero = tcg_constant_tl(0);
622
623    tcg_gen_andi_tl(hs, shamt, 64);
624    tcg_gen_andi_tl(rs, shamt, 63);
625    tcg_gen_neg_tl(shamt, shamt);
626    tcg_gen_andi_tl(ls, shamt, 63);
627
628    tcg_gen_shr_tl(lr, src1l, rs);
629    tcg_gen_shr_tl(h1, src1h, rs);
630    tcg_gen_shl_tl(ll, src1h, ls);
631    tcg_gen_movcond_tl(TCG_COND_NE, ll, shamt, zero, ll, zero);
632    tcg_gen_or_tl(h0, ll, lr);
633
634    tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0);
635    tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, zero, h1);
636
637    tcg_temp_free(ls);
638    tcg_temp_free(rs);
639    tcg_temp_free(hs);
640    tcg_temp_free(ll);
641    tcg_temp_free(lr);
642    tcg_temp_free(h0);
643    tcg_temp_free(h1);
644}
645
646static bool trans_srl(DisasContext *ctx, arg_srl *a)
647{
648    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, gen_srl_i128);
649}
650
651static void gen_sra_i128(TCGv destl, TCGv desth,
652                         TCGv src1l, TCGv src1h, TCGv shamt)
653{
654    TCGv ls = tcg_temp_new();
655    TCGv rs = tcg_temp_new();
656    TCGv hs = tcg_temp_new();
657    TCGv ll = tcg_temp_new();
658    TCGv lr = tcg_temp_new();
659    TCGv h0 = tcg_temp_new();
660    TCGv h1 = tcg_temp_new();
661    TCGv zero = tcg_constant_tl(0);
662
663    tcg_gen_andi_tl(hs, shamt, 64);
664    tcg_gen_andi_tl(rs, shamt, 63);
665    tcg_gen_neg_tl(shamt, shamt);
666    tcg_gen_andi_tl(ls, shamt, 63);
667
668    tcg_gen_shr_tl(lr, src1l, rs);
669    tcg_gen_sar_tl(h1, src1h, rs);
670    tcg_gen_shl_tl(ll, src1h, ls);
671    tcg_gen_movcond_tl(TCG_COND_NE, ll, shamt, zero, ll, zero);
672    tcg_gen_or_tl(h0, ll, lr);
673    tcg_gen_sari_tl(lr, src1h, 63);
674
675    tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0);
676    tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, lr, h1);
677
678    tcg_temp_free(ls);
679    tcg_temp_free(rs);
680    tcg_temp_free(hs);
681    tcg_temp_free(ll);
682    tcg_temp_free(lr);
683    tcg_temp_free(h0);
684    tcg_temp_free(h1);
685}
686
687static bool trans_sra(DisasContext *ctx, arg_sra *a)
688{
689    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, gen_sra_i128);
690}
691
692static bool trans_xor(DisasContext *ctx, arg_xor *a)
693{
694    return gen_logic(ctx, a, tcg_gen_xor_tl);
695}
696
697static bool trans_or(DisasContext *ctx, arg_or *a)
698{
699    return gen_logic(ctx, a, tcg_gen_or_tl);
700}
701
702static bool trans_and(DisasContext *ctx, arg_and *a)
703{
704    return gen_logic(ctx, a, tcg_gen_and_tl);
705}
706
707static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
708{
709    REQUIRE_64_OR_128BIT(ctx);
710    ctx->ol = MXL_RV32;
711    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, NULL);
712}
713
714static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
715{
716    REQUIRE_64_OR_128BIT(ctx);
717    ctx->ol = MXL_RV32;
718    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL);
719}
720
721static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
722{
723    REQUIRE_64_OR_128BIT(ctx);
724    ctx->ol = MXL_RV32;
725    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw, NULL);
726}
727
728static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
729{
730    REQUIRE_64_OR_128BIT(ctx);
731    ctx->ol = MXL_RV32;
732    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw, NULL);
733}
734
735static bool trans_sllid(DisasContext *ctx, arg_sllid *a)
736{
737    REQUIRE_128BIT(ctx);
738    ctx->ol = MXL_RV64;
739    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL);
740}
741
742static bool trans_srlid(DisasContext *ctx, arg_srlid *a)
743{
744    REQUIRE_128BIT(ctx);
745    ctx->ol = MXL_RV64;
746    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shri_tl, NULL);
747}
748
749static bool trans_sraid(DisasContext *ctx, arg_sraid *a)
750{
751    REQUIRE_128BIT(ctx);
752    ctx->ol = MXL_RV64;
753    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_sari_tl,  NULL);
754}
755
756static bool trans_addw(DisasContext *ctx, arg_addw *a)
757{
758    REQUIRE_64_OR_128BIT(ctx);
759    ctx->ol = MXL_RV32;
760    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, NULL);
761}
762
763static bool trans_subw(DisasContext *ctx, arg_subw *a)
764{
765    REQUIRE_64_OR_128BIT(ctx);
766    ctx->ol = MXL_RV32;
767    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, NULL);
768}
769
770static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
771{
772    REQUIRE_64_OR_128BIT(ctx);
773    ctx->ol = MXL_RV32;
774    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL);
775}
776
777static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
778{
779    REQUIRE_64_OR_128BIT(ctx);
780    ctx->ol = MXL_RV32;
781    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL);
782}
783
784static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
785{
786    REQUIRE_64_OR_128BIT(ctx);
787    ctx->ol = MXL_RV32;
788    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
789}
790
791static bool trans_slld(DisasContext *ctx, arg_slld *a)
792{
793    REQUIRE_128BIT(ctx);
794    ctx->ol = MXL_RV64;
795    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL);
796}
797
798static bool trans_srld(DisasContext *ctx, arg_srld *a)
799{
800    REQUIRE_128BIT(ctx);
801    ctx->ol = MXL_RV64;
802    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL);
803}
804
805static bool trans_srad(DisasContext *ctx, arg_srad *a)
806{
807    REQUIRE_128BIT(ctx);
808    ctx->ol = MXL_RV64;
809    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
810}
811
812
813static bool trans_fence(DisasContext *ctx, arg_fence *a)
814{
815    /* FENCE is a full memory barrier. */
816    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
817    return true;
818}
819
820static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
821{
822    if (!ctx->ext_ifencei) {
823        return false;
824    }
825
826    /*
827     * FENCE_I is a no-op in QEMU,
828     * however we need to end the translation block
829     */
830    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
831    tcg_gen_exit_tb(NULL, 0);
832    ctx->base.is_jmp = DISAS_NORETURN;
833    return true;
834}
835
836static bool do_csr_post(DisasContext *ctx)
837{
838    /* We may have changed important cpu state -- exit to main loop. */
839    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
840    tcg_gen_exit_tb(NULL, 0);
841    ctx->base.is_jmp = DISAS_NORETURN;
842    return true;
843}
844
845static bool do_csrr(DisasContext *ctx, int rd, int rc)
846{
847    TCGv dest = dest_gpr(ctx, rd);
848    TCGv_i32 csr = tcg_constant_i32(rc);
849
850    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
851        gen_io_start();
852    }
853    gen_helper_csrr(dest, cpu_env, csr);
854    gen_set_gpr(ctx, rd, dest);
855    return do_csr_post(ctx);
856}
857
858static bool do_csrw(DisasContext *ctx, int rc, TCGv src)
859{
860    TCGv_i32 csr = tcg_constant_i32(rc);
861
862    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
863        gen_io_start();
864    }
865    gen_helper_csrw(cpu_env, csr, src);
866    return do_csr_post(ctx);
867}
868
869static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask)
870{
871    TCGv dest = dest_gpr(ctx, rd);
872    TCGv_i32 csr = tcg_constant_i32(rc);
873
874    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
875        gen_io_start();
876    }
877    gen_helper_csrrw(dest, cpu_env, csr, src, mask);
878    gen_set_gpr(ctx, rd, dest);
879    return do_csr_post(ctx);
880}
881
882static bool do_csrr_i128(DisasContext *ctx, int rd, int rc)
883{
884    TCGv destl = dest_gpr(ctx, rd);
885    TCGv desth = dest_gprh(ctx, rd);
886    TCGv_i32 csr = tcg_constant_i32(rc);
887
888    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
889        gen_io_start();
890    }
891    gen_helper_csrr_i128(destl, cpu_env, csr);
892    tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh));
893    gen_set_gpr128(ctx, rd, destl, desth);
894    return do_csr_post(ctx);
895}
896
897static bool do_csrw_i128(DisasContext *ctx, int rc, TCGv srcl, TCGv srch)
898{
899    TCGv_i32 csr = tcg_constant_i32(rc);
900
901    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
902        gen_io_start();
903    }
904    gen_helper_csrw_i128(cpu_env, csr, srcl, srch);
905    return do_csr_post(ctx);
906}
907
908static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
909                          TCGv srcl, TCGv srch, TCGv maskl, TCGv maskh)
910{
911    TCGv destl = dest_gpr(ctx, rd);
912    TCGv desth = dest_gprh(ctx, rd);
913    TCGv_i32 csr = tcg_constant_i32(rc);
914
915    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
916        gen_io_start();
917    }
918    gen_helper_csrrw_i128(destl, cpu_env, csr, srcl, srch, maskl, maskh);
919    tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh));
920    gen_set_gpr128(ctx, rd, destl, desth);
921    return do_csr_post(ctx);
922}
923
924static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
925{
926    if (get_xl(ctx) < MXL_RV128) {
927        TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
928
929        /*
930         * If rd == 0, the insn shall not read the csr, nor cause any of the
931         * side effects that might occur on a csr read.
932         */
933        if (a->rd == 0) {
934            return do_csrw(ctx, a->csr, src);
935        }
936
937        TCGv mask = tcg_constant_tl(-1);
938        return do_csrrw(ctx, a->rd, a->csr, src, mask);
939    } else {
940        TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
941        TCGv srch = get_gprh(ctx, a->rs1);
942
943        /*
944         * If rd == 0, the insn shall not read the csr, nor cause any of the
945         * side effects that might occur on a csr read.
946         */
947        if (a->rd == 0) {
948            return do_csrw_i128(ctx, a->csr, srcl, srch);
949        }
950
951        TCGv mask = tcg_constant_tl(-1);
952        return do_csrrw_i128(ctx, a->rd, a->csr, srcl, srch, mask, mask);
953    }
954}
955
956static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
957{
958    /*
959     * If rs1 == 0, the insn shall not write to the csr at all, nor
960     * cause any of the side effects that might occur on a csr write.
961     * Note that if rs1 specifies a register other than x0, holding
962     * a zero value, the instruction will still attempt to write the
963     * unmodified value back to the csr and will cause side effects.
964     */
965    if (get_xl(ctx) < MXL_RV128) {
966        if (a->rs1 == 0) {
967            return do_csrr(ctx, a->rd, a->csr);
968        }
969
970        TCGv ones = tcg_constant_tl(-1);
971        TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
972        return do_csrrw(ctx, a->rd, a->csr, ones, mask);
973    } else {
974        if (a->rs1 == 0) {
975            return do_csrr_i128(ctx, a->rd, a->csr);
976        }
977
978        TCGv ones = tcg_constant_tl(-1);
979        TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
980        TCGv maskh = get_gprh(ctx, a->rs1);
981        return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, maskl, maskh);
982    }
983}
984
985static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
986{
987    /*
988     * If rs1 == 0, the insn shall not write to the csr at all, nor
989     * cause any of the side effects that might occur on a csr write.
990     * Note that if rs1 specifies a register other than x0, holding
991     * a zero value, the instruction will still attempt to write the
992     * unmodified value back to the csr and will cause side effects.
993     */
994    if (get_xl(ctx) < MXL_RV128) {
995        if (a->rs1 == 0) {
996            return do_csrr(ctx, a->rd, a->csr);
997        }
998
999        TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
1000        return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
1001    } else {
1002        if (a->rs1 == 0) {
1003            return do_csrr_i128(ctx, a->rd, a->csr);
1004        }
1005
1006        TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
1007        TCGv maskh = get_gprh(ctx, a->rs1);
1008        return do_csrrw_i128(ctx, a->rd, a->csr,
1009                             ctx->zero, ctx->zero, maskl, maskh);
1010    }
1011}
1012
1013static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
1014{
1015    if (get_xl(ctx) < MXL_RV128) {
1016        TCGv src = tcg_constant_tl(a->rs1);
1017
1018        /*
1019         * If rd == 0, the insn shall not read the csr, nor cause any of the
1020         * side effects that might occur on a csr read.
1021         */
1022        if (a->rd == 0) {
1023            return do_csrw(ctx, a->csr, src);
1024        }
1025
1026        TCGv mask = tcg_constant_tl(-1);
1027        return do_csrrw(ctx, a->rd, a->csr, src, mask);
1028    } else {
1029        TCGv src = tcg_constant_tl(a->rs1);
1030
1031        /*
1032         * If rd == 0, the insn shall not read the csr, nor cause any of the
1033         * side effects that might occur on a csr read.
1034         */
1035        if (a->rd == 0) {
1036            return do_csrw_i128(ctx, a->csr, src, ctx->zero);
1037        }
1038
1039        TCGv mask = tcg_constant_tl(-1);
1040        return do_csrrw_i128(ctx, a->rd, a->csr, src, ctx->zero, mask, mask);
1041    }
1042}
1043
1044static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
1045{
1046    /*
1047     * If rs1 == 0, the insn shall not write to the csr at all, nor
1048     * cause any of the side effects that might occur on a csr write.
1049     * Note that if rs1 specifies a register other than x0, holding
1050     * a zero value, the instruction will still attempt to write the
1051     * unmodified value back to the csr and will cause side effects.
1052     */
1053    if (get_xl(ctx) < MXL_RV128) {
1054        if (a->rs1 == 0) {
1055            return do_csrr(ctx, a->rd, a->csr);
1056        }
1057
1058        TCGv ones = tcg_constant_tl(-1);
1059        TCGv mask = tcg_constant_tl(a->rs1);
1060        return do_csrrw(ctx, a->rd, a->csr, ones, mask);
1061    } else {
1062        if (a->rs1 == 0) {
1063            return do_csrr_i128(ctx, a->rd, a->csr);
1064        }
1065
1066        TCGv ones = tcg_constant_tl(-1);
1067        TCGv mask = tcg_constant_tl(a->rs1);
1068        return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, mask, ctx->zero);
1069    }
1070}
1071
1072static bool trans_csrrci(DisasContext *ctx, arg_csrrci * a)
1073{
1074    /*
1075     * If rs1 == 0, the insn shall not write to the csr at all, nor
1076     * cause any of the side effects that might occur on a csr write.
1077     * Note that if rs1 specifies a register other than x0, holding
1078     * a zero value, the instruction will still attempt to write the
1079     * unmodified value back to the csr and will cause side effects.
1080     */
1081    if (get_xl(ctx) < MXL_RV128) {
1082        if (a->rs1 == 0) {
1083            return do_csrr(ctx, a->rd, a->csr);
1084        }
1085
1086        TCGv mask = tcg_constant_tl(a->rs1);
1087        return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
1088    } else {
1089        if (a->rs1 == 0) {
1090            return do_csrr_i128(ctx, a->rd, a->csr);
1091        }
1092
1093        TCGv mask = tcg_constant_tl(a->rs1);
1094        return do_csrrw_i128(ctx, a->rd, a->csr,
1095                             ctx->zero, ctx->zero, mask, ctx->zero);
1096    }
1097}
1098